1 // SPDX-License-Identifier: GPL-2.0
3 * NAND Flash Controller Device Driver
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017 Socionext Inc.
7 * Reworked by Masahiro Yamada <yamada.masahiro@socionext.com>
10 #include <linux/bitfield.h>
11 #include <linux/completion.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
23 #define DENALI_NAND_NAME "denali-nand"
24 #define DENALI_DEFAULT_OOB_SKIP_BYTES 8
26 /* for Indexed Addressing */
27 #define DENALI_INDEXED_CTRL 0x00
28 #define DENALI_INDEXED_DATA 0x10
30 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
31 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
32 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
33 #define DENALI_MAP11 (3 << 26) /* direct controller access */
35 /* MAP11 access cycle type */
36 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
37 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
38 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
40 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
42 #define DENALI_INVALID_BANK -1
43 #define DENALI_NR_BANKS 4
45 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
47 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
50 static struct denali_nand_info *to_denali(struct nand_chip *chip)
52 return container_of(chip, struct denali_nand_info, nand);
56 * Direct Addressing - the slave address forms the control information (command
57 * type, bank, block, and page address). The slave data is the actual data to
58 * be transferred. This mode requires 28 bits of address region allocated.
60 static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
62 return ioread32(denali->host + addr);
65 static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
68 iowrite32(data, denali->host + addr);
72 * Indexed Addressing - address translation module intervenes in passing the
73 * control information. This mode reduces the required address range. The
74 * control information and transferred data are latched by the registers in
75 * the translation module.
77 static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
79 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
80 return ioread32(denali->host + DENALI_INDEXED_DATA);
83 static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
86 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
87 iowrite32(data, denali->host + DENALI_INDEXED_DATA);
91 * Use the configuration feature register to determine the maximum number of
92 * banks that the hardware supports.
94 static void denali_detect_max_banks(struct denali_nand_info *denali)
96 uint32_t features = ioread32(denali->reg + FEATURES);
98 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
100 /* the encoding changed from rev 5.0 to 5.1 */
101 if (denali->revision < 0x0501)
102 denali->max_banks <<= 1;
105 static void denali_enable_irq(struct denali_nand_info *denali)
109 for (i = 0; i < DENALI_NR_BANKS; i++)
110 iowrite32(U32_MAX, denali->reg + INTR_EN(i));
111 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
114 static void denali_disable_irq(struct denali_nand_info *denali)
118 for (i = 0; i < DENALI_NR_BANKS; i++)
119 iowrite32(0, denali->reg + INTR_EN(i));
120 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
123 static void denali_clear_irq(struct denali_nand_info *denali,
124 int bank, uint32_t irq_status)
126 /* write one to clear bits */
127 iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
130 static void denali_clear_irq_all(struct denali_nand_info *denali)
134 for (i = 0; i < DENALI_NR_BANKS; i++)
135 denali_clear_irq(denali, i, U32_MAX);
138 static irqreturn_t denali_isr(int irq, void *dev_id)
140 struct denali_nand_info *denali = dev_id;
141 irqreturn_t ret = IRQ_NONE;
145 spin_lock(&denali->irq_lock);
147 for (i = 0; i < DENALI_NR_BANKS; i++) {
148 irq_status = ioread32(denali->reg + INTR_STATUS(i));
152 denali_clear_irq(denali, i, irq_status);
154 if (i != denali->active_bank)
157 denali->irq_status |= irq_status;
159 if (denali->irq_status & denali->irq_mask)
160 complete(&denali->complete);
163 spin_unlock(&denali->irq_lock);
168 static void denali_reset_irq(struct denali_nand_info *denali)
172 spin_lock_irqsave(&denali->irq_lock, flags);
173 denali->irq_status = 0;
174 denali->irq_mask = 0;
175 spin_unlock_irqrestore(&denali->irq_lock, flags);
178 static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
181 unsigned long time_left, flags;
184 spin_lock_irqsave(&denali->irq_lock, flags);
186 irq_status = denali->irq_status;
188 if (irq_mask & irq_status) {
189 /* return immediately if the IRQ has already happened. */
190 spin_unlock_irqrestore(&denali->irq_lock, flags);
194 denali->irq_mask = irq_mask;
195 reinit_completion(&denali->complete);
196 spin_unlock_irqrestore(&denali->irq_lock, flags);
198 time_left = wait_for_completion_timeout(&denali->complete,
199 msecs_to_jiffies(1000));
201 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
206 return denali->irq_status;
209 static void denali_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
211 struct mtd_info *mtd = nand_to_mtd(chip);
212 struct denali_nand_info *denali = mtd_to_denali(mtd);
213 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
216 for (i = 0; i < len; i++)
217 buf[i] = denali->host_read(denali, addr);
220 static void denali_write_buf(struct nand_chip *chip, const uint8_t *buf,
223 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
224 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
227 for (i = 0; i < len; i++)
228 denali->host_write(denali, addr, buf[i]);
231 static void denali_read_buf16(struct nand_chip *chip, uint8_t *buf, int len)
233 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
234 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
235 uint16_t *buf16 = (uint16_t *)buf;
238 for (i = 0; i < len / 2; i++)
239 buf16[i] = denali->host_read(denali, addr);
242 static void denali_write_buf16(struct nand_chip *chip, const uint8_t *buf,
245 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
246 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
247 const uint16_t *buf16 = (const uint16_t *)buf;
250 for (i = 0; i < len / 2; i++)
251 denali->host_write(denali, addr, buf16[i]);
254 static uint8_t denali_read_byte(struct nand_chip *chip)
258 denali_read_buf(chip, &byte, 1);
263 static void denali_write_byte(struct nand_chip *chip, uint8_t byte)
265 denali_write_buf(chip, &byte, 1);
268 static void denali_cmd_ctrl(struct nand_chip *chip, int dat, unsigned int ctrl)
270 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
274 type = DENALI_MAP11_CMD;
275 else if (ctrl & NAND_ALE)
276 type = DENALI_MAP11_ADDR;
281 * Some commands are followed by chip->legacy.waitfunc.
282 * irq_status must be cleared here to catch the R/B# interrupt later.
284 if (ctrl & NAND_CTRL_CHANGE)
285 denali_reset_irq(denali);
287 denali->host_write(denali, DENALI_BANK(denali) | type, dat);
290 static int denali_change_column(struct nand_chip *chip, unsigned int offset,
291 void *buf, unsigned int len, bool write)
294 return nand_change_write_column_op(chip, offset, buf, len,
297 return nand_change_read_column_op(chip, offset, buf, len,
301 static int denali_payload_xfer(struct nand_chip *chip, void *buf, bool write)
303 struct denali_nand_info *denali = to_denali(chip);
304 struct mtd_info *mtd = nand_to_mtd(chip);
305 struct nand_ecc_ctrl *ecc = &chip->ecc;
306 int writesize = mtd->writesize;
307 int oob_skip = denali->oob_skip_bytes;
308 int ret, i, pos, len;
310 for (i = 0; i < ecc->steps; i++) {
311 pos = i * (ecc->size + ecc->bytes);
314 if (pos >= writesize) {
316 } else if (pos + len > writesize) {
317 /* This chunk overwraps the BBM area. Must be split */
318 ret = denali_change_column(chip, pos, buf,
319 writesize - pos, write);
323 buf += writesize - pos;
324 len -= writesize - pos;
325 pos = writesize + oob_skip;
328 ret = denali_change_column(chip, pos, buf, len, write);
338 static int denali_oob_xfer(struct nand_chip *chip, void *buf, bool write)
340 struct denali_nand_info *denali = to_denali(chip);
341 struct mtd_info *mtd = nand_to_mtd(chip);
342 struct nand_ecc_ctrl *ecc = &chip->ecc;
343 int writesize = mtd->writesize;
344 int oobsize = mtd->oobsize;
345 int oob_skip = denali->oob_skip_bytes;
346 int ret, i, pos, len;
348 /* BBM at the beginning of the OOB area */
349 ret = denali_change_column(chip, writesize, buf, oob_skip, write);
355 for (i = 0; i < ecc->steps; i++) {
356 pos = ecc->size + i * (ecc->size + ecc->bytes);
358 if (i == ecc->steps - 1)
359 /* The last chunk includes OOB free */
360 len = writesize + oobsize - pos - oob_skip;
364 if (pos >= writesize) {
366 } else if (pos + len > writesize) {
367 /* This chunk overwraps the BBM area. Must be split */
368 ret = denali_change_column(chip, pos, buf,
369 writesize - pos, write);
373 buf += writesize - pos;
374 len -= writesize - pos;
375 pos = writesize + oob_skip;
378 ret = denali_change_column(chip, pos, buf, len, write);
388 static int denali_read_raw(struct nand_chip *chip, void *buf, void *oob_buf,
393 if (!buf && !oob_buf)
396 ret = nand_read_page_op(chip, page, 0, NULL, 0);
401 ret = denali_payload_xfer(chip, buf, false);
407 ret = denali_oob_xfer(chip, oob_buf, false);
415 static int denali_write_raw(struct nand_chip *chip, const void *buf,
416 const void *oob_buf, int page)
420 if (!buf && !oob_buf)
423 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
428 ret = denali_payload_xfer(chip, (void *)buf, true);
434 ret = denali_oob_xfer(chip, (void *)oob_buf, true);
439 return nand_prog_page_end_op(chip);
442 static int denali_read_page_raw(struct nand_chip *chip, u8 *buf,
443 int oob_required, int page)
445 return denali_read_raw(chip, buf, oob_required ? chip->oob_poi : NULL,
449 static int denali_write_page_raw(struct nand_chip *chip, const u8 *buf,
450 int oob_required, int page)
452 return denali_write_raw(chip, buf, oob_required ? chip->oob_poi : NULL,
456 static int denali_read_oob(struct nand_chip *chip, int page)
458 return denali_read_raw(chip, NULL, chip->oob_poi, page);
461 static int denali_write_oob(struct nand_chip *chip, int page)
463 return denali_write_raw(chip, NULL, chip->oob_poi, page);
466 static int denali_check_erased_page(struct nand_chip *chip, u8 *buf,
467 unsigned long uncor_ecc_flags,
468 unsigned int max_bitflips)
470 struct denali_nand_info *denali = to_denali(chip);
471 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats;
472 uint8_t *ecc_code = chip->oob_poi + denali->oob_skip_bytes;
473 int ecc_steps = chip->ecc.steps;
474 int ecc_size = chip->ecc.size;
475 int ecc_bytes = chip->ecc.bytes;
478 for (i = 0; i < ecc_steps; i++) {
479 if (!(uncor_ecc_flags & BIT(i)))
482 stat = nand_check_erased_ecc_chunk(buf, ecc_size,
489 ecc_stats->corrected += stat;
490 max_bitflips = max_t(unsigned int, max_bitflips, stat);
494 ecc_code += ecc_bytes;
500 static int denali_hw_ecc_fixup(struct nand_chip *chip,
501 unsigned long *uncor_ecc_flags)
503 struct denali_nand_info *denali = to_denali(chip);
504 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats;
505 int bank = denali->active_bank;
507 unsigned int max_bitflips;
509 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
510 ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
512 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
514 * This flag is set when uncorrectable error occurs at least in
515 * one ECC sector. We can not know "how many sectors", or
516 * "which sector(s)". We need erase-page check for all sectors.
518 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
522 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
525 * The register holds the maximum of per-sector corrected bitflips.
526 * This is suitable for the return value of the ->read_page() callback.
527 * Unfortunately, we can not know the total number of corrected bits in
528 * the page. Increase the stats by max_bitflips. (compromised solution)
530 ecc_stats->corrected += max_bitflips;
535 static int denali_sw_ecc_fixup(struct nand_chip *chip,
536 unsigned long *uncor_ecc_flags, uint8_t *buf)
538 struct denali_nand_info *denali = to_denali(chip);
539 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats;
540 unsigned int ecc_size = chip->ecc.size;
541 unsigned int bitflips = 0;
542 unsigned int max_bitflips = 0;
543 uint32_t err_addr, err_cor_info;
544 unsigned int err_byte, err_sector, err_device;
545 uint8_t err_cor_value;
546 unsigned int prev_sector = 0;
549 denali_reset_irq(denali);
552 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
553 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
554 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
556 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
557 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
559 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
562 /* reset the bitflip counter when crossing ECC sector */
563 if (err_sector != prev_sector)
566 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
568 * Check later if this is a real ECC error, or
571 *uncor_ecc_flags |= BIT(err_sector);
572 } else if (err_byte < ecc_size) {
574 * If err_byte is larger than ecc_size, means error
575 * happened in OOB, so we ignore it. It's no need for
576 * us to correct it err_device is represented the NAND
577 * error bits are happened in if there are more than
578 * one NAND connected.
581 unsigned int flips_in_byte;
583 offset = (err_sector * ecc_size + err_byte) *
584 denali->devs_per_cs + err_device;
586 /* correct the ECC error */
587 flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
588 buf[offset] ^= err_cor_value;
589 ecc_stats->corrected += flips_in_byte;
590 bitflips += flips_in_byte;
592 max_bitflips = max(max_bitflips, bitflips);
595 prev_sector = err_sector;
596 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
599 * Once handle all ECC errors, controller will trigger an
600 * ECC_TRANSACTION_DONE interrupt.
602 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
603 if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
609 static void denali_setup_dma64(struct denali_nand_info *denali,
610 dma_addr_t dma_addr, int page, int write)
613 const int page_count = 1;
615 mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
617 /* DMA is a three step process */
620 * 1. setup transfer type, interrupt when complete,
621 * burst len = 64 bytes, the number of pages
623 denali->host_write(denali, mode,
624 0x01002000 | (64 << 16) | (write << 8) | page_count);
626 /* 2. set memory low address */
627 denali->host_write(denali, mode, lower_32_bits(dma_addr));
629 /* 3. set memory high address */
630 denali->host_write(denali, mode, upper_32_bits(dma_addr));
633 static void denali_setup_dma32(struct denali_nand_info *denali,
634 dma_addr_t dma_addr, int page, int write)
637 const int page_count = 1;
639 mode = DENALI_MAP10 | DENALI_BANK(denali);
641 /* DMA is a four step process */
643 /* 1. setup transfer type and # of pages */
644 denali->host_write(denali, mode | page,
645 0x2000 | (write << 8) | page_count);
647 /* 2. set memory high address bits 23:8 */
648 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
650 /* 3. set memory low address bits 23:8 */
651 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
653 /* 4. interrupt when complete, burst len = 64 bytes */
654 denali->host_write(denali, mode | 0x14000, 0x2400);
657 static int denali_pio_read(struct denali_nand_info *denali, void *buf,
658 size_t size, int page)
660 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
661 uint32_t *buf32 = (uint32_t *)buf;
662 uint32_t irq_status, ecc_err_mask;
665 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
666 ecc_err_mask = INTR__ECC_UNCOR_ERR;
668 ecc_err_mask = INTR__ECC_ERR;
670 denali_reset_irq(denali);
672 for (i = 0; i < size / 4; i++)
673 *buf32++ = denali->host_read(denali, addr);
675 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
676 if (!(irq_status & INTR__PAGE_XFER_INC))
679 if (irq_status & INTR__ERASED_PAGE)
680 memset(buf, 0xff, size);
682 return irq_status & ecc_err_mask ? -EBADMSG : 0;
685 static int denali_pio_write(struct denali_nand_info *denali,
686 const void *buf, size_t size, int page)
688 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
689 const uint32_t *buf32 = (uint32_t *)buf;
693 denali_reset_irq(denali);
695 for (i = 0; i < size / 4; i++)
696 denali->host_write(denali, addr, *buf32++);
698 irq_status = denali_wait_for_irq(denali,
699 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
700 if (!(irq_status & INTR__PROGRAM_COMP))
706 static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
707 size_t size, int page, int write)
710 return denali_pio_write(denali, buf, size, page);
712 return denali_pio_read(denali, buf, size, page);
715 static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
716 size_t size, int page, int write)
719 uint32_t irq_mask, irq_status, ecc_err_mask;
720 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
723 dma_addr = dma_map_single(denali->dev, buf, size, dir);
724 if (dma_mapping_error(denali->dev, dma_addr)) {
725 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
726 return denali_pio_xfer(denali, buf, size, page, write);
731 * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
732 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
733 * when the page program is completed.
735 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
737 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
738 irq_mask = INTR__DMA_CMD_COMP;
739 ecc_err_mask = INTR__ECC_UNCOR_ERR;
741 irq_mask = INTR__DMA_CMD_COMP;
742 ecc_err_mask = INTR__ECC_ERR;
745 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
747 * The ->setup_dma() hook kicks DMA by using the data/command
748 * interface, which belongs to a different AXI port from the
749 * register interface. Read back the register to avoid a race.
751 ioread32(denali->reg + DMA_ENABLE);
753 denali_reset_irq(denali);
754 denali->setup_dma(denali, dma_addr, page, write);
756 irq_status = denali_wait_for_irq(denali, irq_mask);
757 if (!(irq_status & INTR__DMA_CMD_COMP))
759 else if (irq_status & ecc_err_mask)
762 iowrite32(0, denali->reg + DMA_ENABLE);
764 dma_unmap_single(denali->dev, dma_addr, size, dir);
766 if (irq_status & INTR__ERASED_PAGE)
767 memset(buf, 0xff, size);
772 static int denali_page_xfer(struct nand_chip *chip, void *buf, size_t size,
775 struct denali_nand_info *denali = to_denali(chip);
777 if (denali->dma_avail)
778 return denali_dma_xfer(denali, buf, size, page, write);
780 return denali_pio_xfer(denali, buf, size, page, write);
783 static int denali_read_page(struct nand_chip *chip, uint8_t *buf,
784 int oob_required, int page)
786 struct mtd_info *mtd = nand_to_mtd(chip);
787 struct denali_nand_info *denali = mtd_to_denali(mtd);
788 unsigned long uncor_ecc_flags = 0;
792 ret = denali_page_xfer(chip, buf, mtd->writesize, page, 0);
793 if (ret && ret != -EBADMSG)
796 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
797 stat = denali_hw_ecc_fixup(chip, &uncor_ecc_flags);
798 else if (ret == -EBADMSG)
799 stat = denali_sw_ecc_fixup(chip, &uncor_ecc_flags, buf);
804 if (uncor_ecc_flags) {
805 ret = denali_read_oob(chip, page);
809 stat = denali_check_erased_page(chip, buf,
810 uncor_ecc_flags, stat);
816 static int denali_write_page(struct nand_chip *chip, const uint8_t *buf,
817 int oob_required, int page)
819 struct mtd_info *mtd = nand_to_mtd(chip);
821 return denali_page_xfer(chip, (void *)buf, mtd->writesize, page, 1);
824 static void denali_select_chip(struct nand_chip *chip, int cs)
826 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
828 denali->active_bank = cs;
831 static int denali_waitfunc(struct nand_chip *chip)
833 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
836 /* R/B# pin transitioned from low to high? */
837 irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
839 return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
842 static int denali_setup_data_interface(struct nand_chip *chip, int chipnr,
843 const struct nand_data_interface *conf)
845 struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
846 const struct nand_sdr_timings *timings;
847 unsigned long t_x, mult_x;
848 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
849 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
850 int addr_2_data_mask;
853 timings = nand_get_sdr_timings(conf);
855 return PTR_ERR(timings);
857 /* clk_x period in picoseconds */
858 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
863 * The bus interface clock, clk_x, is phase aligned with the core clock.
864 * The clk_x is an integral multiple N of the core clk. The value N is
865 * configured at IP delivery time, and its available value is 4, 5, 6.
867 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
868 if (mult_x < 4 || mult_x > 6)
871 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
874 /* tREA -> ACC_CLKS */
875 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x);
876 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
878 tmp = ioread32(denali->reg + ACC_CLKS);
879 tmp &= ~ACC_CLKS__VALUE;
880 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
881 iowrite32(tmp, denali->reg + ACC_CLKS);
883 /* tRWH -> RE_2_WE */
884 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
885 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
887 tmp = ioread32(denali->reg + RE_2_WE);
888 tmp &= ~RE_2_WE__VALUE;
889 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
890 iowrite32(tmp, denali->reg + RE_2_WE);
892 /* tRHZ -> RE_2_RE */
893 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
894 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
896 tmp = ioread32(denali->reg + RE_2_RE);
897 tmp &= ~RE_2_RE__VALUE;
898 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
899 iowrite32(tmp, denali->reg + RE_2_RE);
902 * tCCS, tWHR -> WE_2_RE
904 * With WE_2_RE properly set, the Denali controller automatically takes
905 * care of the delay; the driver need not set NAND_WAIT_TCCS.
907 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
908 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
910 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
911 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
912 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
913 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
915 /* tADL -> ADDR_2_DATA */
917 /* for older versions, ADDR_2_DATA is only 6 bit wide */
918 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
919 if (denali->revision < 0x0501)
920 addr_2_data_mask >>= 1;
922 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x);
923 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
925 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
926 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
927 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
928 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
930 /* tREH, tWH -> RDWR_EN_HI_CNT */
931 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
933 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
935 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
936 tmp &= ~RDWR_EN_HI_CNT__VALUE;
937 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
938 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
940 /* tRP, tWP -> RDWR_EN_LO_CNT */
941 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x);
942 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
944 rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x);
945 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
946 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
948 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
949 tmp &= ~RDWR_EN_LO_CNT__VALUE;
950 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
951 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
953 /* tCS, tCEA -> CS_SETUP_CNT */
954 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
955 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks,
957 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
959 tmp = ioread32(denali->reg + CS_SETUP_CNT);
960 tmp &= ~CS_SETUP_CNT__VALUE;
961 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
962 iowrite32(tmp, denali->reg + CS_SETUP_CNT);
967 static void denali_hw_init(struct denali_nand_info *denali)
970 * The REVISION register may not be reliable. Platforms are allowed to
973 if (!denali->revision)
974 denali->revision = swab16(ioread32(denali->reg + REVISION));
977 * Set how many bytes should be skipped before writing data in OOB.
978 * If a non-zero value has already been set (by firmware or something),
979 * just use it. Otherwise, set the driver default.
981 denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES);
982 if (!denali->oob_skip_bytes) {
983 denali->oob_skip_bytes = DENALI_DEFAULT_OOB_SKIP_BYTES;
984 iowrite32(denali->oob_skip_bytes,
985 denali->reg + SPARE_AREA_SKIP_BYTES);
988 denali_detect_max_banks(denali);
989 iowrite32(0, denali->reg + TRANSFER_SPARE_REG);
990 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
991 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
992 iowrite32(ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
993 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
996 int denali_calc_ecc_bytes(int step_size, int strength)
998 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
999 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
1001 EXPORT_SYMBOL(denali_calc_ecc_bytes);
1003 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
1004 struct mtd_oob_region *oobregion)
1006 struct denali_nand_info *denali = mtd_to_denali(mtd);
1007 struct nand_chip *chip = mtd_to_nand(mtd);
1012 oobregion->offset = denali->oob_skip_bytes;
1013 oobregion->length = chip->ecc.total;
1018 static int denali_ooblayout_free(struct mtd_info *mtd, int section,
1019 struct mtd_oob_region *oobregion)
1021 struct denali_nand_info *denali = mtd_to_denali(mtd);
1022 struct nand_chip *chip = mtd_to_nand(mtd);
1027 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
1028 oobregion->length = mtd->oobsize - oobregion->offset;
1033 static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
1034 .ecc = denali_ooblayout_ecc,
1035 .free = denali_ooblayout_free,
1038 static int denali_multidev_fixup(struct nand_chip *chip)
1040 struct denali_nand_info *denali = to_denali(chip);
1041 struct mtd_info *mtd = nand_to_mtd(chip);
1042 struct nand_memory_organization *memorg;
1044 memorg = nanddev_get_memorg(&chip->base);
1047 * Support for multi device:
1048 * When the IP configuration is x16 capable and two x8 chips are
1049 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1050 * In this case, the core framework knows nothing about this fact,
1051 * so we should tell it the _logical_ pagesize and anything necessary.
1053 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
1056 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1057 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1059 if (denali->devs_per_cs == 0) {
1060 denali->devs_per_cs = 1;
1061 iowrite32(1, denali->reg + DEVICES_CONNECTED);
1064 if (denali->devs_per_cs == 1)
1067 if (denali->devs_per_cs != 2) {
1068 dev_err(denali->dev, "unsupported number of devices %d\n",
1069 denali->devs_per_cs);
1073 /* 2 chips in parallel */
1074 memorg->pagesize <<= 1;
1075 memorg->oobsize <<= 1;
1077 mtd->erasesize <<= 1;
1078 mtd->writesize <<= 1;
1080 chip->page_shift += 1;
1081 chip->phys_erase_shift += 1;
1082 chip->bbt_erase_shift += 1;
1083 chip->chip_shift += 1;
1084 chip->pagemask <<= 1;
1085 chip->ecc.size <<= 1;
1086 chip->ecc.bytes <<= 1;
1087 chip->ecc.strength <<= 1;
1088 denali->oob_skip_bytes <<= 1;
1093 static int denali_attach_chip(struct nand_chip *chip)
1095 struct mtd_info *mtd = nand_to_mtd(chip);
1096 struct denali_nand_info *denali = mtd_to_denali(mtd);
1099 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
1100 denali->dma_avail = 1;
1102 if (denali->dma_avail) {
1103 int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32;
1105 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit));
1107 dev_info(denali->dev,
1108 "Failed to set DMA mask. Disabling DMA.\n");
1109 denali->dma_avail = 0;
1113 if (denali->dma_avail) {
1114 chip->options |= NAND_USE_BOUNCE_BUFFER;
1115 chip->buf_align = 16;
1116 if (denali->caps & DENALI_CAP_DMA_64BIT)
1117 denali->setup_dma = denali_setup_dma64;
1119 denali->setup_dma = denali_setup_dma32;
1122 chip->bbt_options |= NAND_BBT_USE_FLASH;
1123 chip->bbt_options |= NAND_BBT_NO_OOB;
1124 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
1125 chip->options |= NAND_NO_SUBPAGE_WRITE;
1127 ret = nand_ecc_choose_conf(chip, denali->ecc_caps,
1128 mtd->oobsize - denali->oob_skip_bytes);
1130 dev_err(denali->dev, "Failed to setup ECC settings.\n");
1134 dev_dbg(denali->dev,
1135 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
1136 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
1138 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
1139 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
1140 denali->reg + ECC_CORRECTION);
1141 iowrite32(mtd->erasesize / mtd->writesize,
1142 denali->reg + PAGES_PER_BLOCK);
1143 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
1144 denali->reg + DEVICE_WIDTH);
1145 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
1146 denali->reg + TWO_ROW_ADDR_CYCLES);
1147 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
1148 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
1150 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
1151 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
1152 /* chip->ecc.steps is set by nand_scan_tail(); not available here */
1153 iowrite32(mtd->writesize / chip->ecc.size,
1154 denali->reg + CFG_NUM_DATA_BLOCKS);
1156 mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
1158 if (chip->options & NAND_BUSWIDTH_16) {
1159 chip->legacy.read_buf = denali_read_buf16;
1160 chip->legacy.write_buf = denali_write_buf16;
1162 chip->legacy.read_buf = denali_read_buf;
1163 chip->legacy.write_buf = denali_write_buf;
1165 chip->ecc.read_page = denali_read_page;
1166 chip->ecc.read_page_raw = denali_read_page_raw;
1167 chip->ecc.write_page = denali_write_page;
1168 chip->ecc.write_page_raw = denali_write_page_raw;
1169 chip->ecc.read_oob = denali_read_oob;
1170 chip->ecc.write_oob = denali_write_oob;
1172 ret = denali_multidev_fixup(chip);
1179 static const struct nand_controller_ops denali_controller_ops = {
1180 .attach_chip = denali_attach_chip,
1181 .setup_data_interface = denali_setup_data_interface,
1184 int denali_init(struct denali_nand_info *denali)
1186 struct nand_chip *chip = &denali->nand;
1187 struct mtd_info *mtd = nand_to_mtd(chip);
1188 u32 features = ioread32(denali->reg + FEATURES);
1191 mtd->dev.parent = denali->dev;
1192 denali_hw_init(denali);
1194 init_completion(&denali->complete);
1195 spin_lock_init(&denali->irq_lock);
1197 denali_clear_irq_all(denali);
1199 ret = devm_request_irq(denali->dev, denali->irq, denali_isr,
1200 IRQF_SHARED, DENALI_NAND_NAME, denali);
1202 dev_err(denali->dev, "Unable to request IRQ\n");
1206 denali_enable_irq(denali);
1208 denali->active_bank = DENALI_INVALID_BANK;
1210 nand_set_flash_node(chip, denali->dev->of_node);
1211 /* Fallback to the default name if DT did not give "label" property */
1213 mtd->name = "denali-nand";
1215 chip->legacy.select_chip = denali_select_chip;
1216 chip->legacy.read_byte = denali_read_byte;
1217 chip->legacy.write_byte = denali_write_byte;
1218 chip->legacy.cmd_ctrl = denali_cmd_ctrl;
1219 chip->legacy.waitfunc = denali_waitfunc;
1221 if (features & FEATURES__INDEX_ADDR) {
1222 denali->host_read = denali_indexed_read;
1223 denali->host_write = denali_indexed_write;
1225 denali->host_read = denali_direct_read;
1226 denali->host_write = denali_direct_write;
1229 /* clk rate info is needed for setup_data_interface */
1230 if (!denali->clk_rate || !denali->clk_x_rate)
1231 chip->options |= NAND_KEEP_TIMINGS;
1233 chip->legacy.dummy_controller.ops = &denali_controller_ops;
1234 ret = nand_scan(chip, denali->max_banks);
1238 ret = mtd_device_register(mtd, NULL, 0);
1240 dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
1249 denali_disable_irq(denali);
1253 EXPORT_SYMBOL(denali_init);
1255 void denali_remove(struct denali_nand_info *denali)
1257 nand_release(&denali->nand);
1258 denali_disable_irq(denali);
1260 EXPORT_SYMBOL(denali_remove);
1262 MODULE_DESCRIPTION("Driver core for Denali NAND controller");
1263 MODULE_AUTHOR("Intel Corporation and its suppliers");
1264 MODULE_LICENSE("GPL v2");