drivers/mtd/nand/raw/atmel/nand-controller.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2017 ATMEL
   4  * Copyright 2017 Free Electrons
   5  *
   6  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   7  *
   8  * Derived from the atmel_nand.c driver which contained the following
   9  * copyrights:
  10  *
  11  *   Copyright 2003 Rick Bronson
  12  *
  13  *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
  14  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
  15  *
  16  *   Derived from drivers/mtd/spia.c (removed in v3.8)
  17  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
  18  *
  19  *
  20  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  21  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
  22  *
  23  *   Derived from Das U-Boot source code
  24  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  25  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  26  *
  27  *   Add Programmable Multibit ECC support for various AT91 SoC
  28  *      Copyright 2012 ATMEL, Hong Xu
  29  *
  30  *   Add Nand Flash Controller support for SAMA5 SoC
  31  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
  32  *
  33  * A few words about the naming convention in this file. This convention
  34  * applies to structure and function names.
  35  *
  36  * Prefixes:
  37  *
  38  * - atmel_nand_: all generic structures/functions
  39  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
  40  *                    (at91sam9 and avr32 SoCs)
  41  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
  42  *                     (sama5 SoCs and later)
  43  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
  44  *               that is available in the HSMC block
  45  * - <soc>_nand_: all SoC specific structures/functions
  46  */
  47
  48 #include <linux/clk.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/genalloc.h>
  52 #include <linux/gpio/consumer.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/mfd/syscon.h>
  55 #include <linux/mfd/syscon/atmel-matrix.h>
  56 #include <linux/mfd/syscon/atmel-smc.h>
  57 #include <linux/module.h>
  58 #include <linux/mtd/rawnand.h>
  59 #include <linux/of_address.h>
  60 #include <linux/of_irq.h>
  61 #include <linux/of_platform.h>
  62 #include <linux/iopoll.h>
  63 #include <linux/platform_device.h>
  64 #include <linux/regmap.h>
  65 #include <soc/at91/atmel-sfr.h>
  66
  67 #include "pmecc.h"
  68
  69 #define ATMEL_HSMC_NFC_CFG                      0x0
  70 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
  71 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
  72 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
  73 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
  74 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
  75 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
  76 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
  77 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
  78 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
  79 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
  80
  81 #define ATMEL_HSMC_NFC_CTRL                     0x4
  82 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
  83 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
  84
  85 #define ATMEL_HSMC_NFC_SR                       0x8
  86 #define ATMEL_HSMC_NFC_IER                      0xc
  87 #define ATMEL_HSMC_NFC_IDR                      0x10
  88 #define ATMEL_HSMC_NFC_IMR                      0x14
  89 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
  90 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
  91 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
  92 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
  93 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
  94 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
  95 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
  96 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
  97 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
  98 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
  99 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
 100 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
 101 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
 102                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
 103                                                  ATMEL_HSMC_NFC_SR_AWB | \
 104                                                  ATMEL_HSMC_NFC_SR_NFCASE)
 105 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
 106
 107 #define ATMEL_HSMC_NFC_ADDR                     0x18
 108 #define ATMEL_HSMC_NFC_BANK                     0x1c
 109
 110 #define ATMEL_NFC_MAX_RB_ID                     7
 111
 112 #define ATMEL_NFC_SRAM_SIZE                     0x2400
 113
 114 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
 115 #define ATMEL_NFC_VCMD2                         BIT(18)
 116 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
 117 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
 118 #define ATMEL_NFC_DATAEN                        BIT(25)
 119 #define ATMEL_NFC_NFCWR                         BIT(26)
 120
 121 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
 122
 123 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
 124 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
 125
 126 #define DEFAULT_TIMEOUT_MS                      1000
 127 #define MIN_DMA_LEN                             128
 128
 129 static bool atmel_nand_avoid_dma __read_mostly;
 130
 131 MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
 132 module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
 133
 134 enum atmel_nand_rb_type {
 135         ATMEL_NAND_NO_RB,
 136         ATMEL_NAND_NATIVE_RB,
 137         ATMEL_NAND_GPIO_RB,
 138 };
 139
 140 struct atmel_nand_rb {
 141         enum atmel_nand_rb_type type;
 142         union {
 143                 struct gpio_desc *gpio;
 144                 int id;
 145         };
 146 };
 147
 148 struct atmel_nand_cs {
 149         int id;
 150         struct atmel_nand_rb rb;
 151         struct gpio_desc *csgpio;
 152         struct {
 153                 void __iomem *virt;
 154                 dma_addr_t dma;
 155         } io;
 156
 157         struct atmel_smc_cs_conf smcconf;
 158 };
 159
 160 struct atmel_nand {
 161         struct list_head node;
 162         struct device *dev;
 163         struct nand_chip base;
 164         struct atmel_nand_cs *activecs;
 165         struct atmel_pmecc_user *pmecc;
 166         struct gpio_desc *cdgpio;
 167         int numcs;
 168         struct atmel_nand_cs cs[];
 169 };
 170
 171 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
 172 {
 173         return container_of(chip, struct atmel_nand, base);
 174 }
 175
 176 enum atmel_nfc_data_xfer {
 177         ATMEL_NFC_NO_DATA,
 178         ATMEL_NFC_READ_DATA,
 179         ATMEL_NFC_WRITE_DATA,
 180 };
 181
 182 struct atmel_nfc_op {
 183         u8 cs;
 184         u8 ncmds;
 185         u8 cmds[2];
 186         u8 naddrs;
 187         u8 addrs[5];
 188         enum atmel_nfc_data_xfer data;
 189         u32 wait;
 190         u32 errors;
 191 };
 192
 193 struct atmel_nand_controller;
 194 struct atmel_nand_controller_caps;
 195
 196 struct atmel_nand_controller_ops {
 197         int (*probe)(struct platform_device *pdev,
 198                      const struct atmel_nand_controller_caps *caps);
 199         int (*remove)(struct atmel_nand_controller *nc);
 200         void (*nand_init)(struct atmel_nand_controller *nc,
 201                           struct atmel_nand *nand);
 202         int (*ecc_init)(struct nand_chip *chip);
 203         int (*setup_interface)(struct atmel_nand *nand, int csline,
 204                                const struct nand_interface_config *conf);
 205 };
 206
 207 struct atmel_nand_controller_caps {
 208         bool has_dma;
 209         bool legacy_of_bindings;
 210         u32 ale_offs;
 211         u32 cle_offs;
 212         const char *ebi_csa_regmap_name;
 213         const struct atmel_nand_controller_ops *ops;
 214 };
 215
 216 struct atmel_nand_controller {
 217         struct nand_controller base;
 218         const struct atmel_nand_controller_caps *caps;
 219         struct device *dev;
 220         struct regmap *smc;
 221         struct dma_chan *dmac;
 222         struct atmel_pmecc *pmecc;
 223         struct list_head chips;
 224         struct clk *mck;
 225 };
 226
 227 static inline struct atmel_nand_controller *
 228 to_nand_controller(struct nand_controller *ctl)
 229 {
 230         return container_of(ctl, struct atmel_nand_controller, base);
 231 }
 232
 233 struct atmel_smc_nand_ebi_csa_cfg {
 234         u32 offs;
 235         u32 nfd0_on_d16;
 236 };
 237
 238 struct atmel_smc_nand_controller {
 239         struct atmel_nand_controller base;
 240         struct regmap *ebi_csa_regmap;
 241         struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
 242 };
 243
 244 static inline struct atmel_smc_nand_controller *
 245 to_smc_nand_controller(struct nand_controller *ctl)
 246 {
 247         return container_of(to_nand_controller(ctl),
 248                             struct atmel_smc_nand_controller, base);
 249 }
 250
 251 struct atmel_hsmc_nand_controller {
 252         struct atmel_nand_controller base;
 253         struct {
 254                 struct gen_pool *pool;
 255                 void __iomem *virt;
 256                 dma_addr_t dma;
 257         } sram;
 258         const struct atmel_hsmc_reg_layout *hsmc_layout;
 259         struct regmap *io;
 260         struct atmel_nfc_op op;
 261         struct completion complete;
 262         int irq;
 263
 264         /* Only used when instantiating from legacy DT bindings. */
 265         struct clk *clk;
 266 };
 267
 268 static inline struct atmel_hsmc_nand_controller *
 269 to_hsmc_nand_controller(struct nand_controller *ctl)
 270 {
 271         return container_of(to_nand_controller(ctl),
 272                             struct atmel_hsmc_nand_controller, base);
 273 }
 274
 275 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
 276 {
 277         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
 278         op->wait ^= status & op->wait;
 279
 280         return !op->wait || op->errors;
 281 }
 282
 283 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
 284 {
 285         struct atmel_hsmc_nand_controller *nc = data;
 286         u32 sr, rcvd;
 287         bool done;
 288
 289         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
 290
 291         rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 292         done = atmel_nfc_op_done(&nc->op, sr);
 293
 294         if (rcvd)
 295                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
 296
 297         if (done)
 298                 complete(&nc->complete);
 299
 300         return rcvd ? IRQ_HANDLED : IRQ_NONE;
 301 }
 302
 303 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
 304                           unsigned int timeout_ms)
 305 {
 306         int ret;
 307
 308         if (!timeout_ms)
 309                 timeout_ms = DEFAULT_TIMEOUT_MS;
 310
 311         if (poll) {
 312                 u32 status;
 313
 314                 ret = regmap_read_poll_timeout(nc->base.smc,
 315                                                ATMEL_HSMC_NFC_SR, status,
 316                                                atmel_nfc_op_done(&nc->op,
 317                                                                  status),
 318                                                0, timeout_ms * 1000);
 319         } else {
 320                 init_completion(&nc->complete);
 321                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
 322                              nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 323                 ret = wait_for_completion_timeout(&nc->complete,
 324                                                 msecs_to_jiffies(timeout_ms));
 325                 if (!ret)
 326                         ret = -ETIMEDOUT;
 327                 else
 328                         ret = 0;
 329
 330                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
 331         }
 332
 333         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
 334                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
 335                 ret = -ETIMEDOUT;
 336         }
 337
 338         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
 339                 dev_err(nc->base.dev, "Access to an undefined area\n");
 340                 ret = -EIO;
 341         }
 342
 343         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
 344                 dev_err(nc->base.dev, "Access while busy\n");
 345                 ret = -EIO;
 346         }
 347
 348         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
 349                 dev_err(nc->base.dev, "Wrong access size\n");
 350                 ret = -EIO;
 351         }
 352
 353         return ret;
 354 }
 355
 356 static void atmel_nand_dma_transfer_finished(void *data)
 357 {
 358         struct completion *finished = data;
 359
 360         complete(finished);
 361 }
 362
 363 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
 364                                    void *buf, dma_addr_t dev_dma, size_t len,
 365                                    enum dma_data_direction dir)
 366 {
 367         DECLARE_COMPLETION_ONSTACK(finished);
 368         dma_addr_t src_dma, dst_dma, buf_dma;
 369         struct dma_async_tx_descriptor *tx;
 370         dma_cookie_t cookie;
 371
 372         buf_dma = dma_map_single(nc->dev, buf, len, dir);
 373         if (dma_mapping_error(nc->dev, dev_dma)) {
 374                 dev_err(nc->dev,
 375                         "Failed to prepare a buffer for DMA access\n");
 376                 goto err;
 377         }
 378
 379         if (dir == DMA_FROM_DEVICE) {
 380                 src_dma = dev_dma;
 381                 dst_dma = buf_dma;
 382         } else {
 383                 src_dma = buf_dma;
 384                 dst_dma = dev_dma;
 385         }
 386
 387         tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
 388                                        DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
 389         if (!tx) {
 390                 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
 391                 goto err_unmap;
 392         }
 393
 394         tx->callback = atmel_nand_dma_transfer_finished;
 395         tx->callback_param = &finished;
 396
 397         cookie = dmaengine_submit(tx);
 398         if (dma_submit_error(cookie)) {
 399                 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
 400                 goto err_unmap;
 401         }
 402
 403         dma_async_issue_pending(nc->dmac);
 404         wait_for_completion(&finished);
 405
 406         return 0;
 407
 408 err_unmap:
 409         dma_unmap_single(nc->dev, buf_dma, len, dir);
 410
 411 err:
 412         dev_dbg(nc->dev, "Fall back to CPU I/O\n");
 413
 414         return -EIO;
 415 }
 416
 417 static u8 atmel_nand_read_byte(struct nand_chip *chip)
 418 {
 419         struct atmel_nand *nand = to_atmel_nand(chip);
 420
 421         return ioread8(nand->activecs->io.virt);
 422 }
 423
 424 static void atmel_nand_write_byte(struct nand_chip *chip, u8 byte)
 425 {
 426         struct atmel_nand *nand = to_atmel_nand(chip);
 427
 428         if (chip->options & NAND_BUSWIDTH_16)
 429                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
 430         else
 431                 iowrite8(byte, nand->activecs->io.virt);
 432 }
 433
 434 static void atmel_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
 435 {
 436         struct atmel_nand *nand = to_atmel_nand(chip);
 437         struct atmel_nand_controller *nc;
 438
 439         nc = to_nand_controller(chip->controller);
 440
 441         /*
 442          * If the controller supports DMA, the buffer address is DMA-able and
 443          * len is long enough to make DMA transfers profitable, let's trigger
 444          * a DMA transfer. If it fails, fallback to PIO mode.
 445          */
 446         if (nc->dmac && virt_addr_valid(buf) &&
 447             len >= MIN_DMA_LEN &&
 448             !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
 449                                      DMA_FROM_DEVICE))
 450                 return;
 451
 452         if (chip->options & NAND_BUSWIDTH_16)
 453                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
 454         else
 455                 ioread8_rep(nand->activecs->io.virt, buf, len);
 456 }
 457
 458 static void atmel_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
 459 {
 460         struct atmel_nand *nand = to_atmel_nand(chip);
 461         struct atmel_nand_controller *nc;
 462
 463         nc = to_nand_controller(chip->controller);
 464
 465         /*
 466          * If the controller supports DMA, the buffer address is DMA-able and
 467          * len is long enough to make DMA transfers profitable, let's trigger
 468          * a DMA transfer. If it fails, fallback to PIO mode.
 469          */
 470         if (nc->dmac && virt_addr_valid(buf) &&
 471             len >= MIN_DMA_LEN &&
 472             !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
 473                                      len, DMA_TO_DEVICE))
 474                 return;
 475
 476         if (chip->options & NAND_BUSWIDTH_16)
 477                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
 478         else
 479                 iowrite8_rep(nand->activecs->io.virt, buf, len);
 480 }
 481
 482 static int atmel_nand_dev_ready(struct nand_chip *chip)
 483 {
 484         struct atmel_nand *nand = to_atmel_nand(chip);
 485
 486         return gpiod_get_value(nand->activecs->rb.gpio);
 487 }
 488
 489 static void atmel_nand_select_chip(struct nand_chip *chip, int cs)
 490 {
 491         struct atmel_nand *nand = to_atmel_nand(chip);
 492
 493         if (cs < 0 || cs >= nand->numcs) {
 494                 nand->activecs = NULL;
 495                 chip->legacy.dev_ready = NULL;
 496                 return;
 497         }
 498
 499         nand->activecs = &nand->cs[cs];
 500
 501         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
 502                 chip->legacy.dev_ready = atmel_nand_dev_ready;
 503 }
 504
 505 static int atmel_hsmc_nand_dev_ready(struct nand_chip *chip)
 506 {
 507         struct atmel_nand *nand = to_atmel_nand(chip);
 508         struct atmel_hsmc_nand_controller *nc;
 509         u32 status;
 510
 511         nc = to_hsmc_nand_controller(chip->controller);
 512
 513         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
 514
 515         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 516 }
 517
 518 static void atmel_hsmc_nand_select_chip(struct nand_chip *chip, int cs)
 519 {
 520         struct mtd_info *mtd = nand_to_mtd(chip);
 521         struct atmel_nand *nand = to_atmel_nand(chip);
 522         struct atmel_hsmc_nand_controller *nc;
 523
 524         nc = to_hsmc_nand_controller(chip->controller);
 525
 526         atmel_nand_select_chip(chip, cs);
 527
 528         if (!nand->activecs) {
 529                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 530                              ATMEL_HSMC_NFC_CTRL_DIS);
 531                 return;
 532         }
 533
 534         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
 535                 chip->legacy.dev_ready = atmel_hsmc_nand_dev_ready;
 536
 537         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
 538                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
 539                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
 540                            ATMEL_HSMC_NFC_CFG_RSPARE |
 541                            ATMEL_HSMC_NFC_CFG_WSPARE,
 542                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
 543                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
 544                            ATMEL_HSMC_NFC_CFG_RSPARE);
 545         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 546                      ATMEL_HSMC_NFC_CTRL_EN);
 547 }
 548
 549 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
 550 {
 551         u8 *addrs = nc->op.addrs;
 552         unsigned int op = 0;
 553         u32 addr, val;
 554         int i, ret;
 555
 556         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
 557
 558         for (i = 0; i < nc->op.ncmds; i++)
 559                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
 560
 561         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 562                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
 563
 564         op |= ATMEL_NFC_CSID(nc->op.cs) |
 565               ATMEL_NFC_ACYCLE(nc->op.naddrs);
 566
 567         if (nc->op.ncmds > 1)
 568                 op |= ATMEL_NFC_VCMD2;
 569
 570         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
 571                (addrs[3] << 24);
 572
 573         if (nc->op.data != ATMEL_NFC_NO_DATA) {
 574                 op |= ATMEL_NFC_DATAEN;
 575                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
 576
 577                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
 578                         op |= ATMEL_NFC_NFCWR;
 579         }
 580
 581         /* Clear all flags. */
 582         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
 583
 584         /* Send the command. */
 585         regmap_write(nc->io, op, addr);
 586
 587         ret = atmel_nfc_wait(nc, poll, 0);
 588         if (ret)
 589                 dev_err(nc->base.dev,
 590                         "Failed to send NAND command (err = %d)!",
 591                         ret);
 592
 593         /* Reset the op state. */
 594         memset(&nc->op, 0, sizeof(nc->op));
 595
 596         return ret;
 597 }
 598
 599 static void atmel_hsmc_nand_cmd_ctrl(struct nand_chip *chip, int dat,
 600                                      unsigned int ctrl)
 601 {
 602         struct atmel_nand *nand = to_atmel_nand(chip);
 603         struct atmel_hsmc_nand_controller *nc;
 604
 605         nc = to_hsmc_nand_controller(chip->controller);
 606
 607         if (ctrl & NAND_ALE) {
 608                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 609                         return;
 610
 611                 nc->op.addrs[nc->op.naddrs++] = dat;
 612         } else if (ctrl & NAND_CLE) {
 613                 if (nc->op.ncmds > 1)
 614                         return;
 615
 616                 nc->op.cmds[nc->op.ncmds++] = dat;
 617         }
 618
 619         if (dat == NAND_CMD_NONE) {
 620                 nc->op.cs = nand->activecs->id;
 621                 atmel_nfc_exec_op(nc, true);
 622         }
 623 }
 624
 625 static void atmel_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
 626                                 unsigned int ctrl)
 627 {
 628         struct atmel_nand *nand = to_atmel_nand(chip);
 629         struct atmel_nand_controller *nc;
 630
 631         nc = to_nand_controller(chip->controller);
 632
 633         if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
 634                 if (ctrl & NAND_NCE)
 635                         gpiod_set_value(nand->activecs->csgpio, 0);
 636                 else
 637                         gpiod_set_value(nand->activecs->csgpio, 1);
 638         }
 639
 640         if (ctrl & NAND_ALE)
 641                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
 642         else if (ctrl & NAND_CLE)
 643                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
 644 }
 645
 646 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
 647                                    bool oob_required)
 648 {
 649         struct mtd_info *mtd = nand_to_mtd(chip);
 650         struct atmel_hsmc_nand_controller *nc;
 651         int ret = -EIO;
 652
 653         nc = to_hsmc_nand_controller(chip->controller);
 654
 655         if (nc->base.dmac)
 656                 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
 657                                               nc->sram.dma, mtd->writesize,
 658                                               DMA_TO_DEVICE);
 659
 660         /* Falling back to CPU copy. */
 661         if (ret)
 662                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
 663
 664         if (oob_required)
 665                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
 666                             mtd->oobsize);
 667 }
 668
 669 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
 670                                      bool oob_required)
 671 {
 672         struct mtd_info *mtd = nand_to_mtd(chip);
 673         struct atmel_hsmc_nand_controller *nc;
 674         int ret = -EIO;
 675
 676         nc = to_hsmc_nand_controller(chip->controller);
 677
 678         if (nc->base.dmac)
 679                 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
 680                                               mtd->writesize, DMA_FROM_DEVICE);
 681
 682         /* Falling back to CPU copy. */
 683         if (ret)
 684                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
 685
 686         if (oob_required)
 687                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
 688                               mtd->oobsize);
 689 }
 690
 691 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
 692 {
 693         struct mtd_info *mtd = nand_to_mtd(chip);
 694         struct atmel_hsmc_nand_controller *nc;
 695
 696         nc = to_hsmc_nand_controller(chip->controller);
 697
 698         if (column >= 0) {
 699                 nc->op.addrs[nc->op.naddrs++] = column;
 700
 701                 /*
 702                  * 2 address cycles for the column offset on large page NANDs.
 703                  */
 704                 if (mtd->writesize > 512)
 705                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
 706         }
 707
 708         if (page >= 0) {
 709                 nc->op.addrs[nc->op.naddrs++] = page;
 710                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
 711
 712                 if (chip->options & NAND_ROW_ADDR_3)
 713                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
 714         }
 715 }
 716
 717 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
 718 {
 719         struct atmel_nand *nand = to_atmel_nand(chip);
 720         struct atmel_nand_controller *nc;
 721         int ret;
 722
 723         nc = to_nand_controller(chip->controller);
 724
 725         if (raw)
 726                 return 0;
 727
 728         ret = atmel_pmecc_enable(nand->pmecc, op);
 729         if (ret)
 730                 dev_err(nc->dev,
 731                         "Failed to enable ECC engine (err = %d)\n", ret);
 732
 733         return ret;
 734 }
 735
 736 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
 737 {
 738         struct atmel_nand *nand = to_atmel_nand(chip);
 739
 740         if (!raw)
 741                 atmel_pmecc_disable(nand->pmecc);
 742 }
 743
 744 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
 745 {
 746         struct atmel_nand *nand = to_atmel_nand(chip);
 747         struct mtd_info *mtd = nand_to_mtd(chip);
 748         struct atmel_nand_controller *nc;
 749         struct mtd_oob_region oobregion;
 750         void *eccbuf;
 751         int ret, i;
 752
 753         nc = to_nand_controller(chip->controller);
 754
 755         if (raw)
 756                 return 0;
 757
 758         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 759         if (ret) {
 760                 dev_err(nc->dev,
 761                         "Failed to transfer NAND page data (err = %d)\n",
 762                         ret);
 763                 return ret;
 764         }
 765
 766         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 767         eccbuf = chip->oob_poi + oobregion.offset;
 768
 769         for (i = 0; i < chip->ecc.steps; i++) {
 770                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
 771                                                    eccbuf);
 772                 eccbuf += chip->ecc.bytes;
 773         }
 774
 775         return 0;
 776 }
 777
 778 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
 779                                          bool raw)
 780 {
 781         struct atmel_nand *nand = to_atmel_nand(chip);
 782         struct mtd_info *mtd = nand_to_mtd(chip);
 783         struct atmel_nand_controller *nc;
 784         struct mtd_oob_region oobregion;
 785         int ret, i, max_bitflips = 0;
 786         void *databuf, *eccbuf;
 787
 788         nc = to_nand_controller(chip->controller);
 789
 790         if (raw)
 791                 return 0;
 792
 793         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 794         if (ret) {
 795                 dev_err(nc->dev,
 796                         "Failed to read NAND page data (err = %d)\n",
 797                         ret);
 798                 return ret;
 799         }
 800
 801         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 802         eccbuf = chip->oob_poi + oobregion.offset;
 803         databuf = buf;
 804
 805         for (i = 0; i < chip->ecc.steps; i++) {
 806                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
 807                                                  eccbuf);
 808                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
 809                         ret = nand_check_erased_ecc_chunk(databuf,
 810                                                           chip->ecc.size,
 811                                                           eccbuf,
 812                                                           chip->ecc.bytes,
 813                                                           NULL, 0,
 814                                                           chip->ecc.strength);
 815
 816                 if (ret >= 0)
 817                         max_bitflips = max(ret, max_bitflips);
 818                 else
 819                         mtd->ecc_stats.failed++;
 820
 821                 databuf += chip->ecc.size;
 822                 eccbuf += chip->ecc.bytes;
 823         }
 824
 825         return max_bitflips;
 826 }
 827
 828 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 829                                      bool oob_required, int page, bool raw)
 830 {
 831         struct mtd_info *mtd = nand_to_mtd(chip);
 832         struct atmel_nand *nand = to_atmel_nand(chip);
 833         int ret;
 834
 835         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
 836
 837         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 838         if (ret)
 839                 return ret;
 840
 841         atmel_nand_write_buf(chip, buf, mtd->writesize);
 842
 843         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 844         if (ret) {
 845                 atmel_pmecc_disable(nand->pmecc);
 846                 return ret;
 847         }
 848
 849         atmel_nand_pmecc_disable(chip, raw);
 850
 851         atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize);
 852
 853         return nand_prog_page_end_op(chip);
 854 }
 855
 856 static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf,
 857                                        int oob_required, int page)
 858 {
 859         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 860 }
 861
 862 static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip,
 863                                            const u8 *buf, int oob_required,
 864                                            int page)
 865 {
 866         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
 867 }
 868
 869 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 870                                     bool oob_required, int page, bool raw)
 871 {
 872         struct mtd_info *mtd = nand_to_mtd(chip);
 873         int ret;
 874
 875         nand_read_page_op(chip, page, 0, NULL, 0);
 876
 877         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 878         if (ret)
 879                 return ret;
 880
 881         atmel_nand_read_buf(chip, buf, mtd->writesize);
 882         atmel_nand_read_buf(chip, chip->oob_poi, mtd->oobsize);
 883
 884         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 885
 886         atmel_nand_pmecc_disable(chip, raw);
 887
 888         return ret;
 889 }
 890
 891 static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
 892                                       int oob_required, int page)
 893 {
 894         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 895 }
 896
 897 static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf,
 898                                           int oob_required, int page)
 899 {
 900         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
 901 }
 902
 903 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
 904                                           const u8 *buf, bool oob_required,
 905                                           int page, bool raw)
 906 {
 907         struct mtd_info *mtd = nand_to_mtd(chip);
 908         struct atmel_nand *nand = to_atmel_nand(chip);
 909         struct atmel_hsmc_nand_controller *nc;
 910         int ret, status;
 911
 912         nc = to_hsmc_nand_controller(chip->controller);
 913
 914         atmel_nfc_copy_to_sram(chip, buf, false);
 915
 916         nc->op.cmds[0] = NAND_CMD_SEQIN;
 917         nc->op.ncmds = 1;
 918         atmel_nfc_set_op_addr(chip, page, 0x0);
 919         nc->op.cs = nand->activecs->id;
 920         nc->op.data = ATMEL_NFC_WRITE_DATA;
 921
 922         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 923         if (ret)
 924                 return ret;
 925
 926         ret = atmel_nfc_exec_op(nc, false);
 927         if (ret) {
 928                 atmel_nand_pmecc_disable(chip, raw);
 929                 dev_err(nc->base.dev,
 930                         "Failed to transfer NAND page data (err = %d)\n",
 931                         ret);
 932                 return ret;
 933         }
 934
 935         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 936
 937         atmel_nand_pmecc_disable(chip, raw);
 938
 939         if (ret)
 940                 return ret;
 941
 942         atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize);
 943
 944         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
 945         nc->op.ncmds = 1;
 946         nc->op.cs = nand->activecs->id;
 947         ret = atmel_nfc_exec_op(nc, false);
 948         if (ret)
 949                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
 950                         ret);
 951
 952         status = chip->legacy.waitfunc(chip);
 953         if (status & NAND_STATUS_FAIL)
 954                 return -EIO;
 955
 956         return ret;
 957 }
 958
 959 static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip,
 960                                             const u8 *buf, int oob_required,
 961                                             int page)
 962 {
 963         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 964                                               false);
 965 }
 966
 967 static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip,
 968                                                 const u8 *buf,
 969                                                 int oob_required, int page)
 970 {
 971         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 972                                               true);
 973 }
 974
 975 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 976                                          bool oob_required, int page,
 977                                          bool raw)
 978 {
 979         struct mtd_info *mtd = nand_to_mtd(chip);
 980         struct atmel_nand *nand = to_atmel_nand(chip);
 981         struct atmel_hsmc_nand_controller *nc;
 982         int ret;
 983
 984         nc = to_hsmc_nand_controller(chip->controller);
 985
 986         /*
 987          * Optimized read page accessors only work when the NAND R/B pin is
 988          * connected to a native SoC R/B pin. If that's not the case, fallback
 989          * to the non-optimized one.
 990          */
 991         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
 992                 nand_read_page_op(chip, page, 0, NULL, 0);
 993
 994                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
 995                                                 raw);
 996         }
 997
 998         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
 999
1000         if (mtd->writesize > 512)
1001                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1002
1003         atmel_nfc_set_op_addr(chip, page, 0x0);
1004         nc->op.cs = nand->activecs->id;
1005         nc->op.data = ATMEL_NFC_READ_DATA;
1006
1007         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1008         if (ret)
1009                 return ret;
1010
1011         ret = atmel_nfc_exec_op(nc, false);
1012         if (ret) {
1013                 atmel_nand_pmecc_disable(chip, raw);
1014                 dev_err(nc->base.dev,
1015                         "Failed to load NAND page data (err = %d)\n",
1016                         ret);
1017                 return ret;
1018         }
1019
1020         atmel_nfc_copy_from_sram(chip, buf, true);
1021
1022         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1023
1024         atmel_nand_pmecc_disable(chip, raw);
1025
1026         return ret;
1027 }
1028
1029 static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
1030                                            int oob_required, int page)
1031 {
1032         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1033                                              false);
1034 }
1035
1036 static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip,
1037                                                u8 *buf, int oob_required,
1038                                                int page)
1039 {
1040         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1041                                              true);
1042 }
1043
1044 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1045 {
1046         const struct nand_ecc_props *requirements =
1047                 nanddev_get_ecc_requirements(&chip->base);
1048         struct mtd_info *mtd = nand_to_mtd(chip);
1049         struct atmel_nand *nand = to_atmel_nand(chip);
1050         struct atmel_nand_controller *nc;
1051         struct atmel_pmecc_user_req req;
1052
1053         nc = to_nand_controller(chip->controller);
1054
1055         if (!nc->pmecc) {
1056                 dev_err(nc->dev, "HW ECC not supported\n");
1057                 return -ENOTSUPP;
1058         }
1059
1060         if (nc->caps->legacy_of_bindings) {
1061                 u32 val;
1062
1063                 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1064                                           &val))
1065                         chip->ecc.strength = val;
1066
1067                 if (!of_property_read_u32(nc->dev->of_node,
1068                                           "atmel,pmecc-sector-size",
1069                                           &val))
1070                         chip->ecc.size = val;
1071         }
1072
1073         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1074                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1075         else if (chip->ecc.strength)
1076                 req.ecc.strength = chip->ecc.strength;
1077         else if (requirements->strength)
1078                 req.ecc.strength = requirements->strength;
1079         else
1080                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1081
1082         if (chip->ecc.size)
1083                 req.ecc.sectorsize = chip->ecc.size;
1084         else if (requirements->step_size)
1085                 req.ecc.sectorsize = requirements->step_size;
1086         else
1087                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1088
1089         req.pagesize = mtd->writesize;
1090         req.oobsize = mtd->oobsize;
1091
1092         if (mtd->writesize <= 512) {
1093                 req.ecc.bytes = 4;
1094                 req.ecc.ooboffset = 0;
1095         } else {
1096                 req.ecc.bytes = mtd->oobsize - 2;
1097                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1098         }
1099
1100         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1101         if (IS_ERR(nand->pmecc))
1102                 return PTR_ERR(nand->pmecc);
1103
1104         chip->ecc.algo = NAND_ECC_ALGO_BCH;
1105         chip->ecc.size = req.ecc.sectorsize;
1106         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1107         chip->ecc.strength = req.ecc.strength;
1108
1109         chip->options |= NAND_NO_SUBPAGE_WRITE;
1110
1111         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1112
1113         return 0;
1114 }
1115
1116 static int atmel_nand_ecc_init(struct nand_chip *chip)
1117 {
1118         struct atmel_nand_controller *nc;
1119         int ret;
1120
1121         nc = to_nand_controller(chip->controller);
1122
1123         switch (chip->ecc.engine_type) {
1124         case NAND_ECC_ENGINE_TYPE_NONE:
1125         case NAND_ECC_ENGINE_TYPE_SOFT:
1126                 /*
1127                  * Nothing to do, the core will initialize everything for us.
1128                  */
1129                 break;
1130
1131         case NAND_ECC_ENGINE_TYPE_ON_HOST:
1132                 ret = atmel_nand_pmecc_init(chip);
1133                 if (ret)
1134                         return ret;
1135
1136                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1137                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1138                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1139                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1140                 break;
1141
1142         default:
1143                 /* Other modes are not supported. */
1144                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1145                         chip->ecc.engine_type);
1146                 return -ENOTSUPP;
1147         }
1148
1149         return 0;
1150 }
1151
1152 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1153 {
1154         int ret;
1155
1156         ret = atmel_nand_ecc_init(chip);
1157         if (ret)
1158                 return ret;
1159
1160         if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
1161                 return 0;
1162
1163         /* Adjust the ECC operations for the HSMC IP. */
1164         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1165         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1166         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1167         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1168
1169         return 0;
1170 }
1171
1172 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1173                                         const struct nand_interface_config *conf,
1174                                         struct atmel_smc_cs_conf *smcconf)
1175 {
1176         u32 ncycles, totalcycles, timeps, mckperiodps;
1177         struct atmel_nand_controller *nc;
1178         int ret;
1179
1180         nc = to_nand_controller(nand->base.controller);
1181
1182         /* DDR interface not supported. */
1183         if (conf->type != NAND_SDR_IFACE)
1184                 return -ENOTSUPP;
1185
1186         /*
1187          * tRC < 30ns implies EDO mode. This controller does not support this
1188          * mode.
1189          */
1190         if (conf->timings.sdr.tRC_min < 30000)
1191                 return -ENOTSUPP;
1192
1193         atmel_smc_cs_conf_init(smcconf);
1194
1195         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1196         mckperiodps *= 1000;
1197
1198         /*
1199          * Set write pulse timing. This one is easy to extract:
1200          *
1201          * NWE_PULSE = tWP
1202          */
1203         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1204         totalcycles = ncycles;
1205         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1206                                           ncycles);
1207         if (ret)
1208                 return ret;
1209
1210         /*
1211          * The write setup timing depends on the operation done on the NAND.
1212          * All operations goes through the same data bus, but the operation
1213          * type depends on the address we are writing to (ALE/CLE address
1214          * lines).
1215          * Since we have no way to differentiate the different operations at
1216          * the SMC level, we must consider the worst case (the biggest setup
1217          * time among all operation types):
1218          *
1219          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1220          */
1221         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1222                       conf->timings.sdr.tALS_min);
1223         timeps = max(timeps, conf->timings.sdr.tDS_min);
1224         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1225         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1226         totalcycles += ncycles;
1227         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1228                                           ncycles);
1229         if (ret)
1230                 return ret;
1231
1232         /*
1233          * As for the write setup timing, the write hold timing depends on the
1234          * operation done on the NAND:
1235          *
1236          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1237          */
1238         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1239                       conf->timings.sdr.tALH_min);
1240         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1241                       conf->timings.sdr.tWH_min);
1242         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1243         totalcycles += ncycles;
1244
1245         /*
1246          * The write cycle timing is directly matching tWC, but is also
1247          * dependent on the other timings on the setup and hold timings we
1248          * calculated earlier, which gives:
1249          *
1250          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1251          */
1252         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1253         ncycles = max(totalcycles, ncycles);
1254         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1255                                           ncycles);
1256         if (ret)
1257                 return ret;
1258
1259         /*
1260          * We don't want the CS line to be toggled between each byte/word
1261          * transfer to the NAND. The only way to guarantee that is to have the
1262          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1263          *
1264          * NCS_WR_PULSE = NWE_CYCLE
1265          */
1266         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1267                                           ncycles);
1268         if (ret)
1269                 return ret;
1270
1271         /*
1272          * As for the write setup timing, the read hold timing depends on the
1273          * operation done on the NAND:
1274          *
1275          * NRD_HOLD = max(tREH, tRHOH)
1276          */
1277         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1278         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1279         totalcycles = ncycles;
1280
1281         /*
1282          * TDF = tRHZ - NRD_HOLD
1283          */
1284         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1285         ncycles -= totalcycles;
1286
1287         /*
1288          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1289          * we might end up with a config that does not fit in the TDF field.
1290          * Just take the max value in this case and hope that the NAND is more
1291          * tolerant than advertised.
1292          */
1293         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1294                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1295         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1296                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1297
1298         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1299                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1300
1301         /*
1302          * Read pulse timing directly matches tRP:
1303          *
1304          * NRD_PULSE = tRP
1305          */
1306         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1307         totalcycles += ncycles;
1308         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1309                                           ncycles);
1310         if (ret)
1311                 return ret;
1312
1313         /*
1314          * The write cycle timing is directly matching tWC, but is also
1315          * dependent on the setup and hold timings we calculated earlier,
1316          * which gives:
1317          *
1318          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1319          *
1320          * NRD_SETUP is always 0.
1321          */
1322         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1323         ncycles = max(totalcycles, ncycles);
1324         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1325                                           ncycles);
1326         if (ret)
1327                 return ret;
1328
1329         /*
1330          * We don't want the CS line to be toggled between each byte/word
1331          * transfer from the NAND. The only way to guarantee that is to have
1332          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1333          *
1334          * NCS_RD_PULSE = NRD_CYCLE
1335          */
1336         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1337                                           ncycles);
1338         if (ret)
1339                 return ret;
1340
1341         /* Txxx timings are directly matching tXXX ones. */
1342         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1343         ret = atmel_smc_cs_conf_set_timing(smcconf,
1344                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1345                                            ncycles);
1346         if (ret)
1347                 return ret;
1348
1349         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1350         ret = atmel_smc_cs_conf_set_timing(smcconf,
1351                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1352                                            ncycles);
1353         /*
1354          * Version 4 of the ONFI spec mandates that tADL be at least 400
1355          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1356          * fit in the tADL field of the SMC reg. We need to relax the check and
1357          * accept the -ERANGE return code.
1358          *
1359          * Note that previous versions of the ONFI spec had a lower tADL_min
1360          * (100 or 200 ns). It's not clear why this timing constraint got
1361          * increased but it seems most NANDs are fine with values lower than
1362          * 400ns, so we should be safe.
1363          */
1364         if (ret && ret != -ERANGE)
1365                 return ret;
1366
1367         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1368         ret = atmel_smc_cs_conf_set_timing(smcconf,
1369                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1370                                            ncycles);
1371         if (ret)
1372                 return ret;
1373
1374         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1375         ret = atmel_smc_cs_conf_set_timing(smcconf,
1376                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1377                                            ncycles);
1378         if (ret)
1379                 return ret;
1380
1381         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1382         ret = atmel_smc_cs_conf_set_timing(smcconf,
1383                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1384                                            ncycles);
1385         if (ret)
1386                 return ret;
1387
1388         /* Attach the CS line to the NFC logic. */
1389         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1390
1391         /* Set the appropriate data bus width. */
1392         if (nand->base.options & NAND_BUSWIDTH_16)
1393                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1394
1395         /* Operate in NRD/NWE READ/WRITEMODE. */
1396         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1397                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1398
1399         return 0;
1400 }
1401
1402 static int atmel_smc_nand_setup_interface(struct atmel_nand *nand,
1403                                         int csline,
1404                                         const struct nand_interface_config *conf)
1405 {
1406         struct atmel_nand_controller *nc;
1407         struct atmel_smc_cs_conf smcconf;
1408         struct atmel_nand_cs *cs;
1409         int ret;
1410
1411         nc = to_nand_controller(nand->base.controller);
1412
1413         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1414         if (ret)
1415                 return ret;
1416
1417         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1418                 return 0;
1419
1420         cs = &nand->cs[csline];
1421         cs->smcconf = smcconf;
1422         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1423
1424         return 0;
1425 }
1426
1427 static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand,
1428                                         int csline,
1429                                         const struct nand_interface_config *conf)
1430 {
1431         struct atmel_hsmc_nand_controller *nc;
1432         struct atmel_smc_cs_conf smcconf;
1433         struct atmel_nand_cs *cs;
1434         int ret;
1435
1436         nc = to_hsmc_nand_controller(nand->base.controller);
1437
1438         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1439         if (ret)
1440                 return ret;
1441
1442         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1443                 return 0;
1444
1445         cs = &nand->cs[csline];
1446         cs->smcconf = smcconf;
1447
1448         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1449                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1450
1451         atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1452                                  &cs->smcconf);
1453
1454         return 0;
1455 }
1456
1457 static int atmel_nand_setup_interface(struct nand_chip *chip, int csline,
1458                                       const struct nand_interface_config *conf)
1459 {
1460         struct atmel_nand *nand = to_atmel_nand(chip);
1461         struct atmel_nand_controller *nc;
1462
1463         nc = to_nand_controller(nand->base.controller);
1464
1465         if (csline >= nand->numcs ||
1466             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1467                 return -EINVAL;
1468
1469         return nc->caps->ops->setup_interface(nand, csline, conf);
1470 }
1471
1472 static void atmel_nand_init(struct atmel_nand_controller *nc,
1473                             struct atmel_nand *nand)
1474 {
1475         struct nand_chip *chip = &nand->base;
1476         struct mtd_info *mtd = nand_to_mtd(chip);
1477
1478         mtd->dev.parent = nc->dev;
1479         nand->base.controller = &nc->base;
1480
1481         chip->legacy.cmd_ctrl = atmel_nand_cmd_ctrl;
1482         chip->legacy.read_byte = atmel_nand_read_byte;
1483         chip->legacy.write_byte = atmel_nand_write_byte;
1484         chip->legacy.read_buf = atmel_nand_read_buf;
1485         chip->legacy.write_buf = atmel_nand_write_buf;
1486         chip->legacy.select_chip = atmel_nand_select_chip;
1487
1488         if (!nc->mck || !nc->caps->ops->setup_interface)
1489                 chip->options |= NAND_KEEP_TIMINGS;
1490
1491         /* Some NANDs require a longer delay than the default one (20us). */
1492         chip->legacy.chip_delay = 40;
1493
1494         /*
1495          * Use a bounce buffer when the buffer passed by the MTD user is not
1496          * suitable for DMA.
1497          */
1498         if (nc->dmac)
1499                 chip->options |= NAND_USES_DMA;
1500
1501         /* Default to HW ECC if pmecc is available. */
1502         if (nc->pmecc)
1503                 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1504 }
1505
1506 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1507                                 struct atmel_nand *nand)
1508 {
1509         struct nand_chip *chip = &nand->base;
1510         struct atmel_smc_nand_controller *smc_nc;
1511         int i;
1512
1513         atmel_nand_init(nc, nand);
1514
1515         smc_nc = to_smc_nand_controller(chip->controller);
1516         if (!smc_nc->ebi_csa_regmap)
1517                 return;
1518
1519         /* Attach the CS to the NAND Flash logic. */
1520         for (i = 0; i < nand->numcs; i++)
1521                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1522                                    smc_nc->ebi_csa->offs,
1523                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1524
1525         if (smc_nc->ebi_csa->nfd0_on_d16)
1526                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1527                                    smc_nc->ebi_csa->offs,
1528                                    smc_nc->ebi_csa->nfd0_on_d16,
1529                                    smc_nc->ebi_csa->nfd0_on_d16);
1530 }
1531
1532 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1533                                  struct atmel_nand *nand)
1534 {
1535         struct nand_chip *chip = &nand->base;
1536
1537         atmel_nand_init(nc, nand);
1538
1539         /* Overload some methods for the HSMC controller. */
1540         chip->legacy.cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1541         chip->legacy.select_chip = atmel_hsmc_nand_select_chip;
1542 }
1543
1544 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1545 {
1546         struct nand_chip *chip = &nand->base;
1547         struct mtd_info *mtd = nand_to_mtd(chip);
1548         int ret;
1549
1550         ret = mtd_device_unregister(mtd);
1551         if (ret)
1552                 return ret;
1553
1554         nand_cleanup(chip);
1555         list_del(&nand->node);
1556
1557         return 0;
1558 }
1559
1560 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1561                                             struct device_node *np,
1562                                             int reg_cells)
1563 {
1564         struct atmel_nand *nand;
1565         struct gpio_desc *gpio;
1566         int numcs, ret, i;
1567
1568         numcs = of_property_count_elems_of_size(np, "reg",
1569                                                 reg_cells * sizeof(u32));
1570         if (numcs < 1) {
1571                 dev_err(nc->dev, "Missing or invalid reg property\n");
1572                 return ERR_PTR(-EINVAL);
1573         }
1574
1575         nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);
1576         if (!nand) {
1577                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1578                 return ERR_PTR(-ENOMEM);
1579         }
1580
1581         nand->numcs = numcs;
1582
1583         gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np),
1584                                      "det", GPIOD_IN, "nand-det");
1585         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1586                 dev_err(nc->dev,
1587                         "Failed to get detect gpio (err = %ld)\n",
1588                         PTR_ERR(gpio));
1589                 return ERR_CAST(gpio);
1590         }
1591
1592         if (!IS_ERR(gpio))
1593                 nand->cdgpio = gpio;
1594
1595         for (i = 0; i < numcs; i++) {
1596                 struct resource res;
1597                 u32 val;
1598
1599                 ret = of_address_to_resource(np, 0, &res);
1600                 if (ret) {
1601                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1602                                 ret);
1603                         return ERR_PTR(ret);
1604                 }
1605
1606                 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1607                                                  &val);
1608                 if (ret) {
1609                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1610                                 ret);
1611                         return ERR_PTR(ret);
1612                 }
1613
1614                 nand->cs[i].id = val;
1615
1616                 nand->cs[i].io.dma = res.start;
1617                 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1618                 if (IS_ERR(nand->cs[i].io.virt))
1619                         return ERR_CAST(nand->cs[i].io.virt);
1620
1621                 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1622                         if (val > ATMEL_NFC_MAX_RB_ID)
1623                                 return ERR_PTR(-EINVAL);
1624
1625                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1626                         nand->cs[i].rb.id = val;
1627                 } else {
1628                         gpio = devm_fwnode_gpiod_get_index(nc->dev,
1629                                                            of_fwnode_handle(np),
1630                                                            "rb", i, GPIOD_IN,
1631                                                            "nand-rb");
1632                         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1633                                 dev_err(nc->dev,
1634                                         "Failed to get R/B gpio (err = %ld)\n",
1635                                         PTR_ERR(gpio));
1636                                 return ERR_CAST(gpio);
1637                         }
1638
1639                         if (!IS_ERR(gpio)) {
1640                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1641                                 nand->cs[i].rb.gpio = gpio;
1642                         }
1643                 }
1644
1645                 gpio = devm_fwnode_gpiod_get_index(nc->dev,
1646                                                    of_fwnode_handle(np),
1647                                                    "cs", i, GPIOD_OUT_HIGH,
1648                                                    "nand-cs");
1649                 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1650                         dev_err(nc->dev,
1651                                 "Failed to get CS gpio (err = %ld)\n",
1652                                 PTR_ERR(gpio));
1653                         return ERR_CAST(gpio);
1654                 }
1655
1656                 if (!IS_ERR(gpio))
1657                         nand->cs[i].csgpio = gpio;
1658         }
1659
1660         nand_set_flash_node(&nand->base, np);
1661
1662         return nand;
1663 }
1664
1665 static int
1666 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1667                                struct atmel_nand *nand)
1668 {
1669         struct nand_chip *chip = &nand->base;
1670         struct mtd_info *mtd = nand_to_mtd(chip);
1671         int ret;
1672
1673         /* No card inserted, skip this NAND. */
1674         if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1675                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1676                 return 0;
1677         }
1678
1679         nc->caps->ops->nand_init(nc, nand);
1680
1681         ret = nand_scan(chip, nand->numcs);
1682         if (ret) {
1683                 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1684                 return ret;
1685         }
1686
1687         ret = mtd_device_register(mtd, NULL, 0);
1688         if (ret) {
1689                 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1690                 nand_cleanup(chip);
1691                 return ret;
1692         }
1693
1694         list_add_tail(&nand->node, &nc->chips);
1695
1696         return 0;
1697 }
1698
1699 static int
1700 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1701 {
1702         struct atmel_nand *nand, *tmp;
1703         int ret;
1704
1705         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1706                 ret = atmel_nand_controller_remove_nand(nand);
1707                 if (ret)
1708                         return ret;
1709         }
1710
1711         return 0;
1712 }
1713
1714 static int
1715 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1716 {
1717         struct device *dev = nc->dev;
1718         struct platform_device *pdev = to_platform_device(dev);
1719         struct atmel_nand *nand;
1720         struct gpio_desc *gpio;
1721         struct resource *res;
1722
1723         /*
1724          * Legacy bindings only allow connecting a single NAND with a unique CS
1725          * line to the controller.
1726          */
1727         nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1728                             GFP_KERNEL);
1729         if (!nand)
1730                 return -ENOMEM;
1731
1732         nand->numcs = 1;
1733
1734         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1735         nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1736         if (IS_ERR(nand->cs[0].io.virt))
1737                 return PTR_ERR(nand->cs[0].io.virt);
1738
1739         nand->cs[0].io.dma = res->start;
1740
1741         /*
1742          * The old driver was hardcoding the CS id to 3 for all sama5
1743          * controllers. Since this id is only meaningful for the sama5
1744          * controller we can safely assign this id to 3 no matter the
1745          * controller.
1746          * If one wants to connect a NAND to a different CS line, he will
1747          * have to use the new bindings.
1748          */
1749         nand->cs[0].id = 3;
1750
1751         /* R/B GPIO. */
1752         gpio = devm_gpiod_get_index_optional(dev, NULL, 0,  GPIOD_IN);
1753         if (IS_ERR(gpio)) {
1754                 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1755                         PTR_ERR(gpio));
1756                 return PTR_ERR(gpio);
1757         }
1758
1759         if (gpio) {
1760                 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1761                 nand->cs[0].rb.gpio = gpio;
1762         }
1763
1764         /* CS GPIO. */
1765         gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1766         if (IS_ERR(gpio)) {
1767                 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1768                         PTR_ERR(gpio));
1769                 return PTR_ERR(gpio);
1770         }
1771
1772         nand->cs[0].csgpio = gpio;
1773
1774         /* Card detect GPIO. */
1775         gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1776         if (IS_ERR(gpio)) {
1777                 dev_err(dev,
1778                         "Failed to get detect gpio (err = %ld)\n",
1779                         PTR_ERR(gpio));
1780                 return PTR_ERR(gpio);
1781         }
1782
1783         nand->cdgpio = gpio;
1784
1785         nand_set_flash_node(&nand->base, nc->dev->of_node);
1786
1787         return atmel_nand_controller_add_nand(nc, nand);
1788 }
1789
1790 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1791 {
1792         struct device_node *np, *nand_np;
1793         struct device *dev = nc->dev;
1794         int ret, reg_cells;
1795         u32 val;
1796
1797         /* We do not retrieve the SMC syscon when parsing old DTs. */
1798         if (nc->caps->legacy_of_bindings)
1799                 return atmel_nand_controller_legacy_add_nands(nc);
1800
1801         np = dev->of_node;
1802
1803         ret = of_property_read_u32(np, "#address-cells", &val);
1804         if (ret) {
1805                 dev_err(dev, "missing #address-cells property\n");
1806                 return ret;
1807         }
1808
1809         reg_cells = val;
1810
1811         ret = of_property_read_u32(np, "#size-cells", &val);
1812         if (ret) {
1813                 dev_err(dev, "missing #size-cells property\n");
1814                 return ret;
1815         }
1816
1817         reg_cells += val;
1818
1819         for_each_child_of_node(np, nand_np) {
1820                 struct atmel_nand *nand;
1821
1822                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1823                 if (IS_ERR(nand)) {
1824                         ret = PTR_ERR(nand);
1825                         goto err;
1826                 }
1827
1828                 ret = atmel_nand_controller_add_nand(nc, nand);
1829                 if (ret)
1830                         goto err;
1831         }
1832
1833         return 0;
1834
1835 err:
1836         atmel_nand_controller_remove_nands(nc);
1837
1838         return ret;
1839 }
1840
1841 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1842 {
1843         if (nc->dmac)
1844                 dma_release_channel(nc->dmac);
1845
1846         clk_put(nc->mck);
1847 }
1848
1849 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1850         .offs = AT91SAM9260_MATRIX_EBICSA,
1851 };
1852
1853 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1854         .offs = AT91SAM9261_MATRIX_EBICSA,
1855 };
1856
1857 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1858         .offs = AT91SAM9263_MATRIX_EBI0CSA,
1859 };
1860
1861 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1862         .offs = AT91SAM9RL_MATRIX_EBICSA,
1863 };
1864
1865 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1866         .offs = AT91SAM9G45_MATRIX_EBICSA,
1867 };
1868
1869 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1870         .offs = AT91SAM9N12_MATRIX_EBICSA,
1871 };
1872
1873 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1874         .offs = AT91SAM9X5_MATRIX_EBICSA,
1875 };
1876
1877 static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1878         .offs = AT91_SFR_CCFG_EBICSA,
1879         .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1880 };
1881
1882 static const struct of_device_id atmel_ebi_csa_regmap_of_ids[] = {
1883         {
1884                 .compatible = "atmel,at91sam9260-matrix",
1885                 .data = &at91sam9260_ebi_csa,
1886         },
1887         {
1888                 .compatible = "atmel,at91sam9261-matrix",
1889                 .data = &at91sam9261_ebi_csa,
1890         },
1891         {
1892                 .compatible = "atmel,at91sam9263-matrix",
1893                 .data = &at91sam9263_ebi_csa,
1894         },
1895         {
1896                 .compatible = "atmel,at91sam9rl-matrix",
1897                 .data = &at91sam9rl_ebi_csa,
1898         },
1899         {
1900                 .compatible = "atmel,at91sam9g45-matrix",
1901                 .data = &at91sam9g45_ebi_csa,
1902         },
1903         {
1904                 .compatible = "atmel,at91sam9n12-matrix",
1905                 .data = &at91sam9n12_ebi_csa,
1906         },
1907         {
1908                 .compatible = "atmel,at91sam9x5-matrix",
1909                 .data = &at91sam9x5_ebi_csa,
1910         },
1911         {
1912                 .compatible = "microchip,sam9x60-sfr",
1913                 .data = &sam9x60_ebi_csa,
1914         },
1915         { /* sentinel */ },
1916 };
1917
1918 static int atmel_nand_attach_chip(struct nand_chip *chip)
1919 {
1920         struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1921         struct atmel_nand *nand = to_atmel_nand(chip);
1922         struct mtd_info *mtd = nand_to_mtd(chip);
1923         int ret;
1924
1925         ret = nc->caps->ops->ecc_init(chip);
1926         if (ret)
1927                 return ret;
1928
1929         if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1930                 /*
1931                  * We keep the MTD name unchanged to avoid breaking platforms
1932                  * where the MTD cmdline parser is used and the bootloader
1933                  * has not been updated to use the new naming scheme.
1934                  */
1935                 mtd->name = "atmel_nand";
1936         } else if (!mtd->name) {
1937                 /*
1938                  * If the new bindings are used and the bootloader has not been
1939                  * updated to pass a new mtdparts parameter on the cmdline, you
1940                  * should define the following property in your nand node:
1941                  *
1942                  *      label = "atmel_nand";
1943                  *
1944                  * This way, mtd->name will be set by the core when
1945                  * nand_set_flash_node() is called.
1946                  */
1947                 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1948                                            "%s:nand.%d", dev_name(nc->dev),
1949                                            nand->cs[0].id);
1950                 if (!mtd->name) {
1951                         dev_err(nc->dev, "Failed to allocate mtd->name\n");
1952                         return -ENOMEM;
1953                 }
1954         }
1955
1956         return 0;
1957 }
1958
1959 static const struct nand_controller_ops atmel_nand_controller_ops = {
1960         .attach_chip = atmel_nand_attach_chip,
1961         .setup_interface = atmel_nand_setup_interface,
1962 };
1963
1964 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1965                                 struct platform_device *pdev,
1966                                 const struct atmel_nand_controller_caps *caps)
1967 {
1968         struct device *dev = &pdev->dev;
1969         struct device_node *np = dev->of_node;
1970         int ret;
1971
1972         nand_controller_init(&nc->base);
1973         nc->base.ops = &atmel_nand_controller_ops;
1974         INIT_LIST_HEAD(&nc->chips);
1975         nc->dev = dev;
1976         nc->caps = caps;
1977
1978         platform_set_drvdata(pdev, nc);
1979
1980         nc->pmecc = devm_atmel_pmecc_get(dev);
1981         if (IS_ERR(nc->pmecc)) {
1982                 ret = PTR_ERR(nc->pmecc);
1983                 if (ret != -EPROBE_DEFER)
1984                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1985                                 ret);
1986                 return ret;
1987         }
1988
1989         if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
1990                 dma_cap_mask_t mask;
1991
1992                 dma_cap_zero(mask);
1993                 dma_cap_set(DMA_MEMCPY, mask);
1994
1995                 nc->dmac = dma_request_channel(mask, NULL, NULL);
1996                 if (!nc->dmac)
1997                         dev_err(nc->dev, "Failed to request DMA channel\n");
1998         }
1999
2000         /* We do not retrieve the SMC syscon when parsing old DTs. */
2001         if (nc->caps->legacy_of_bindings)
2002                 return 0;
2003
2004         nc->mck = of_clk_get(dev->parent->of_node, 0);
2005         if (IS_ERR(nc->mck)) {
2006                 dev_err(dev, "Failed to retrieve MCK clk\n");
2007                 return PTR_ERR(nc->mck);
2008         }
2009
2010         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2011         if (!np) {
2012                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2013                 return -EINVAL;
2014         }
2015
2016         nc->smc = syscon_node_to_regmap(np);
2017         of_node_put(np);
2018         if (IS_ERR(nc->smc)) {
2019                 ret = PTR_ERR(nc->smc);
2020                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2021                 return ret;
2022         }
2023
2024         return 0;
2025 }
2026
2027 static int
2028 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2029 {
2030         struct device *dev = nc->base.dev;
2031         const struct of_device_id *match;
2032         struct device_node *np;
2033         int ret;
2034
2035         /* We do not retrieve the EBICSA regmap when parsing old DTs. */
2036         if (nc->base.caps->legacy_of_bindings)
2037                 return 0;
2038
2039         np = of_parse_phandle(dev->parent->of_node,
2040                               nc->base.caps->ebi_csa_regmap_name, 0);
2041         if (!np)
2042                 return 0;
2043
2044         match = of_match_node(atmel_ebi_csa_regmap_of_ids, np);
2045         if (!match) {
2046                 of_node_put(np);
2047                 return 0;
2048         }
2049
2050         nc->ebi_csa_regmap = syscon_node_to_regmap(np);
2051         of_node_put(np);
2052         if (IS_ERR(nc->ebi_csa_regmap)) {
2053                 ret = PTR_ERR(nc->ebi_csa_regmap);
2054                 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
2055                 return ret;
2056         }
2057
2058         nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
2059
2060         /*
2061          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2062          * add 4 to ->ebi_csa->offs.
2063          */
2064         if (of_device_is_compatible(dev->parent->of_node,
2065                                     "atmel,at91sam9263-ebi1"))
2066                 nc->ebi_csa->offs += 4;
2067
2068         return 0;
2069 }
2070
2071 static int
2072 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2073 {
2074         struct regmap_config regmap_conf = {
2075                 .reg_bits = 32,
2076                 .val_bits = 32,
2077                 .reg_stride = 4,
2078         };
2079
2080         struct device *dev = nc->base.dev;
2081         struct device_node *nand_np, *nfc_np;
2082         void __iomem *iomem;
2083         struct resource res;
2084         int ret;
2085
2086         nand_np = dev->of_node;
2087         nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
2088         if (!nfc_np) {
2089                 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2090                 return -ENODEV;
2091         }
2092
2093         nc->clk = of_clk_get(nfc_np, 0);
2094         if (IS_ERR(nc->clk)) {
2095                 ret = PTR_ERR(nc->clk);
2096                 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2097                         ret);
2098                 goto out;
2099         }
2100
2101         ret = clk_prepare_enable(nc->clk);
2102         if (ret) {
2103                 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2104                         ret);
2105                 goto out;
2106         }
2107
2108         nc->irq = of_irq_get(nand_np, 0);
2109         if (nc->irq <= 0) {
2110                 ret = nc->irq ?: -ENXIO;
2111                 if (ret != -EPROBE_DEFER)
2112                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2113                                 ret);
2114                 goto out;
2115         }
2116
2117         ret = of_address_to_resource(nfc_np, 0, &res);
2118         if (ret) {
2119                 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2120                         ret);
2121                 goto out;
2122         }
2123
2124         iomem = devm_ioremap_resource(dev, &res);
2125         if (IS_ERR(iomem)) {
2126                 ret = PTR_ERR(iomem);
2127                 goto out;
2128         }
2129
2130         regmap_conf.name = "nfc-io";
2131         regmap_conf.max_register = resource_size(&res) - 4;
2132         nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2133         if (IS_ERR(nc->io)) {
2134                 ret = PTR_ERR(nc->io);
2135                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2136                         ret);
2137                 goto out;
2138         }
2139
2140         ret = of_address_to_resource(nfc_np, 1, &res);
2141         if (ret) {
2142                 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2143                         ret);
2144                 goto out;
2145         }
2146
2147         iomem = devm_ioremap_resource(dev, &res);
2148         if (IS_ERR(iomem)) {
2149                 ret = PTR_ERR(iomem);
2150                 goto out;
2151         }
2152
2153         regmap_conf.name = "smc";
2154         regmap_conf.max_register = resource_size(&res) - 4;
2155         nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2156         if (IS_ERR(nc->base.smc)) {
2157                 ret = PTR_ERR(nc->base.smc);
2158                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2159                         ret);
2160                 goto out;
2161         }
2162
2163         ret = of_address_to_resource(nfc_np, 2, &res);
2164         if (ret) {
2165                 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2166                         ret);
2167                 goto out;
2168         }
2169
2170         nc->sram.virt = devm_ioremap_resource(dev, &res);
2171         if (IS_ERR(nc->sram.virt)) {
2172                 ret = PTR_ERR(nc->sram.virt);
2173                 goto out;
2174         }
2175
2176         nc->sram.dma = res.start;
2177
2178 out:
2179         of_node_put(nfc_np);
2180
2181         return ret;
2182 }
2183
2184 static int
2185 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2186 {
2187         struct device *dev = nc->base.dev;
2188         struct device_node *np;
2189         int ret;
2190
2191         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2192         if (!np) {
2193                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2194                 return -EINVAL;
2195         }
2196
2197         nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2198
2199         nc->irq = of_irq_get(np, 0);
2200         of_node_put(np);
2201         if (nc->irq <= 0) {
2202                 ret = nc->irq ?: -ENXIO;
2203                 if (ret != -EPROBE_DEFER)
2204                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2205                                 ret);
2206                 return ret;
2207         }
2208
2209         np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2210         if (!np) {
2211                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2212                 return -EINVAL;
2213         }
2214
2215         nc->io = syscon_node_to_regmap(np);
2216         of_node_put(np);
2217         if (IS_ERR(nc->io)) {
2218                 ret = PTR_ERR(nc->io);
2219                 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2220                 return ret;
2221         }
2222
2223         nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2224                                          "atmel,nfc-sram", 0);
2225         if (!nc->sram.pool) {
2226                 dev_err(nc->base.dev, "Missing SRAM\n");
2227                 return -ENOMEM;
2228         }
2229
2230         nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2231                                                            ATMEL_NFC_SRAM_SIZE,
2232                                                            &nc->sram.dma);
2233         if (!nc->sram.virt) {
2234                 dev_err(nc->base.dev,
2235                         "Could not allocate memory from the NFC SRAM pool\n");
2236                 return -ENOMEM;
2237         }
2238
2239         return 0;
2240 }
2241
2242 static int
2243 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2244 {
2245         struct atmel_hsmc_nand_controller *hsmc_nc;
2246         int ret;
2247
2248         ret = atmel_nand_controller_remove_nands(nc);
2249         if (ret)
2250                 return ret;
2251
2252         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2253         if (hsmc_nc->sram.pool)
2254                 gen_pool_free(hsmc_nc->sram.pool,
2255                               (unsigned long)hsmc_nc->sram.virt,
2256                               ATMEL_NFC_SRAM_SIZE);
2257
2258         if (hsmc_nc->clk) {
2259                 clk_disable_unprepare(hsmc_nc->clk);
2260                 clk_put(hsmc_nc->clk);
2261         }
2262
2263         atmel_nand_controller_cleanup(nc);
2264
2265         return 0;
2266 }
2267
2268 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2269                                 const struct atmel_nand_controller_caps *caps)
2270 {
2271         struct device *dev = &pdev->dev;
2272         struct atmel_hsmc_nand_controller *nc;
2273         int ret;
2274
2275         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2276         if (!nc)
2277                 return -ENOMEM;
2278
2279         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2280         if (ret)
2281                 return ret;
2282
2283         if (caps->legacy_of_bindings)
2284                 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2285         else
2286                 ret = atmel_hsmc_nand_controller_init(nc);
2287
2288         if (ret)
2289                 return ret;
2290
2291         /* Make sure all irqs are masked before registering our IRQ handler. */
2292         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2293         ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2294                                IRQF_SHARED, "nfc", nc);
2295         if (ret) {
2296                 dev_err(dev,
2297                         "Could not get register NFC interrupt handler (err = %d)\n",
2298                         ret);
2299                 goto err;
2300         }
2301
2302         /* Initial NFC configuration. */
2303         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2304                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2305
2306         ret = atmel_nand_controller_add_nands(&nc->base);
2307         if (ret)
2308                 goto err;
2309
2310         return 0;
2311
2312 err:
2313         atmel_hsmc_nand_controller_remove(&nc->base);
2314
2315         return ret;
2316 }
2317
2318 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2319         .probe = atmel_hsmc_nand_controller_probe,
2320         .remove = atmel_hsmc_nand_controller_remove,
2321         .ecc_init = atmel_hsmc_nand_ecc_init,
2322         .nand_init = atmel_hsmc_nand_init,
2323         .setup_interface = atmel_hsmc_nand_setup_interface,
2324 };
2325
2326 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2327         .has_dma = true,
2328         .ale_offs = BIT(21),
2329         .cle_offs = BIT(22),
2330         .ops = &atmel_hsmc_nc_ops,
2331 };
2332
2333 /* Only used to parse old bindings. */
2334 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2335         .has_dma = true,
2336         .ale_offs = BIT(21),
2337         .cle_offs = BIT(22),
2338         .ops = &atmel_hsmc_nc_ops,
2339         .legacy_of_bindings = true,
2340 };
2341
2342 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2343                                 const struct atmel_nand_controller_caps *caps)
2344 {
2345         struct device *dev = &pdev->dev;
2346         struct atmel_smc_nand_controller *nc;
2347         int ret;
2348
2349         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2350         if (!nc)
2351                 return -ENOMEM;
2352
2353         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2354         if (ret)
2355                 return ret;
2356
2357         ret = atmel_smc_nand_controller_init(nc);
2358         if (ret)
2359                 return ret;
2360
2361         return atmel_nand_controller_add_nands(&nc->base);
2362 }
2363
2364 static int
2365 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2366 {
2367         int ret;
2368
2369         ret = atmel_nand_controller_remove_nands(nc);
2370         if (ret)
2371                 return ret;
2372
2373         atmel_nand_controller_cleanup(nc);
2374
2375         return 0;
2376 }
2377
2378 /*
2379  * The SMC reg layout of at91rm9200 is completely different which prevents us
2380  * from re-using atmel_smc_nand_setup_interface() for the
2381  * ->setup_interface() hook.
2382  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2383  * ->setup_interface() unassigned.
2384  */
2385 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2386         .probe = atmel_smc_nand_controller_probe,
2387         .remove = atmel_smc_nand_controller_remove,
2388         .ecc_init = atmel_nand_ecc_init,
2389         .nand_init = atmel_smc_nand_init,
2390 };
2391
2392 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2393         .ale_offs = BIT(21),
2394         .cle_offs = BIT(22),
2395         .ebi_csa_regmap_name = "atmel,matrix",
2396         .ops = &at91rm9200_nc_ops,
2397 };
2398
2399 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2400         .probe = atmel_smc_nand_controller_probe,
2401         .remove = atmel_smc_nand_controller_remove,
2402         .ecc_init = atmel_nand_ecc_init,
2403         .nand_init = atmel_smc_nand_init,
2404         .setup_interface = atmel_smc_nand_setup_interface,
2405 };
2406
2407 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2408         .ale_offs = BIT(21),
2409         .cle_offs = BIT(22),
2410         .ebi_csa_regmap_name = "atmel,matrix",
2411         .ops = &atmel_smc_nc_ops,
2412 };
2413
2414 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2415         .ale_offs = BIT(22),
2416         .cle_offs = BIT(21),
2417         .ebi_csa_regmap_name = "atmel,matrix",
2418         .ops = &atmel_smc_nc_ops,
2419 };
2420
2421 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2422         .has_dma = true,
2423         .ale_offs = BIT(21),
2424         .cle_offs = BIT(22),
2425         .ebi_csa_regmap_name = "atmel,matrix",
2426         .ops = &atmel_smc_nc_ops,
2427 };
2428
2429 static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2430         .has_dma = true,
2431         .ale_offs = BIT(21),
2432         .cle_offs = BIT(22),
2433         .ebi_csa_regmap_name = "microchip,sfr",
2434         .ops = &atmel_smc_nc_ops,
2435 };
2436
2437 /* Only used to parse old bindings. */
2438 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2439         .ale_offs = BIT(21),
2440         .cle_offs = BIT(22),
2441         .ops = &atmel_smc_nc_ops,
2442         .legacy_of_bindings = true,
2443 };
2444
2445 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2446         .ale_offs = BIT(22),
2447         .cle_offs = BIT(21),
2448         .ops = &atmel_smc_nc_ops,
2449         .legacy_of_bindings = true,
2450 };
2451
2452 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2453         .has_dma = true,
2454         .ale_offs = BIT(21),
2455         .cle_offs = BIT(22),
2456         .ops = &atmel_smc_nc_ops,
2457         .legacy_of_bindings = true,
2458 };
2459
2460 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2461         {
2462                 .compatible = "atmel,at91rm9200-nand-controller",
2463                 .data = &atmel_rm9200_nc_caps,
2464         },
2465         {
2466                 .compatible = "atmel,at91sam9260-nand-controller",
2467                 .data = &atmel_sam9260_nc_caps,
2468         },
2469         {
2470                 .compatible = "atmel,at91sam9261-nand-controller",
2471                 .data = &atmel_sam9261_nc_caps,
2472         },
2473         {
2474                 .compatible = "atmel,at91sam9g45-nand-controller",
2475                 .data = &atmel_sam9g45_nc_caps,
2476         },
2477         {
2478                 .compatible = "atmel,sama5d3-nand-controller",
2479                 .data = &atmel_sama5_nc_caps,
2480         },
2481         {
2482                 .compatible = "microchip,sam9x60-nand-controller",
2483                 .data = &microchip_sam9x60_nc_caps,
2484         },
2485         /* Support for old/deprecated bindings: */
2486         {
2487                 .compatible = "atmel,at91rm9200-nand",
2488                 .data = &atmel_rm9200_nand_caps,
2489         },
2490         {
2491                 .compatible = "atmel,sama5d4-nand",
2492                 .data = &atmel_rm9200_nand_caps,
2493         },
2494         {
2495                 .compatible = "atmel,sama5d2-nand",
2496                 .data = &atmel_rm9200_nand_caps,
2497         },
2498         { /* sentinel */ },
2499 };
2500 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2501
2502 static int atmel_nand_controller_probe(struct platform_device *pdev)
2503 {
2504         const struct atmel_nand_controller_caps *caps;
2505
2506         if (pdev->id_entry)
2507                 caps = (void *)pdev->id_entry->driver_data;
2508         else
2509                 caps = of_device_get_match_data(&pdev->dev);
2510
2511         if (!caps) {
2512                 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2513                 return -EINVAL;
2514         }
2515
2516         if (caps->legacy_of_bindings) {
2517                 struct device_node *nfc_node;
2518                 u32 ale_offs = 21;
2519
2520                 /*
2521                  * If we are parsing legacy DT props and the DT contains a
2522                  * valid NFC node, forward the request to the sama5 logic.
2523                  */
2524                 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2525                                                    "atmel,sama5d3-nfc");
2526                 if (nfc_node) {
2527                         caps = &atmel_sama5_nand_caps;
2528                         of_node_put(nfc_node);
2529                 }
2530
2531                 /*
2532                  * Even if the compatible says we are dealing with an
2533                  * at91rm9200 controller, the atmel,nand-has-dma specify that
2534                  * this controller supports DMA, which means we are in fact
2535                  * dealing with an at91sam9g45+ controller.
2536                  */
2537                 if (!caps->has_dma &&
2538                     of_property_read_bool(pdev->dev.of_node,
2539                                           "atmel,nand-has-dma"))
2540                         caps = &atmel_sam9g45_nand_caps;
2541
2542                 /*
2543                  * All SoCs except the at91sam9261 are assigning ALE to A21 and
2544                  * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2545                  * actually dealing with an at91sam9261 controller.
2546                  */
2547                 of_property_read_u32(pdev->dev.of_node,
2548                                      "atmel,nand-addr-offset", &ale_offs);
2549                 if (ale_offs != 21)
2550                         caps = &atmel_sam9261_nand_caps;
2551         }
2552
2553         return caps->ops->probe(pdev, caps);
2554 }
2555
2556 static int atmel_nand_controller_remove(struct platform_device *pdev)
2557 {
2558         struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2559
2560         return nc->caps->ops->remove(nc);
2561 }
2562
2563 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2564 {
2565         struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2566         struct atmel_nand *nand;
2567
2568         if (nc->pmecc)
2569                 atmel_pmecc_reset(nc->pmecc);
2570
2571         list_for_each_entry(nand, &nc->chips, node) {
2572                 int i;
2573
2574                 for (i = 0; i < nand->numcs; i++)
2575                         nand_reset(&nand->base, i);
2576         }
2577
2578         return 0;
2579 }
2580
2581 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2582                          atmel_nand_controller_resume);
2583
2584 static struct platform_driver atmel_nand_controller_driver = {
2585         .driver = {
2586                 .name = "atmel-nand-controller",
2587                 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2588                 .pm = &atmel_nand_controller_pm_ops,
2589         },
2590         .probe = atmel_nand_controller_probe,
2591         .remove = atmel_nand_controller_remove,
2592 };
2593 module_platform_driver(atmel_nand_controller_driver);
2594
2595 MODULE_LICENSE("GPL");
2596 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2597 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2598 MODULE_ALIAS("platform:atmel-nand-controller");