drivers/mtd/nand/raw/arasan-nand-controller.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Arasan NAND Flash Controller Driver
   4  *
   5  * Copyright (C) 2014 - 2020 Xilinx, Inc.
   6  * Author:
   7  *   Miquel Raynal <miquel.raynal@bootlin.com>
   8  * Original work (fully rewritten):
   9  *   Punnaiah Choudary Kalluri <punnaia@xilinx.com>
  10  *   Naga Sureshkumar Relli <nagasure@xilinx.com>
  11  */
  12
  13 #include <linux/bch.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/module.h>
  21 #include <linux/mtd/mtd.h>
  22 #include <linux/mtd/partitions.h>
  23 #include <linux/mtd/rawnand.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27
  28 #define PKT_REG                         0x00
  29 #define   PKT_SIZE(x)                   FIELD_PREP(GENMASK(10, 0), (x))
  30 #define   PKT_STEPS(x)                  FIELD_PREP(GENMASK(23, 12), (x))
  31
  32 #define MEM_ADDR1_REG                   0x04
  33
  34 #define MEM_ADDR2_REG                   0x08
  35 #define   ADDR2_STRENGTH(x)             FIELD_PREP(GENMASK(27, 25), (x))
  36 #define   ADDR2_CS(x)                   FIELD_PREP(GENMASK(31, 30), (x))
  37
  38 #define CMD_REG                         0x0C
  39 #define   CMD_1(x)                      FIELD_PREP(GENMASK(7, 0), (x))
  40 #define   CMD_2(x)                      FIELD_PREP(GENMASK(15, 8), (x))
  41 #define   CMD_PAGE_SIZE(x)              FIELD_PREP(GENMASK(25, 23), (x))
  42 #define   CMD_DMA_ENABLE                BIT(27)
  43 #define   CMD_NADDRS(x)                 FIELD_PREP(GENMASK(30, 28), (x))
  44 #define   CMD_ECC_ENABLE                BIT(31)
  45
  46 #define PROG_REG                        0x10
  47 #define   PROG_PGRD                     BIT(0)
  48 #define   PROG_ERASE                    BIT(2)
  49 #define   PROG_STATUS                   BIT(3)
  50 #define   PROG_PGPROG                   BIT(4)
  51 #define   PROG_RDID                     BIT(6)
  52 #define   PROG_RDPARAM                  BIT(7)
  53 #define   PROG_RST                      BIT(8)
  54 #define   PROG_GET_FEATURE              BIT(9)
  55 #define   PROG_SET_FEATURE              BIT(10)
  56
  57 #define INTR_STS_EN_REG                 0x14
  58 #define INTR_SIG_EN_REG                 0x18
  59 #define INTR_STS_REG                    0x1C
  60 #define   WRITE_READY                   BIT(0)
  61 #define   READ_READY                    BIT(1)
  62 #define   XFER_COMPLETE                 BIT(2)
  63 #define   DMA_BOUNDARY                  BIT(6)
  64 #define   EVENT_MASK                    GENMASK(7, 0)
  65
  66 #define READY_STS_REG                   0x20
  67
  68 #define DMA_ADDR0_REG                   0x50
  69 #define DMA_ADDR1_REG                   0x24
  70
  71 #define FLASH_STS_REG                   0x28
  72
  73 #define DATA_PORT_REG                   0x30
  74
  75 #define ECC_CONF_REG                    0x34
  76 #define   ECC_CONF_COL(x)               FIELD_PREP(GENMASK(15, 0), (x))
  77 #define   ECC_CONF_LEN(x)               FIELD_PREP(GENMASK(26, 16), (x))
  78 #define   ECC_CONF_BCH_EN               BIT(27)
  79
  80 #define ECC_ERR_CNT_REG                 0x38
  81 #define   GET_PKT_ERR_CNT(x)            FIELD_GET(GENMASK(7, 0), (x))
  82 #define   GET_PAGE_ERR_CNT(x)           FIELD_GET(GENMASK(16, 8), (x))
  83
  84 #define ECC_SP_REG                      0x3C
  85 #define   ECC_SP_CMD1(x)                FIELD_PREP(GENMASK(7, 0), (x))
  86 #define   ECC_SP_CMD2(x)                FIELD_PREP(GENMASK(15, 8), (x))
  87 #define   ECC_SP_ADDRS(x)               FIELD_PREP(GENMASK(30, 28), (x))
  88
  89 #define ECC_1ERR_CNT_REG                0x40
  90 #define ECC_2ERR_CNT_REG                0x44
  91
  92 #define DATA_INTERFACE_REG              0x6C
  93 #define   DIFACE_SDR_MODE(x)            FIELD_PREP(GENMASK(2, 0), (x))
  94 #define   DIFACE_DDR_MODE(x)            FIELD_PREP(GENMASK(5, 3), (X))
  95 #define   DIFACE_SDR                    0
  96 #define   DIFACE_NVDDR                  BIT(9)
  97
  98 #define ANFC_MAX_CS                     2
  99 #define ANFC_DFLT_TIMEOUT_US            1000000
 100 #define ANFC_MAX_CHUNK_SIZE             SZ_1M
 101 #define ANFC_MAX_PARAM_SIZE             SZ_4K
 102 #define ANFC_MAX_STEPS                  SZ_2K
 103 #define ANFC_MAX_PKT_SIZE               (SZ_2K - 1)
 104 #define ANFC_MAX_ADDR_CYC               5U
 105 #define ANFC_RSVD_ECC_BYTES             21
 106
 107 #define ANFC_XLNX_SDR_DFLT_CORE_CLK     100000000
 108 #define ANFC_XLNX_SDR_HS_CORE_CLK       80000000
 109
 110 /**
 111  * struct anfc_op - Defines how to execute an operation
 112  * @pkt_reg: Packet register
 113  * @addr1_reg: Memory address 1 register
 114  * @addr2_reg: Memory address 2 register
 115  * @cmd_reg: Command register
 116  * @prog_reg: Program register
 117  * @steps: Number of "packets" to read/write
 118  * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin
 119  * @len: Data transfer length
 120  * @read: Data transfer direction from the controller point of view
 121  */
 122 struct anfc_op {
 123         u32 pkt_reg;
 124         u32 addr1_reg;
 125         u32 addr2_reg;
 126         u32 cmd_reg;
 127         u32 prog_reg;
 128         int steps;
 129         unsigned int rdy_timeout_ms;
 130         unsigned int len;
 131         bool read;
 132         u8 *buf;
 133 };
 134
 135 /**
 136  * struct anand - Defines the NAND chip related information
 137  * @node:               Used to store NAND chips into a list
 138  * @chip:               NAND chip information structure
 139  * @cs:                 Chip select line
 140  * @rb:                 Ready-busy line
 141  * @page_sz:            Register value of the page_sz field to use
 142  * @clk:                Expected clock frequency to use
 143  * @timings:            Data interface timing mode to use
 144  * @ecc_conf:           Hardware ECC configuration value
 145  * @strength:           Register value of the ECC strength
 146  * @raddr_cycles:       Row address cycle information
 147  * @caddr_cycles:       Column address cycle information
 148  * @ecc_bits:           Exact number of ECC bits per syndrome
 149  * @ecc_total:          Total number of ECC bytes
 150  * @errloc:             Array of errors located with soft BCH
 151  * @hw_ecc:             Buffer to store syndromes computed by hardware
 152  * @bch:                BCH structure
 153  */
 154 struct anand {
 155         struct list_head node;
 156         struct nand_chip chip;
 157         unsigned int cs;
 158         unsigned int rb;
 159         unsigned int page_sz;
 160         unsigned long clk;
 161         u32 timings;
 162         u32 ecc_conf;
 163         u32 strength;
 164         u16 raddr_cycles;
 165         u16 caddr_cycles;
 166         unsigned int ecc_bits;
 167         unsigned int ecc_total;
 168         unsigned int *errloc;
 169         u8 *hw_ecc;
 170         struct bch_control *bch;
 171 };
 172
 173 /**
 174  * struct arasan_nfc - Defines the Arasan NAND flash controller driver instance
 175  * @dev:                Pointer to the device structure
 176  * @base:               Remapped register area
 177  * @controller_clk:             Pointer to the system clock
 178  * @bus_clk:            Pointer to the flash clock
 179  * @controller:         Base controller structure
 180  * @chips:              List of all NAND chips attached to the controller
 181  * @assigned_cs:        Bitmask describing already assigned CS lines
 182  * @cur_clk:            Current clock rate
 183  */
 184 struct arasan_nfc {
 185         struct device *dev;
 186         void __iomem *base;
 187         struct clk *controller_clk;
 188         struct clk *bus_clk;
 189         struct nand_controller controller;
 190         struct list_head chips;
 191         unsigned long assigned_cs;
 192         unsigned int cur_clk;
 193 };
 194
 195 static struct anand *to_anand(struct nand_chip *nand)
 196 {
 197         return container_of(nand, struct anand, chip);
 198 }
 199
 200 static struct arasan_nfc *to_anfc(struct nand_controller *ctrl)
 201 {
 202         return container_of(ctrl, struct arasan_nfc, controller);
 203 }
 204
 205 static int anfc_wait_for_event(struct arasan_nfc *nfc, unsigned int event)
 206 {
 207         u32 val;
 208         int ret;
 209
 210         ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val,
 211                                          val & event, 0,
 212                                          ANFC_DFLT_TIMEOUT_US);
 213         if (ret) {
 214                 dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event);
 215                 return -ETIMEDOUT;
 216         }
 217
 218         writel_relaxed(event, nfc->base + INTR_STS_REG);
 219
 220         return 0;
 221 }
 222
 223 static int anfc_wait_for_rb(struct arasan_nfc *nfc, struct nand_chip *chip,
 224                             unsigned int timeout_ms)
 225 {
 226         struct anand *anand = to_anand(chip);
 227         u32 val;
 228         int ret;
 229
 230         /* There is no R/B interrupt, we must poll a register */
 231         ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val,
 232                                          val & BIT(anand->rb),
 233                                          1, timeout_ms * 1000);
 234         if (ret) {
 235                 dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n",
 236                         readl_relaxed(nfc->base + READY_STS_REG));
 237                 return -ETIMEDOUT;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static void anfc_trigger_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
 244 {
 245         writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG);
 246         writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG);
 247         writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG);
 248         writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
 249         writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG);
 250 }
 251
 252 static int anfc_pkt_len_config(unsigned int len, unsigned int *steps,
 253                                unsigned int *pktsize)
 254 {
 255         unsigned int nb, sz;
 256
 257         for (nb = 1; nb < ANFC_MAX_STEPS; nb *= 2) {
 258                 sz = len / nb;
 259                 if (sz <= ANFC_MAX_PKT_SIZE)
 260                         break;
 261         }
 262
 263         if (sz * nb != len)
 264                 return -ENOTSUPP;
 265
 266         if (steps)
 267                 *steps = nb;
 268
 269         if (pktsize)
 270                 *pktsize = sz;
 271
 272         return 0;
 273 }
 274
 275 /*
 276  * When using the embedded hardware ECC engine, the controller is in charge of
 277  * feeding the engine with, first, the ECC residue present in the data array.
 278  * A typical read operation is:
 279  * 1/ Assert the read operation by sending the relevant command/address cycles
 280  *    but targeting the column of the first ECC bytes in the OOB area instead of
 281  *    the main data directly.
 282  * 2/ After having read the relevant number of ECC bytes, the controller uses
 283  *    the RNDOUT/RNDSTART commands which are set into the "ECC Spare Command
 284  *    Register" to move the pointer back at the beginning of the main data.
 285  * 3/ It will read the content of the main area for a given size (pktsize) and
 286  *    will feed the ECC engine with this buffer again.
 287  * 4/ The ECC engine derives the ECC bytes for the given data and compare them
 288  *    with the ones already received. It eventually trigger status flags and
 289  *    then set the "Buffer Read Ready" flag.
 290  * 5/ The corrected data is then available for reading from the data port
 291  *    register.
 292  *
 293  * The hardware BCH ECC engine is known to be inconstent in BCH mode and never
 294  * reports uncorrectable errors. Because of this bug, we have to use the
 295  * software BCH implementation in the read path.
 296  */
 297 static int anfc_read_page_hw_ecc(struct nand_chip *chip, u8 *buf,
 298                                  int oob_required, int page)
 299 {
 300         struct arasan_nfc *nfc = to_anfc(chip->controller);
 301         struct mtd_info *mtd = nand_to_mtd(chip);
 302         struct anand *anand = to_anand(chip);
 303         unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
 304         unsigned int max_bitflips = 0;
 305         dma_addr_t dma_addr;
 306         int step, ret;
 307         struct anfc_op nfc_op = {
 308                 .pkt_reg =
 309                         PKT_SIZE(chip->ecc.size) |
 310                         PKT_STEPS(chip->ecc.steps),
 311                 .addr1_reg =
 312                         (page & 0xFF) << (8 * (anand->caddr_cycles)) |
 313                         (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))),
 314                 .addr2_reg =
 315                         ((page >> 16) & 0xFF) |
 316                         ADDR2_STRENGTH(anand->strength) |
 317                         ADDR2_CS(anand->cs),
 318                 .cmd_reg =
 319                         CMD_1(NAND_CMD_READ0) |
 320                         CMD_2(NAND_CMD_READSTART) |
 321                         CMD_PAGE_SIZE(anand->page_sz) |
 322                         CMD_DMA_ENABLE |
 323                         CMD_NADDRS(anand->caddr_cycles +
 324                                    anand->raddr_cycles),
 325                 .prog_reg = PROG_PGRD,
 326         };
 327
 328         dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_FROM_DEVICE);
 329         if (dma_mapping_error(nfc->dev, dma_addr)) {
 330                 dev_err(nfc->dev, "Buffer mapping error");
 331                 return -EIO;
 332         }
 333
 334         writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
 335         writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
 336
 337         anfc_trigger_op(nfc, &nfc_op);
 338
 339         ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
 340         dma_unmap_single(nfc->dev, dma_addr, len, DMA_FROM_DEVICE);
 341         if (ret) {
 342                 dev_err(nfc->dev, "Error reading page %d\n", page);
 343                 return ret;
 344         }
 345
 346         /* Store the raw OOB bytes as well */
 347         ret = nand_change_read_column_op(chip, mtd->writesize, chip->oob_poi,
 348                                          mtd->oobsize, 0);
 349         if (ret)
 350                 return ret;
 351
 352         /*
 353          * For each step, compute by softare the BCH syndrome over the raw data.
 354          * Compare the theoretical amount of errors and compare with the
 355          * hardware engine feedback.
 356          */
 357         for (step = 0; step < chip->ecc.steps; step++) {
 358                 u8 *raw_buf = &buf[step * chip->ecc.size];
 359                 unsigned int bit, byte;
 360                 int bf, i;
 361
 362                 /* Extract the syndrome, it is not necessarily aligned */
 363                 memset(anand->hw_ecc, 0, chip->ecc.bytes);
 364                 nand_extract_bits(anand->hw_ecc, 0,
 365                                   &chip->oob_poi[mtd->oobsize - anand->ecc_total],
 366                                   anand->ecc_bits * step, anand->ecc_bits);
 367
 368                 bf = bch_decode(anand->bch, raw_buf, chip->ecc.size,
 369                                 anand->hw_ecc, NULL, NULL, anand->errloc);
 370                 if (!bf) {
 371                         continue;
 372                 } else if (bf > 0) {
 373                         for (i = 0; i < bf; i++) {
 374                                 /* Only correct the data, not the syndrome */
 375                                 if (anand->errloc[i] < (chip->ecc.size * 8)) {
 376                                         bit = BIT(anand->errloc[i] & 7);
 377                                         byte = anand->errloc[i] >> 3;
 378                                         raw_buf[byte] ^= bit;
 379                                 }
 380                         }
 381
 382                         mtd->ecc_stats.corrected += bf;
 383                         max_bitflips = max_t(unsigned int, max_bitflips, bf);
 384
 385                         continue;
 386                 }
 387
 388                 bf = nand_check_erased_ecc_chunk(raw_buf, chip->ecc.size,
 389                                                  NULL, 0, NULL, 0,
 390                                                  chip->ecc.strength);
 391                 if (bf > 0) {
 392                         mtd->ecc_stats.corrected += bf;
 393                         max_bitflips = max_t(unsigned int, max_bitflips, bf);
 394                         memset(raw_buf, 0xFF, chip->ecc.size);
 395                 } else if (bf < 0) {
 396                         mtd->ecc_stats.failed++;
 397                 }
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int anfc_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf,
 404                                   int oob_required, int page)
 405 {
 406         struct anand *anand = to_anand(chip);
 407         struct arasan_nfc *nfc = to_anfc(chip->controller);
 408         struct mtd_info *mtd = nand_to_mtd(chip);
 409         unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
 410         dma_addr_t dma_addr;
 411         int ret;
 412         struct anfc_op nfc_op = {
 413                 .pkt_reg =
 414                         PKT_SIZE(chip->ecc.size) |
 415                         PKT_STEPS(chip->ecc.steps),
 416                 .addr1_reg =
 417                         (page & 0xFF) << (8 * (anand->caddr_cycles)) |
 418                         (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))),
 419                 .addr2_reg =
 420                         ((page >> 16) & 0xFF) |
 421                         ADDR2_STRENGTH(anand->strength) |
 422                         ADDR2_CS(anand->cs),
 423                 .cmd_reg =
 424                         CMD_1(NAND_CMD_SEQIN) |
 425                         CMD_2(NAND_CMD_PAGEPROG) |
 426                         CMD_PAGE_SIZE(anand->page_sz) |
 427                         CMD_DMA_ENABLE |
 428                         CMD_NADDRS(anand->caddr_cycles +
 429                                    anand->raddr_cycles) |
 430                         CMD_ECC_ENABLE,
 431                 .prog_reg = PROG_PGPROG,
 432         };
 433
 434         writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG);
 435         writel_relaxed(ECC_SP_CMD1(NAND_CMD_RNDIN) |
 436                        ECC_SP_ADDRS(anand->caddr_cycles),
 437                        nfc->base + ECC_SP_REG);
 438
 439         dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_TO_DEVICE);
 440         if (dma_mapping_error(nfc->dev, dma_addr)) {
 441                 dev_err(nfc->dev, "Buffer mapping error");
 442                 return -EIO;
 443         }
 444
 445         writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
 446         writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
 447
 448         anfc_trigger_op(nfc, &nfc_op);
 449         ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
 450         dma_unmap_single(nfc->dev, dma_addr, len, DMA_TO_DEVICE);
 451         if (ret) {
 452                 dev_err(nfc->dev, "Error writing page %d\n", page);
 453                 return ret;
 454         }
 455
 456         /* Spare data is not protected */
 457         if (oob_required)
 458                 ret = nand_write_oob_std(chip, page);
 459
 460         return ret;
 461 }
 462
 463 /* NAND framework ->exec_op() hooks and related helpers */
 464 static int anfc_parse_instructions(struct nand_chip *chip,
 465                                    const struct nand_subop *subop,
 466                                    struct anfc_op *nfc_op)
 467 {
 468         struct anand *anand = to_anand(chip);
 469         const struct nand_op_instr *instr = NULL;
 470         bool first_cmd = true;
 471         unsigned int op_id;
 472         int ret, i;
 473
 474         memset(nfc_op, 0, sizeof(*nfc_op));
 475         nfc_op->addr2_reg = ADDR2_CS(anand->cs);
 476         nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz);
 477
 478         for (op_id = 0; op_id < subop->ninstrs; op_id++) {
 479                 unsigned int offset, naddrs, pktsize;
 480                 const u8 *addrs;
 481                 u8 *buf;
 482
 483                 instr = &subop->instrs[op_id];
 484
 485                 switch (instr->type) {
 486                 case NAND_OP_CMD_INSTR:
 487                         if (first_cmd)
 488                                 nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode);
 489                         else
 490                                 nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode);
 491
 492                         first_cmd = false;
 493                         break;
 494
 495                 case NAND_OP_ADDR_INSTR:
 496                         offset = nand_subop_get_addr_start_off(subop, op_id);
 497                         naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
 498                         addrs = &instr->ctx.addr.addrs[offset];
 499                         nfc_op->cmd_reg |= CMD_NADDRS(naddrs);
 500
 501                         for (i = 0; i < min(ANFC_MAX_ADDR_CYC, naddrs); i++) {
 502                                 if (i < 4)
 503                                         nfc_op->addr1_reg |= (u32)addrs[i] << i * 8;
 504                                 else
 505                                         nfc_op->addr2_reg |= addrs[i];
 506                         }
 507
 508                         break;
 509                 case NAND_OP_DATA_IN_INSTR:
 510                         nfc_op->read = true;
 511                         fallthrough;
 512                 case NAND_OP_DATA_OUT_INSTR:
 513                         offset = nand_subop_get_data_start_off(subop, op_id);
 514                         buf = instr->ctx.data.buf.in;
 515                         nfc_op->buf = &buf[offset];
 516                         nfc_op->len = nand_subop_get_data_len(subop, op_id);
 517                         ret = anfc_pkt_len_config(nfc_op->len, &nfc_op->steps,
 518                                                   &pktsize);
 519                         if (ret)
 520                                 return ret;
 521
 522                         /*
 523                          * Number of DATA cycles must be aligned on 4, this
 524                          * means the controller might read/write more than
 525                          * requested. This is harmless most of the time as extra
 526                          * DATA are discarded in the write path and read pointer
 527                          * adjusted in the read path.
 528                          *
 529                          * FIXME: The core should mark operations where
 530                          * reading/writing more is allowed so the exec_op()
 531                          * implementation can take the right decision when the
 532                          * alignment constraint is not met: adjust the number of
 533                          * DATA cycles when it's allowed, reject the operation
 534                          * otherwise.
 535                          */
 536                         nfc_op->pkt_reg |= PKT_SIZE(round_up(pktsize, 4)) |
 537                                            PKT_STEPS(nfc_op->steps);
 538                         break;
 539                 case NAND_OP_WAITRDY_INSTR:
 540                         nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
 541                         break;
 542                 }
 543         }
 544
 545         return 0;
 546 }
 547
 548 static int anfc_rw_pio_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
 549 {
 550         unsigned int dwords = (nfc_op->len / 4) / nfc_op->steps;
 551         unsigned int last_len = nfc_op->len % 4;
 552         unsigned int offset, dir;
 553         u8 *buf = nfc_op->buf;
 554         int ret, i;
 555
 556         for (i = 0; i < nfc_op->steps; i++) {
 557                 dir = nfc_op->read ? READ_READY : WRITE_READY;
 558                 ret = anfc_wait_for_event(nfc, dir);
 559                 if (ret) {
 560                         dev_err(nfc->dev, "PIO %s ready signal not received\n",
 561                                 nfc_op->read ? "Read" : "Write");
 562                         return ret;
 563                 }
 564
 565                 offset = i * (dwords * 4);
 566                 if (nfc_op->read)
 567                         ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
 568                                      dwords);
 569                 else
 570                         iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
 571                                       dwords);
 572         }
 573
 574         if (last_len) {
 575                 u32 remainder;
 576
 577                 offset = nfc_op->len - last_len;
 578
 579                 if (nfc_op->read) {
 580                         remainder = readl_relaxed(nfc->base + DATA_PORT_REG);
 581                         memcpy(&buf[offset], &remainder, last_len);
 582                 } else {
 583                         memcpy(&remainder, &buf[offset], last_len);
 584                         writel_relaxed(remainder, nfc->base + DATA_PORT_REG);
 585                 }
 586         }
 587
 588         return anfc_wait_for_event(nfc, XFER_COMPLETE);
 589 }
 590
 591 static int anfc_misc_data_type_exec(struct nand_chip *chip,
 592                                     const struct nand_subop *subop,
 593                                     u32 prog_reg)
 594 {
 595         struct arasan_nfc *nfc = to_anfc(chip->controller);
 596         struct anfc_op nfc_op = {};
 597         int ret;
 598
 599         ret = anfc_parse_instructions(chip, subop, &nfc_op);
 600         if (ret)
 601                 return ret;
 602
 603         nfc_op.prog_reg = prog_reg;
 604         anfc_trigger_op(nfc, &nfc_op);
 605
 606         if (nfc_op.rdy_timeout_ms) {
 607                 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
 608                 if (ret)
 609                         return ret;
 610         }
 611
 612         return anfc_rw_pio_op(nfc, &nfc_op);
 613 }
 614
 615 static int anfc_param_read_type_exec(struct nand_chip *chip,
 616                                      const struct nand_subop *subop)
 617 {
 618         return anfc_misc_data_type_exec(chip, subop, PROG_RDPARAM);
 619 }
 620
 621 static int anfc_data_read_type_exec(struct nand_chip *chip,
 622                                     const struct nand_subop *subop)
 623 {
 624         return anfc_misc_data_type_exec(chip, subop, PROG_PGRD);
 625 }
 626
 627 static int anfc_param_write_type_exec(struct nand_chip *chip,
 628                                       const struct nand_subop *subop)
 629 {
 630         return anfc_misc_data_type_exec(chip, subop, PROG_SET_FEATURE);
 631 }
 632
 633 static int anfc_data_write_type_exec(struct nand_chip *chip,
 634                                      const struct nand_subop *subop)
 635 {
 636         return anfc_misc_data_type_exec(chip, subop, PROG_PGPROG);
 637 }
 638
 639 static int anfc_misc_zerolen_type_exec(struct nand_chip *chip,
 640                                        const struct nand_subop *subop,
 641                                        u32 prog_reg)
 642 {
 643         struct arasan_nfc *nfc = to_anfc(chip->controller);
 644         struct anfc_op nfc_op = {};
 645         int ret;
 646
 647         ret = anfc_parse_instructions(chip, subop, &nfc_op);
 648         if (ret)
 649                 return ret;
 650
 651         nfc_op.prog_reg = prog_reg;
 652         anfc_trigger_op(nfc, &nfc_op);
 653
 654         ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
 655         if (ret)
 656                 return ret;
 657
 658         if (nfc_op.rdy_timeout_ms)
 659                 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
 660
 661         return ret;
 662 }
 663
 664 static int anfc_status_type_exec(struct nand_chip *chip,
 665                                  const struct nand_subop *subop)
 666 {
 667         struct arasan_nfc *nfc = to_anfc(chip->controller);
 668         u32 tmp;
 669         int ret;
 670
 671         /* See anfc_check_op() for details about this constraint */
 672         if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS)
 673                 return -ENOTSUPP;
 674
 675         ret = anfc_misc_zerolen_type_exec(chip, subop, PROG_STATUS);
 676         if (ret)
 677                 return ret;
 678
 679         tmp = readl_relaxed(nfc->base + FLASH_STS_REG);
 680         memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1);
 681
 682         return 0;
 683 }
 684
 685 static int anfc_reset_type_exec(struct nand_chip *chip,
 686                                 const struct nand_subop *subop)
 687 {
 688         return anfc_misc_zerolen_type_exec(chip, subop, PROG_RST);
 689 }
 690
 691 static int anfc_erase_type_exec(struct nand_chip *chip,
 692                                 const struct nand_subop *subop)
 693 {
 694         return anfc_misc_zerolen_type_exec(chip, subop, PROG_ERASE);
 695 }
 696
 697 static int anfc_wait_type_exec(struct nand_chip *chip,
 698                                const struct nand_subop *subop)
 699 {
 700         struct arasan_nfc *nfc = to_anfc(chip->controller);
 701         struct anfc_op nfc_op = {};
 702         int ret;
 703
 704         ret = anfc_parse_instructions(chip, subop, &nfc_op);
 705         if (ret)
 706                 return ret;
 707
 708         return anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
 709 }
 710
 711 static const struct nand_op_parser anfc_op_parser = NAND_OP_PARSER(
 712         NAND_OP_PARSER_PATTERN(
 713                 anfc_param_read_type_exec,
 714                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 715                 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
 716                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
 717                 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)),
 718         NAND_OP_PARSER_PATTERN(
 719                 anfc_param_write_type_exec,
 720                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 721                 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
 722                 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_PARAM_SIZE)),
 723         NAND_OP_PARSER_PATTERN(
 724                 anfc_data_read_type_exec,
 725                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 726                 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
 727                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 728                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
 729                 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, ANFC_MAX_CHUNK_SIZE)),
 730         NAND_OP_PARSER_PATTERN(
 731                 anfc_data_write_type_exec,
 732                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 733                 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
 734                 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_CHUNK_SIZE),
 735                 NAND_OP_PARSER_PAT_CMD_ELEM(false)),
 736         NAND_OP_PARSER_PATTERN(
 737                 anfc_reset_type_exec,
 738                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 739                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
 740         NAND_OP_PARSER_PATTERN(
 741                 anfc_erase_type_exec,
 742                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 743                 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
 744                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 745                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
 746         NAND_OP_PARSER_PATTERN(
 747                 anfc_status_type_exec,
 748                 NAND_OP_PARSER_PAT_CMD_ELEM(false),
 749                 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)),
 750         NAND_OP_PARSER_PATTERN(
 751                 anfc_wait_type_exec,
 752                 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
 753         );
 754
 755 static int anfc_select_target(struct nand_chip *chip, int target)
 756 {
 757         struct anand *anand = to_anand(chip);
 758         struct arasan_nfc *nfc = to_anfc(chip->controller);
 759         int ret;
 760
 761         /* Update the controller timings and the potential ECC configuration */
 762         writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG);
 763
 764         /* Update clock frequency */
 765         if (nfc->cur_clk != anand->clk) {
 766                 clk_disable_unprepare(nfc->controller_clk);
 767                 ret = clk_set_rate(nfc->controller_clk, anand->clk);
 768                 if (ret) {
 769                         dev_err(nfc->dev, "Failed to change clock rate\n");
 770                         return ret;
 771                 }
 772
 773                 ret = clk_prepare_enable(nfc->controller_clk);
 774                 if (ret) {
 775                         dev_err(nfc->dev,
 776                                 "Failed to re-enable the controller clock\n");
 777                         return ret;
 778                 }
 779
 780                 nfc->cur_clk = anand->clk;
 781         }
 782
 783         return 0;
 784 }
 785
 786 static int anfc_check_op(struct nand_chip *chip,
 787                          const struct nand_operation *op)
 788 {
 789         const struct nand_op_instr *instr;
 790         int op_id;
 791
 792         /*
 793          * The controller abstracts all the NAND operations and do not support
 794          * data only operations.
 795          *
 796          * TODO: The nand_op_parser framework should be extended to
 797          * support custom checks on DATA instructions.
 798          */
 799         for (op_id = 0; op_id < op->ninstrs; op_id++) {
 800                 instr = &op->instrs[op_id];
 801
 802                 switch (instr->type) {
 803                 case NAND_OP_ADDR_INSTR:
 804                         if (instr->ctx.addr.naddrs > ANFC_MAX_ADDR_CYC)
 805                                 return -ENOTSUPP;
 806
 807                         break;
 808                 case NAND_OP_DATA_IN_INSTR:
 809                 case NAND_OP_DATA_OUT_INSTR:
 810                         if (instr->ctx.data.len > ANFC_MAX_CHUNK_SIZE)
 811                                 return -ENOTSUPP;
 812
 813                         if (anfc_pkt_len_config(instr->ctx.data.len, 0, 0))
 814                                 return -ENOTSUPP;
 815
 816                         break;
 817                 default:
 818                         break;
 819                 }
 820         }
 821
 822         /*
 823          * The controller does not allow to proceed with a CMD+DATA_IN cycle
 824          * manually on the bus by reading data from the data register. Instead,
 825          * the controller abstract a status read operation with its own status
 826          * register after ordering a read status operation. Hence, we cannot
 827          * support any CMD+DATA_IN operation other than a READ STATUS.
 828          *
 829          * TODO: The nand_op_parser() framework should be extended to describe
 830          * fixed patterns instead of open-coding this check here.
 831          */
 832         if (op->ninstrs == 2 &&
 833             op->instrs[0].type == NAND_OP_CMD_INSTR &&
 834             op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS &&
 835             op->instrs[1].type == NAND_OP_DATA_IN_INSTR)
 836                 return -ENOTSUPP;
 837
 838         return nand_op_parser_exec_op(chip, &anfc_op_parser, op, true);
 839 }
 840
 841 static int anfc_exec_op(struct nand_chip *chip,
 842                         const struct nand_operation *op,
 843                         bool check_only)
 844 {
 845         int ret;
 846
 847         if (check_only)
 848                 return anfc_check_op(chip, op);
 849
 850         ret = anfc_select_target(chip, op->cs);
 851         if (ret)
 852                 return ret;
 853
 854         return nand_op_parser_exec_op(chip, &anfc_op_parser, op, check_only);
 855 }
 856
 857 static int anfc_setup_interface(struct nand_chip *chip, int target,
 858                                 const struct nand_interface_config *conf)
 859 {
 860         struct anand *anand = to_anand(chip);
 861         struct arasan_nfc *nfc = to_anfc(chip->controller);
 862         struct device_node *np = nfc->dev->of_node;
 863
 864         if (target < 0)
 865                 return 0;
 866
 867         anand->timings = DIFACE_SDR | DIFACE_SDR_MODE(conf->timings.mode);
 868         anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
 869
 870         /*
 871          * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work
 872          * with f > 90MHz (default clock is 100MHz) but signals are unstable
 873          * with higher modes. Hence we decrease a little bit the clock rate to
 874          * 80MHz when using modes 2-5 with this SoC.
 875          */
 876         if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") &&
 877             conf->timings.mode >= 2)
 878                 anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK;
 879
 880         return 0;
 881 }
 882
 883 static int anfc_calc_hw_ecc_bytes(int step_size, int strength)
 884 {
 885         unsigned int bch_gf_mag, ecc_bits;
 886
 887         switch (step_size) {
 888         case SZ_512:
 889                 bch_gf_mag = 13;
 890                 break;
 891         case SZ_1K:
 892                 bch_gf_mag = 14;
 893                 break;
 894         default:
 895                 return -EINVAL;
 896         }
 897
 898         ecc_bits = bch_gf_mag * strength;
 899
 900         return DIV_ROUND_UP(ecc_bits, 8);
 901 }
 902
 903 static const int anfc_hw_ecc_512_strengths[] = {4, 8, 12};
 904
 905 static const int anfc_hw_ecc_1024_strengths[] = {24};
 906
 907 static const struct nand_ecc_step_info anfc_hw_ecc_step_infos[] = {
 908         {
 909                 .stepsize = SZ_512,
 910                 .strengths = anfc_hw_ecc_512_strengths,
 911                 .nstrengths = ARRAY_SIZE(anfc_hw_ecc_512_strengths),
 912         },
 913         {
 914                 .stepsize = SZ_1K,
 915                 .strengths = anfc_hw_ecc_1024_strengths,
 916                 .nstrengths = ARRAY_SIZE(anfc_hw_ecc_1024_strengths),
 917         },
 918 };
 919
 920 static const struct nand_ecc_caps anfc_hw_ecc_caps = {
 921         .stepinfos = anfc_hw_ecc_step_infos,
 922         .nstepinfos = ARRAY_SIZE(anfc_hw_ecc_step_infos),
 923         .calc_ecc_bytes = anfc_calc_hw_ecc_bytes,
 924 };
 925
 926 static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc,
 927                                        struct nand_chip *chip)
 928 {
 929         struct anand *anand = to_anand(chip);
 930         struct mtd_info *mtd = nand_to_mtd(chip);
 931         struct nand_ecc_ctrl *ecc = &chip->ecc;
 932         unsigned int bch_prim_poly = 0, bch_gf_mag = 0, ecc_offset;
 933         int ret;
 934
 935         switch (mtd->writesize) {
 936         case SZ_512:
 937         case SZ_2K:
 938         case SZ_4K:
 939         case SZ_8K:
 940         case SZ_16K:
 941                 break;
 942         default:
 943                 dev_err(nfc->dev, "Unsupported page size %d\n", mtd->writesize);
 944                 return -EINVAL;
 945         }
 946
 947         ret = nand_ecc_choose_conf(chip, &anfc_hw_ecc_caps, mtd->oobsize);
 948         if (ret)
 949                 return ret;
 950
 951         switch (ecc->strength) {
 952         case 12:
 953                 anand->strength = 0x1;
 954                 break;
 955         case 8:
 956                 anand->strength = 0x2;
 957                 break;
 958         case 4:
 959                 anand->strength = 0x3;
 960                 break;
 961         case 24:
 962                 anand->strength = 0x4;
 963                 break;
 964         default:
 965                 dev_err(nfc->dev, "Unsupported strength %d\n", ecc->strength);
 966                 return -EINVAL;
 967         }
 968
 969         switch (ecc->size) {
 970         case SZ_512:
 971                 bch_gf_mag = 13;
 972                 bch_prim_poly = 0x201b;
 973                 break;
 974         case SZ_1K:
 975                 bch_gf_mag = 14;
 976                 bch_prim_poly = 0x4443;
 977                 break;
 978         default:
 979                 dev_err(nfc->dev, "Unsupported step size %d\n", ecc->strength);
 980                 return -EINVAL;
 981         }
 982
 983         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
 984
 985         ecc->steps = mtd->writesize / ecc->size;
 986         ecc->algo = NAND_ECC_ALGO_BCH;
 987         anand->ecc_bits = bch_gf_mag * ecc->strength;
 988         ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8);
 989         anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8);
 990         ecc_offset = mtd->writesize + mtd->oobsize - anand->ecc_total;
 991         anand->ecc_conf = ECC_CONF_COL(ecc_offset) |
 992                           ECC_CONF_LEN(anand->ecc_total) |
 993                           ECC_CONF_BCH_EN;
 994
 995         anand->errloc = devm_kmalloc_array(nfc->dev, ecc->strength,
 996                                            sizeof(*anand->errloc), GFP_KERNEL);
 997         if (!anand->errloc)
 998                 return -ENOMEM;
 999
1000         anand->hw_ecc = devm_kmalloc(nfc->dev, ecc->bytes, GFP_KERNEL);
1001         if (!anand->hw_ecc)
1002                 return -ENOMEM;
1003
1004         /* Enforce bit swapping to fit the hardware */
1005         anand->bch = bch_init(bch_gf_mag, ecc->strength, bch_prim_poly, true);
1006         if (!anand->bch)
1007                 return -EINVAL;
1008
1009         ecc->read_page = anfc_read_page_hw_ecc;
1010         ecc->write_page = anfc_write_page_hw_ecc;
1011
1012         return 0;
1013 }
1014
1015 static int anfc_attach_chip(struct nand_chip *chip)
1016 {
1017         struct anand *anand = to_anand(chip);
1018         struct arasan_nfc *nfc = to_anfc(chip->controller);
1019         struct mtd_info *mtd = nand_to_mtd(chip);
1020         int ret = 0;
1021
1022         if (mtd->writesize <= SZ_512)
1023                 anand->caddr_cycles = 1;
1024         else
1025                 anand->caddr_cycles = 2;
1026
1027         if (chip->options & NAND_ROW_ADDR_3)
1028                 anand->raddr_cycles = 3;
1029         else
1030                 anand->raddr_cycles = 2;
1031
1032         switch (mtd->writesize) {
1033         case 512:
1034                 anand->page_sz = 0;
1035                 break;
1036         case 1024:
1037                 anand->page_sz = 5;
1038                 break;
1039         case 2048:
1040                 anand->page_sz = 1;
1041                 break;
1042         case 4096:
1043                 anand->page_sz = 2;
1044                 break;
1045         case 8192:
1046                 anand->page_sz = 3;
1047                 break;
1048         case 16384:
1049                 anand->page_sz = 4;
1050                 break;
1051         default:
1052                 return -EINVAL;
1053         }
1054
1055         /* These hooks are valid for all ECC providers */
1056         chip->ecc.read_page_raw = nand_monolithic_read_page_raw;
1057         chip->ecc.write_page_raw = nand_monolithic_write_page_raw;
1058
1059         switch (chip->ecc.engine_type) {
1060         case NAND_ECC_ENGINE_TYPE_NONE:
1061         case NAND_ECC_ENGINE_TYPE_SOFT:
1062         case NAND_ECC_ENGINE_TYPE_ON_DIE:
1063                 break;
1064         case NAND_ECC_ENGINE_TYPE_ON_HOST:
1065                 ret = anfc_init_hw_ecc_controller(nfc, chip);
1066                 break;
1067         default:
1068                 dev_err(nfc->dev, "Unsupported ECC mode: %d\n",
1069                         chip->ecc.engine_type);
1070                 return -EINVAL;
1071         }
1072
1073         return ret;
1074 }
1075
1076 static void anfc_detach_chip(struct nand_chip *chip)
1077 {
1078         struct anand *anand = to_anand(chip);
1079
1080         if (anand->bch)
1081                 bch_free(anand->bch);
1082 }
1083
1084 static const struct nand_controller_ops anfc_ops = {
1085         .exec_op = anfc_exec_op,
1086         .setup_interface = anfc_setup_interface,
1087         .attach_chip = anfc_attach_chip,
1088         .detach_chip = anfc_detach_chip,
1089 };
1090
1091 static int anfc_chip_init(struct arasan_nfc *nfc, struct device_node *np)
1092 {
1093         struct anand *anand;
1094         struct nand_chip *chip;
1095         struct mtd_info *mtd;
1096         int cs, rb, ret;
1097
1098         anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL);
1099         if (!anand)
1100                 return -ENOMEM;
1101
1102         /* We do not support multiple CS per chip yet */
1103         if (of_property_count_elems_of_size(np, "reg", sizeof(u32)) != 1) {
1104                 dev_err(nfc->dev, "Invalid reg property\n");
1105                 return -EINVAL;
1106         }
1107
1108         ret = of_property_read_u32(np, "reg", &cs);
1109         if (ret)
1110                 return ret;
1111
1112         ret = of_property_read_u32(np, "nand-rb", &rb);
1113         if (ret)
1114                 return ret;
1115
1116         if (cs >= ANFC_MAX_CS || rb >= ANFC_MAX_CS) {
1117                 dev_err(nfc->dev, "Wrong CS %d or RB %d\n", cs, rb);
1118                 return -EINVAL;
1119         }
1120
1121         if (test_and_set_bit(cs, &nfc->assigned_cs)) {
1122                 dev_err(nfc->dev, "Already assigned CS %d\n", cs);
1123                 return -EINVAL;
1124         }
1125
1126         anand->cs = cs;
1127         anand->rb = rb;
1128
1129         chip = &anand->chip;
1130         mtd = nand_to_mtd(chip);
1131         mtd->dev.parent = nfc->dev;
1132         chip->controller = &nfc->controller;
1133         chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
1134                         NAND_USES_DMA;
1135
1136         nand_set_flash_node(chip, np);
1137         if (!mtd->name) {
1138                 dev_err(nfc->dev, "NAND label property is mandatory\n");
1139                 return -EINVAL;
1140         }
1141
1142         ret = nand_scan(chip, 1);
1143         if (ret) {
1144                 dev_err(nfc->dev, "Scan operation failed\n");
1145                 return ret;
1146         }
1147
1148         ret = mtd_device_register(mtd, NULL, 0);
1149         if (ret) {
1150                 nand_cleanup(chip);
1151                 return ret;
1152         }
1153
1154         list_add_tail(&anand->node, &nfc->chips);
1155
1156         return 0;
1157 }
1158
1159 static void anfc_chips_cleanup(struct arasan_nfc *nfc)
1160 {
1161         struct anand *anand, *tmp;
1162         struct nand_chip *chip;
1163         int ret;
1164
1165         list_for_each_entry_safe(anand, tmp, &nfc->chips, node) {
1166                 chip = &anand->chip;
1167                 ret = mtd_device_unregister(nand_to_mtd(chip));
1168                 WARN_ON(ret);
1169                 nand_cleanup(chip);
1170                 list_del(&anand->node);
1171         }
1172 }
1173
1174 static int anfc_chips_init(struct arasan_nfc *nfc)
1175 {
1176         struct device_node *np = nfc->dev->of_node, *nand_np;
1177         int nchips = of_get_child_count(np);
1178         int ret;
1179
1180         if (!nchips || nchips > ANFC_MAX_CS) {
1181                 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n",
1182                         nchips);
1183                 return -EINVAL;
1184         }
1185
1186         for_each_child_of_node(np, nand_np) {
1187                 ret = anfc_chip_init(nfc, nand_np);
1188                 if (ret) {
1189                         of_node_put(nand_np);
1190                         anfc_chips_cleanup(nfc);
1191                         break;
1192                 }
1193         }
1194
1195         return ret;
1196 }
1197
1198 static void anfc_reset(struct arasan_nfc *nfc)
1199 {
1200         /* Disable interrupt signals */
1201         writel_relaxed(0, nfc->base + INTR_SIG_EN_REG);
1202
1203         /* Enable interrupt status */
1204         writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG);
1205 }
1206
1207 static int anfc_probe(struct platform_device *pdev)
1208 {
1209         struct arasan_nfc *nfc;
1210         int ret;
1211
1212         nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
1213         if (!nfc)
1214                 return -ENOMEM;
1215
1216         nfc->dev = &pdev->dev;
1217         nand_controller_init(&nfc->controller);
1218         nfc->controller.ops = &anfc_ops;
1219         INIT_LIST_HEAD(&nfc->chips);
1220
1221         nfc->base = devm_platform_ioremap_resource(pdev, 0);
1222         if (IS_ERR(nfc->base))
1223                 return PTR_ERR(nfc->base);
1224
1225         anfc_reset(nfc);
1226
1227         nfc->controller_clk = devm_clk_get(&pdev->dev, "controller");
1228         if (IS_ERR(nfc->controller_clk))
1229                 return PTR_ERR(nfc->controller_clk);
1230
1231         nfc->bus_clk = devm_clk_get(&pdev->dev, "bus");
1232         if (IS_ERR(nfc->bus_clk))
1233                 return PTR_ERR(nfc->bus_clk);
1234
1235         ret = clk_prepare_enable(nfc->controller_clk);
1236         if (ret)
1237                 return ret;
1238
1239         ret = clk_prepare_enable(nfc->bus_clk);
1240         if (ret)
1241                 goto disable_controller_clk;
1242
1243         ret = anfc_chips_init(nfc);
1244         if (ret)
1245                 goto disable_bus_clk;
1246
1247         platform_set_drvdata(pdev, nfc);
1248
1249         return 0;
1250
1251 disable_bus_clk:
1252         clk_disable_unprepare(nfc->bus_clk);
1253
1254 disable_controller_clk:
1255         clk_disable_unprepare(nfc->controller_clk);
1256
1257         return ret;
1258 }
1259
1260 static int anfc_remove(struct platform_device *pdev)
1261 {
1262         struct arasan_nfc *nfc = platform_get_drvdata(pdev);
1263
1264         anfc_chips_cleanup(nfc);
1265
1266         clk_disable_unprepare(nfc->bus_clk);
1267         clk_disable_unprepare(nfc->controller_clk);
1268
1269         return 0;
1270 }
1271
1272 static const struct of_device_id anfc_ids[] = {
1273         {
1274                 .compatible = "xlnx,zynqmp-nand-controller",
1275         },
1276         {
1277                 .compatible = "arasan,nfc-v3p10",
1278         },
1279         {}
1280 };
1281 MODULE_DEVICE_TABLE(of, anfc_ids);
1282
1283 static struct platform_driver anfc_driver = {
1284         .driver = {
1285                 .name = "arasan-nand-controller",
1286                 .of_match_table = anfc_ids,
1287         },
1288         .probe = anfc_probe,
1289         .remove = anfc_remove,
1290 };
1291 module_platform_driver(anfc_driver);
1292
1293 MODULE_LICENSE("GPL v2");
1294 MODULE_AUTHOR("Punnaiah Choudary Kalluri <punnaia@xilinx.com>");
1295 MODULE_AUTHOR("Naga Sureshkumar Relli <nagasure@xilinx.com>");
1296 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
1297 MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");