2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/platform_device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/sched.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
22 #include <linux/slab.h>
24 #ifdef CONFIG_MTD_NAND_OMAP_BCH
25 #include <linux/bch.h>
29 #include <plat/gpmc.h>
30 #include <plat/nand.h>
32 #define DRIVER_NAME "omap2-nand"
33 #define OMAP_NAND_TIMEOUT_MS 5000
35 #define NAND_Ecc_P1e (1 << 0)
36 #define NAND_Ecc_P2e (1 << 1)
37 #define NAND_Ecc_P4e (1 << 2)
38 #define NAND_Ecc_P8e (1 << 3)
39 #define NAND_Ecc_P16e (1 << 4)
40 #define NAND_Ecc_P32e (1 << 5)
41 #define NAND_Ecc_P64e (1 << 6)
42 #define NAND_Ecc_P128e (1 << 7)
43 #define NAND_Ecc_P256e (1 << 8)
44 #define NAND_Ecc_P512e (1 << 9)
45 #define NAND_Ecc_P1024e (1 << 10)
46 #define NAND_Ecc_P2048e (1 << 11)
48 #define NAND_Ecc_P1o (1 << 16)
49 #define NAND_Ecc_P2o (1 << 17)
50 #define NAND_Ecc_P4o (1 << 18)
51 #define NAND_Ecc_P8o (1 << 19)
52 #define NAND_Ecc_P16o (1 << 20)
53 #define NAND_Ecc_P32o (1 << 21)
54 #define NAND_Ecc_P64o (1 << 22)
55 #define NAND_Ecc_P128o (1 << 23)
56 #define NAND_Ecc_P256o (1 << 24)
57 #define NAND_Ecc_P512o (1 << 25)
58 #define NAND_Ecc_P1024o (1 << 26)
59 #define NAND_Ecc_P2048o (1 << 27)
61 #define TF(value) (value ? 1 : 0)
63 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
64 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
65 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
66 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
67 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
68 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
69 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
70 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
73 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
74 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
75 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
76 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
77 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
78 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
79 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
82 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
83 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
84 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
85 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
86 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
87 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
88 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
91 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
92 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
93 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
94 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
95 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
96 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
97 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
100 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102 /* oob info generated runtime depending on ecc algorithm and layout selected */
103 static struct nand_ecclayout omap_oobinfo;
104 /* Define some generic bad / good block scan pattern which are used
105 * while scanning a device for factory marked good / bad blocks
107 static uint8_t scan_ff_pattern[] = { 0xff };
108 static struct nand_bbt_descr bb_descrip_flashbased = {
109 .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
112 .pattern = scan_ff_pattern,
116 struct omap_nand_info {
117 struct nand_hw_control controller;
118 struct omap_nand_platform_data *pdata;
120 struct nand_chip nand;
121 struct platform_device *pdev;
124 unsigned long phys_base;
125 struct completion comp;
129 OMAP_NAND_IO_READ = 0, /* read */
130 OMAP_NAND_IO_WRITE, /* write */
135 #ifdef CONFIG_MTD_NAND_OMAP_BCH
136 struct bch_control *bch;
137 struct nand_ecclayout ecclayout;
142 * omap_hwcontrol - hardware specific access to control-lines
143 * @mtd: MTD device structure
144 * @cmd: command to device
146 * NAND_NCE: bit 0 -> don't care
147 * NAND_CLE: bit 1 -> Command Latch
148 * NAND_ALE: bit 2 -> Address Latch
150 * NOTE: boards may use different bits for these!!
152 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
154 struct omap_nand_info *info = container_of(mtd,
155 struct omap_nand_info, mtd);
157 if (cmd != NAND_CMD_NONE) {
159 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
161 else if (ctrl & NAND_ALE)
162 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
165 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
170 * omap_read_buf8 - read data from NAND controller into buffer
171 * @mtd: MTD device structure
172 * @buf: buffer to store date
173 * @len: number of bytes to read
175 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
177 struct nand_chip *nand = mtd->priv;
179 ioread8_rep(nand->IO_ADDR_R, buf, len);
183 * omap_write_buf8 - write buffer to NAND controller
184 * @mtd: MTD device structure
186 * @len: number of bytes to write
188 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
190 struct omap_nand_info *info = container_of(mtd,
191 struct omap_nand_info, mtd);
192 u_char *p = (u_char *)buf;
196 iowrite8(*p++, info->nand.IO_ADDR_W);
197 /* wait until buffer is available for write */
199 status = gpmc_read_status(GPMC_STATUS_BUFFER);
205 * omap_read_buf16 - read data from NAND controller into buffer
206 * @mtd: MTD device structure
207 * @buf: buffer to store date
208 * @len: number of bytes to read
210 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
212 struct nand_chip *nand = mtd->priv;
214 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
218 * omap_write_buf16 - write buffer to NAND controller
219 * @mtd: MTD device structure
221 * @len: number of bytes to write
223 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
225 struct omap_nand_info *info = container_of(mtd,
226 struct omap_nand_info, mtd);
227 u16 *p = (u16 *) buf;
229 /* FIXME try bursts of writesw() or DMA ... */
233 iowrite16(*p++, info->nand.IO_ADDR_W);
234 /* wait until buffer is available for write */
236 status = gpmc_read_status(GPMC_STATUS_BUFFER);
242 * omap_read_buf_pref - read data from NAND controller into buffer
243 * @mtd: MTD device structure
244 * @buf: buffer to store date
245 * @len: number of bytes to read
247 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
249 struct omap_nand_info *info = container_of(mtd,
250 struct omap_nand_info, mtd);
251 uint32_t r_count = 0;
255 /* take care of subpage reads */
257 if (info->nand.options & NAND_BUSWIDTH_16)
258 omap_read_buf16(mtd, buf, len % 4);
260 omap_read_buf8(mtd, buf, len % 4);
261 p = (u32 *) (buf + len % 4);
265 /* configure and start prefetch transfer */
266 ret = gpmc_prefetch_enable(info->gpmc_cs,
267 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
269 /* PFPW engine is busy, use cpu copy method */
270 if (info->nand.options & NAND_BUSWIDTH_16)
271 omap_read_buf16(mtd, (u_char *)p, len);
273 omap_read_buf8(mtd, (u_char *)p, len);
276 r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
277 r_count = r_count >> 2;
278 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
282 /* disable and stop the PFPW engine */
283 gpmc_prefetch_reset(info->gpmc_cs);
288 * omap_write_buf_pref - write buffer to NAND controller
289 * @mtd: MTD device structure
291 * @len: number of bytes to write
293 static void omap_write_buf_pref(struct mtd_info *mtd,
294 const u_char *buf, int len)
296 struct omap_nand_info *info = container_of(mtd,
297 struct omap_nand_info, mtd);
298 uint32_t w_count = 0;
301 unsigned long tim, limit;
303 /* take care of subpage writes */
305 writeb(*buf, info->nand.IO_ADDR_W);
306 p = (u16 *)(buf + 1);
310 /* configure and start prefetch transfer */
311 ret = gpmc_prefetch_enable(info->gpmc_cs,
312 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
314 /* PFPW engine is busy, use cpu copy method */
315 if (info->nand.options & NAND_BUSWIDTH_16)
316 omap_write_buf16(mtd, (u_char *)p, len);
318 omap_write_buf8(mtd, (u_char *)p, len);
321 w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
322 w_count = w_count >> 1;
323 for (i = 0; (i < w_count) && len; i++, len -= 2)
324 iowrite16(*p++, info->nand.IO_ADDR_W);
326 /* wait for data to flushed-out before reset the prefetch */
328 limit = (loops_per_jiffy *
329 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
330 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
333 /* disable and stop the PFPW engine */
334 gpmc_prefetch_reset(info->gpmc_cs);
339 * omap_nand_dma_cb: callback on the completion of dma transfer
340 * @lch: logical channel
341 * @ch_satuts: channel status
342 * @data: pointer to completion data structure
344 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
346 complete((struct completion *) data);
350 * omap_nand_dma_transfer: configer and start dma transfer
351 * @mtd: MTD device structure
352 * @addr: virtual address in RAM of source/destination
353 * @len: number of data bytes to be transferred
354 * @is_write: flag for read/write operation
356 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
357 unsigned int len, int is_write)
359 struct omap_nand_info *info = container_of(mtd,
360 struct omap_nand_info, mtd);
361 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
365 unsigned long tim, limit;
367 /* The fifo depth is 64 bytes max.
368 * But configure the FIFO-threahold to 32 to get a sync at each frame
369 * and frame length is 32 bytes.
371 int buf_len = len >> 6;
373 if (addr >= high_memory) {
376 if (((size_t)addr & PAGE_MASK) !=
377 ((size_t)(addr + len - 1) & PAGE_MASK))
379 p1 = vmalloc_to_page(addr);
382 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
385 dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
386 if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
387 dev_err(&info->pdev->dev,
388 "Couldn't DMA map a %d byte buffer\n", len);
393 omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
394 info->phys_base, 0, 0);
395 omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
397 omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
398 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
399 OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
401 omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
402 info->phys_base, 0, 0);
403 omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
405 omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
406 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
407 OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
409 /* configure and start prefetch transfer */
410 ret = gpmc_prefetch_enable(info->gpmc_cs,
411 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
413 /* PFPW engine is busy, use cpu copy method */
416 init_completion(&info->comp);
418 omap_start_dma(info->dma_ch);
420 /* setup and start DMA using dma_addr */
421 wait_for_completion(&info->comp);
423 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
424 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
427 /* disable and stop the PFPW engine */
428 gpmc_prefetch_reset(info->gpmc_cs);
430 dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
434 dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
436 if (info->nand.options & NAND_BUSWIDTH_16)
437 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
438 : omap_write_buf16(mtd, (u_char *) addr, len);
440 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
441 : omap_write_buf8(mtd, (u_char *) addr, len);
446 * omap_read_buf_dma_pref - read data from NAND controller into buffer
447 * @mtd: MTD device structure
448 * @buf: buffer to store date
449 * @len: number of bytes to read
451 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
453 if (len <= mtd->oobsize)
454 omap_read_buf_pref(mtd, buf, len);
456 /* start transfer in DMA mode */
457 omap_nand_dma_transfer(mtd, buf, len, 0x0);
461 * omap_write_buf_dma_pref - write buffer to NAND controller
462 * @mtd: MTD device structure
464 * @len: number of bytes to write
466 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
467 const u_char *buf, int len)
469 if (len <= mtd->oobsize)
470 omap_write_buf_pref(mtd, buf, len);
472 /* start transfer in DMA mode */
473 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
477 * omap_nand_irq - GMPC irq handler
478 * @this_irq: gpmc irq number
479 * @dev: omap_nand_info structure pointer is passed here
481 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
483 struct omap_nand_info *info = (struct omap_nand_info *) dev;
487 irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
488 bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
489 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
490 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
494 if (info->buf_len && (info->buf_len < bytes))
495 bytes = info->buf_len;
496 else if (!info->buf_len)
498 iowrite32_rep(info->nand.IO_ADDR_W,
499 (u32 *)info->buf, bytes >> 2);
500 info->buf = info->buf + bytes;
501 info->buf_len -= bytes;
504 ioread32_rep(info->nand.IO_ADDR_R,
505 (u32 *)info->buf, bytes >> 2);
506 info->buf = info->buf + bytes;
511 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
516 complete(&info->comp);
518 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
521 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
527 * omap_read_buf_irq_pref - read data from NAND controller into buffer
528 * @mtd: MTD device structure
529 * @buf: buffer to store date
530 * @len: number of bytes to read
532 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
534 struct omap_nand_info *info = container_of(mtd,
535 struct omap_nand_info, mtd);
538 if (len <= mtd->oobsize) {
539 omap_read_buf_pref(mtd, buf, len);
543 info->iomode = OMAP_NAND_IO_READ;
545 init_completion(&info->comp);
547 /* configure and start prefetch transfer */
548 ret = gpmc_prefetch_enable(info->gpmc_cs,
549 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
551 /* PFPW engine is busy, use cpu copy method */
556 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
557 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
559 /* waiting for read to complete */
560 wait_for_completion(&info->comp);
562 /* disable and stop the PFPW engine */
563 gpmc_prefetch_reset(info->gpmc_cs);
567 if (info->nand.options & NAND_BUSWIDTH_16)
568 omap_read_buf16(mtd, buf, len);
570 omap_read_buf8(mtd, buf, len);
574 * omap_write_buf_irq_pref - write buffer to NAND controller
575 * @mtd: MTD device structure
577 * @len: number of bytes to write
579 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
580 const u_char *buf, int len)
582 struct omap_nand_info *info = container_of(mtd,
583 struct omap_nand_info, mtd);
585 unsigned long tim, limit;
587 if (len <= mtd->oobsize) {
588 omap_write_buf_pref(mtd, buf, len);
592 info->iomode = OMAP_NAND_IO_WRITE;
593 info->buf = (u_char *) buf;
594 init_completion(&info->comp);
596 /* configure and start prefetch transfer : size=24 */
597 ret = gpmc_prefetch_enable(info->gpmc_cs,
598 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
600 /* PFPW engine is busy, use cpu copy method */
605 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
606 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
608 /* waiting for write to complete */
609 wait_for_completion(&info->comp);
610 /* wait for data to flushed-out before reset the prefetch */
612 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
613 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
616 /* disable and stop the PFPW engine */
617 gpmc_prefetch_reset(info->gpmc_cs);
621 if (info->nand.options & NAND_BUSWIDTH_16)
622 omap_write_buf16(mtd, buf, len);
624 omap_write_buf8(mtd, buf, len);
628 * omap_verify_buf - Verify chip data against buffer
629 * @mtd: MTD device structure
630 * @buf: buffer containing the data to compare
631 * @len: number of bytes to compare
633 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
635 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
637 u16 *p = (u16 *) buf;
641 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
649 * gen_true_ecc - This function will generate true ECC value
650 * @ecc_buf: buffer to store ecc code
652 * This generated true ECC value can be used when correcting
653 * data read from NAND flash memory core
655 static void gen_true_ecc(u8 *ecc_buf)
657 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
658 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
660 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
661 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
662 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
663 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
664 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
665 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
669 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
670 * @ecc_data1: ecc code from nand spare area
671 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
672 * @page_data: page data
674 * This function compares two ECC's and indicates if there is an error.
675 * If the error can be corrected it will be corrected to the buffer.
676 * If there is no error, %0 is returned. If there is an error but it
677 * was corrected, %1 is returned. Otherwise, %-1 is returned.
679 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
680 u8 *ecc_data2, /* read from register */
684 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
685 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
692 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
694 gen_true_ecc(ecc_data1);
695 gen_true_ecc(ecc_data2);
697 for (i = 0; i <= 2; i++) {
698 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
699 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
702 for (i = 0; i < 8; i++) {
703 tmp0_bit[i] = *ecc_data1 % 2;
704 *ecc_data1 = *ecc_data1 / 2;
707 for (i = 0; i < 8; i++) {
708 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
709 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
712 for (i = 0; i < 8; i++) {
713 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
714 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
717 for (i = 0; i < 8; i++) {
718 comp0_bit[i] = *ecc_data2 % 2;
719 *ecc_data2 = *ecc_data2 / 2;
722 for (i = 0; i < 8; i++) {
723 comp1_bit[i] = *(ecc_data2 + 1) % 2;
724 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
727 for (i = 0; i < 8; i++) {
728 comp2_bit[i] = *(ecc_data2 + 2) % 2;
729 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
732 for (i = 0; i < 6; i++)
733 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
735 for (i = 0; i < 8; i++)
736 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
738 for (i = 0; i < 8; i++)
739 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
741 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
742 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
744 for (i = 0; i < 24; i++)
745 ecc_sum += ecc_bit[i];
749 /* Not reached because this function is not called if
750 * ECC values are equal
755 /* Uncorrectable error */
756 pr_debug("ECC UNCORRECTED_ERROR 1\n");
760 /* UN-Correctable error */
761 pr_debug("ECC UNCORRECTED_ERROR B\n");
765 /* Correctable error */
766 find_byte = (ecc_bit[23] << 8) +
776 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
778 pr_debug("Correcting single bit ECC error at offset: "
779 "%d, bit: %d\n", find_byte, find_bit);
781 page_data[find_byte] ^= (1 << find_bit);
786 if (ecc_data2[0] == 0 &&
791 pr_debug("UNCORRECTED_ERROR default\n");
797 * omap_correct_data - Compares the ECC read with HW generated ECC
798 * @mtd: MTD device structure
800 * @read_ecc: ecc read from nand flash
801 * @calc_ecc: ecc read from HW ECC registers
803 * Compares the ecc read from nand spare area with ECC registers values
804 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
805 * detection and correction. If there are no errors, %0 is returned. If
806 * there were errors and all of the errors were corrected, the number of
807 * corrected errors is returned. If uncorrectable errors exist, %-1 is
810 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
811 u_char *read_ecc, u_char *calc_ecc)
813 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
815 int blockCnt = 0, i = 0, ret = 0;
818 /* Ex NAND_ECC_HW12_2048 */
819 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
820 (info->nand.ecc.size == 2048))
825 for (i = 0; i < blockCnt; i++) {
826 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
827 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
830 /* keep track of the number of corrected errors */
841 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
842 * @mtd: MTD device structure
843 * @dat: The pointer to data on which ecc is computed
844 * @ecc_code: The ecc_code buffer
846 * Using noninverted ECC can be considered ugly since writing a blank
847 * page ie. padding will clear the ECC bytes. This is no problem as long
848 * nobody is trying to write data on the seemingly unused page. Reading
849 * an erased page will produce an ECC mismatch between generated and read
850 * ECC bytes that has to be dealt with separately.
852 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
855 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
857 return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
861 * omap_enable_hwecc - This function enables the hardware ecc functionality
862 * @mtd: MTD device structure
863 * @mode: Read/Write mode
865 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
867 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
869 struct nand_chip *chip = mtd->priv;
870 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
872 gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
876 * omap_wait - wait until the command is done
877 * @mtd: MTD device structure
878 * @chip: NAND Chip structure
880 * Wait function is called during Program and erase operations and
881 * the way it is called from MTD layer, we should wait till the NAND
882 * chip is ready after the programming/erase operation has completed.
884 * Erase can take up to 400ms and program up to 20ms according to
885 * general NAND and SmartMedia specs
887 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
889 struct nand_chip *this = mtd->priv;
890 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
892 unsigned long timeo = jiffies;
893 int status, state = this->state;
895 if (state == FL_ERASING)
896 timeo += (HZ * 400) / 1000;
898 timeo += (HZ * 20) / 1000;
900 gpmc_nand_write(info->gpmc_cs,
901 GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
902 while (time_before(jiffies, timeo)) {
903 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
904 if (status & NAND_STATUS_READY)
909 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
914 * omap_dev_ready - calls the platform specific dev_ready function
915 * @mtd: MTD device structure
917 static int omap_dev_ready(struct mtd_info *mtd)
919 unsigned int val = 0;
920 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
923 val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
924 if ((val & 0x100) == 0x100) {
925 /* Clear IRQ Interrupt */
928 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
930 unsigned int cnt = 0;
931 while (cnt++ < 0x1FF) {
932 if ((val & 0x100) == 0x100)
934 val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
941 #ifdef CONFIG_MTD_NAND_OMAP_BCH
944 * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
945 * @mtd: MTD device structure
946 * @mode: Read/Write mode
948 static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
951 unsigned int dev_width;
952 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
954 struct nand_chip *chip = mtd->priv;
956 nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4;
957 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
959 * Program GPMC to perform correction on one 512-byte sector at a time.
960 * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and
961 * gives a slight (5%) performance gain (but requires additional code).
963 (void)gpmc_enable_hwecc_bch(info->gpmc_cs, mode, dev_width, 1, nerrors);
967 * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
968 * @mtd: MTD device structure
969 * @dat: The pointer to data on which ecc is computed
970 * @ecc_code: The ecc_code buffer
972 static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
975 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
977 return gpmc_calculate_ecc_bch4(info->gpmc_cs, dat, ecc_code);
981 * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
982 * @mtd: MTD device structure
983 * @dat: The pointer to data on which ecc is computed
984 * @ecc_code: The ecc_code buffer
986 static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
989 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
991 return gpmc_calculate_ecc_bch8(info->gpmc_cs, dat, ecc_code);
995 * omap3_correct_data_bch - Decode received data and correct errors
996 * @mtd: MTD device structure
998 * @read_ecc: ecc read from nand flash
999 * @calc_ecc: ecc read from HW ECC registers
1001 static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data,
1002 u_char *read_ecc, u_char *calc_ecc)
1005 /* cannot correct more than 8 errors */
1006 unsigned int errloc[8];
1007 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1010 count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL,
1013 /* correct errors */
1014 for (i = 0; i < count; i++) {
1015 /* correct data only, not ecc bytes */
1016 if (errloc[i] < 8*512)
1017 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
1018 pr_debug("corrected bitflip %u\n", errloc[i]);
1020 } else if (count < 0) {
1021 pr_err("ecc unrecoverable error\n");
1027 * omap3_free_bch - Release BCH ecc resources
1028 * @mtd: MTD device structure
1030 static void omap3_free_bch(struct mtd_info *mtd)
1032 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1035 free_bch(info->bch);
1041 * omap3_init_bch - Initialize BCH ECC
1042 * @mtd: MTD device structure
1043 * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW)
1045 static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
1047 int ret, max_errors;
1048 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1050 #ifdef CONFIG_MTD_NAND_OMAP_BCH8
1051 const int hw_errors = 8;
1053 const int hw_errors = 4;
1057 max_errors = (ecc_opt == OMAP_ECC_BCH8_CODE_HW) ? 8 : 4;
1058 if (max_errors != hw_errors) {
1059 pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported",
1060 max_errors, hw_errors);
1064 /* initialize GPMC BCH engine */
1065 ret = gpmc_init_hwecc_bch(info->gpmc_cs, 1, max_errors);
1069 /* software bch library is only used to detect and locate errors */
1070 info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */);
1074 info->nand.ecc.size = 512;
1075 info->nand.ecc.hwctl = omap3_enable_hwecc_bch;
1076 info->nand.ecc.correct = omap3_correct_data_bch;
1077 info->nand.ecc.mode = NAND_ECC_HW;
1080 * The number of corrected errors in an ecc block that will trigger
1081 * block scrubbing defaults to the ecc strength (4 or 8).
1082 * Set mtd->bitflip_threshold here to define a custom threshold.
1085 if (max_errors == 8) {
1086 info->nand.ecc.strength = 8;
1087 info->nand.ecc.bytes = 13;
1088 info->nand.ecc.calculate = omap3_calculate_ecc_bch8;
1090 info->nand.ecc.strength = 4;
1091 info->nand.ecc.bytes = 7;
1092 info->nand.ecc.calculate = omap3_calculate_ecc_bch4;
1095 pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors);
1098 omap3_free_bch(mtd);
1103 * omap3_init_bch_tail - Build an oob layout for BCH ECC correction.
1104 * @mtd: MTD device structure
1106 static int omap3_init_bch_tail(struct mtd_info *mtd)
1109 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1111 struct nand_ecclayout *layout = &info->ecclayout;
1113 /* build oob layout */
1114 steps = mtd->writesize/info->nand.ecc.size;
1115 layout->eccbytes = steps*info->nand.ecc.bytes;
1117 /* do not bother creating special oob layouts for small page devices */
1118 if (mtd->oobsize < 64) {
1119 pr_err("BCH ecc is not supported on small page devices\n");
1123 /* reserve 2 bytes for bad block marker */
1124 if (layout->eccbytes+2 > mtd->oobsize) {
1125 pr_err("no oob layout available for oobsize %d eccbytes %u\n",
1126 mtd->oobsize, layout->eccbytes);
1130 /* put ecc bytes at oob tail */
1131 for (i = 0; i < layout->eccbytes; i++)
1132 layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i;
1134 layout->oobfree[0].offset = 2;
1135 layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
1136 info->nand.ecc.layout = layout;
1138 if (!(info->nand.options & NAND_BUSWIDTH_16))
1139 info->nand.badblock_pattern = &bb_descrip_flashbased;
1142 omap3_free_bch(mtd);
1147 static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
1149 pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n");
1152 static int omap3_init_bch_tail(struct mtd_info *mtd)
1156 static void omap3_free_bch(struct mtd_info *mtd)
1159 #endif /* CONFIG_MTD_NAND_OMAP_BCH */
1161 static int __devinit omap_nand_probe(struct platform_device *pdev)
1163 struct omap_nand_info *info;
1164 struct omap_nand_platform_data *pdata;
1168 pdata = pdev->dev.platform_data;
1169 if (pdata == NULL) {
1170 dev_err(&pdev->dev, "platform data missing\n");
1174 info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
1178 platform_set_drvdata(pdev, info);
1180 spin_lock_init(&info->controller.lock);
1181 init_waitqueue_head(&info->controller.wq);
1185 info->gpmc_cs = pdata->cs;
1186 info->phys_base = pdata->phys_base;
1188 info->mtd.priv = &info->nand;
1189 info->mtd.name = dev_name(&pdev->dev);
1190 info->mtd.owner = THIS_MODULE;
1192 info->nand.options = pdata->devsize;
1193 info->nand.options |= NAND_SKIP_BBTSCAN;
1195 /* NAND write protect off */
1196 gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
1198 if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
1199 pdev->dev.driver->name)) {
1204 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
1205 if (!info->nand.IO_ADDR_R) {
1207 goto out_release_mem_region;
1210 info->nand.controller = &info->controller;
1212 info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
1213 info->nand.cmd_ctrl = omap_hwcontrol;
1216 * If RDY/BSY line is connected to OMAP then use the omap ready
1217 * funcrtion and the generic nand_wait function which reads the status
1218 * register after monitoring the RDY/BSY line.Otherwise use a standard
1219 * chip delay which is slightly more than tR (AC Timing) of the NAND
1220 * device and read status register until you get a failure or success
1222 if (pdata->dev_ready) {
1223 info->nand.dev_ready = omap_dev_ready;
1224 info->nand.chip_delay = 0;
1226 info->nand.waitfunc = omap_wait;
1227 info->nand.chip_delay = 50;
1230 switch (pdata->xfer_type) {
1231 case NAND_OMAP_PREFETCH_POLLED:
1232 info->nand.read_buf = omap_read_buf_pref;
1233 info->nand.write_buf = omap_write_buf_pref;
1236 case NAND_OMAP_POLLED:
1237 if (info->nand.options & NAND_BUSWIDTH_16) {
1238 info->nand.read_buf = omap_read_buf16;
1239 info->nand.write_buf = omap_write_buf16;
1241 info->nand.read_buf = omap_read_buf8;
1242 info->nand.write_buf = omap_write_buf8;
1246 case NAND_OMAP_PREFETCH_DMA:
1247 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
1248 omap_nand_dma_cb, &info->comp, &info->dma_ch);
1251 dev_err(&pdev->dev, "DMA request failed!\n");
1252 goto out_release_mem_region;
1254 omap_set_dma_dest_burst_mode(info->dma_ch,
1255 OMAP_DMA_DATA_BURST_16);
1256 omap_set_dma_src_burst_mode(info->dma_ch,
1257 OMAP_DMA_DATA_BURST_16);
1259 info->nand.read_buf = omap_read_buf_dma_pref;
1260 info->nand.write_buf = omap_write_buf_dma_pref;
1264 case NAND_OMAP_PREFETCH_IRQ:
1265 err = request_irq(pdata->gpmc_irq,
1266 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1268 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1269 pdata->gpmc_irq, err);
1270 goto out_release_mem_region;
1272 info->gpmc_irq = pdata->gpmc_irq;
1273 info->nand.read_buf = omap_read_buf_irq_pref;
1274 info->nand.write_buf = omap_write_buf_irq_pref;
1280 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1282 goto out_release_mem_region;
1285 info->nand.verify_buf = omap_verify_buf;
1287 /* selsect the ecc type */
1288 if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1289 info->nand.ecc.mode = NAND_ECC_SOFT;
1290 else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1291 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1292 info->nand.ecc.bytes = 3;
1293 info->nand.ecc.size = 512;
1294 info->nand.ecc.strength = 1;
1295 info->nand.ecc.calculate = omap_calculate_ecc;
1296 info->nand.ecc.hwctl = omap_enable_hwecc;
1297 info->nand.ecc.correct = omap_correct_data;
1298 info->nand.ecc.mode = NAND_ECC_HW;
1299 } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
1300 (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
1301 err = omap3_init_bch(&info->mtd, pdata->ecc_opt);
1304 goto out_release_mem_region;
1308 /* DIP switches on some boards change between 8 and 16 bit
1309 * bus widths for flash. Try the other width if the first try fails.
1311 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1312 info->nand.options ^= NAND_BUSWIDTH_16;
1313 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1315 goto out_release_mem_region;
1319 /* rom code layout */
1320 if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1322 if (info->nand.options & NAND_BUSWIDTH_16)
1326 info->nand.badblock_pattern = &bb_descrip_flashbased;
1328 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1329 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1330 omap_oobinfo.eccpos[i] = i+offset;
1332 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1333 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1334 (offset + omap_oobinfo.eccbytes);
1336 info->nand.ecc.layout = &omap_oobinfo;
1337 } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
1338 (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
1339 /* build OOB layout for BCH ECC correction */
1340 err = omap3_init_bch_tail(&info->mtd);
1343 goto out_release_mem_region;
1347 /* second phase scan */
1348 if (nand_scan_tail(&info->mtd)) {
1350 goto out_release_mem_region;
1353 mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
1356 platform_set_drvdata(pdev, &info->mtd);
1360 out_release_mem_region:
1361 release_mem_region(info->phys_base, NAND_IO_SIZE);
1368 static int omap_nand_remove(struct platform_device *pdev)
1370 struct mtd_info *mtd = platform_get_drvdata(pdev);
1371 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1373 omap3_free_bch(&info->mtd);
1375 platform_set_drvdata(pdev, NULL);
1376 if (info->dma_ch != -1)
1377 omap_free_dma(info->dma_ch);
1380 free_irq(info->gpmc_irq, info);
1382 /* Release NAND device, its internal structures and partitions */
1383 nand_release(&info->mtd);
1384 iounmap(info->nand.IO_ADDR_R);
1389 static struct platform_driver omap_nand_driver = {
1390 .probe = omap_nand_probe,
1391 .remove = omap_nand_remove,
1393 .name = DRIVER_NAME,
1394 .owner = THIS_MODULE,
1398 module_platform_driver(omap_nand_driver);
1400 MODULE_ALIAS("platform:" DRIVER_NAME);
1401 MODULE_LICENSE("GPL");
1402 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");