1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * MTK ECC controller driver.
4 * Copyright (C) 2016 MediaTek Inc.
5 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
9 #include <linux/platform_device.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/iopoll.h>
16 #include <linux/of_platform.h>
17 #include <linux/mutex.h>
18 #include <linux/mtd/nand-ecc-mtk.h>
20 #define ECC_IDLE_MASK BIT(0)
21 #define ECC_IRQ_EN BIT(0)
22 #define ECC_PG_IRQ_SEL BIT(1)
23 #define ECC_OP_ENABLE (1)
24 #define ECC_OP_DISABLE (0)
26 #define ECC_ENCCON (0x00)
27 #define ECC_ENCCNFG (0x04)
28 #define ECC_MS_SHIFT (16)
29 #define ECC_ENCDIADDR (0x08)
30 #define ECC_ENCIDLE (0x0C)
31 #define ECC_DECCON (0x100)
32 #define ECC_DECCNFG (0x104)
33 #define DEC_EMPTY_EN BIT(31)
34 #define DEC_CNFG_CORRECT (0x3 << 12)
35 #define ECC_DECIDLE (0x10C)
36 #define ECC_DECENUM0 (0x114)
38 #define ECC_TIMEOUT (500000)
40 #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
41 #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
45 const u8 *ecc_strength;
55 const struct mtk_ecc_caps *caps;
59 struct completion done;
66 /* ecc strength that each IP supports */
67 static const u8 ecc_strength_mt2701[] = {
68 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
69 40, 44, 48, 52, 56, 60
72 static const u8 ecc_strength_mt2712[] = {
73 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
74 40, 44, 48, 52, 56, 60, 68, 72, 80
77 static const u8 ecc_strength_mt7622[] = {
78 4, 6, 8, 10, 12, 14, 16
90 static int mt2701_ecc_regs[] = {
91 [ECC_ENCPAR00] = 0x10,
92 [ECC_ENCIRQ_EN] = 0x80,
93 [ECC_ENCIRQ_STA] = 0x84,
94 [ECC_DECDONE] = 0x124,
95 [ECC_DECIRQ_EN] = 0x200,
96 [ECC_DECIRQ_STA] = 0x204,
99 static int mt2712_ecc_regs[] = {
100 [ECC_ENCPAR00] = 0x300,
101 [ECC_ENCIRQ_EN] = 0x80,
102 [ECC_ENCIRQ_STA] = 0x84,
103 [ECC_DECDONE] = 0x124,
104 [ECC_DECIRQ_EN] = 0x200,
105 [ECC_DECIRQ_STA] = 0x204,
108 static int mt7622_ecc_regs[] = {
109 [ECC_ENCPAR00] = 0x10,
110 [ECC_ENCIRQ_EN] = 0x30,
111 [ECC_ENCIRQ_STA] = 0x34,
112 [ECC_DECDONE] = 0x11c,
113 [ECC_DECIRQ_EN] = 0x140,
114 [ECC_DECIRQ_STA] = 0x144,
117 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
118 enum mtk_ecc_operation op)
120 struct device *dev = ecc->dev;
124 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
128 dev_warn(dev, "%s NOT idle\n",
129 op == ECC_ENCODE ? "encoder" : "decoder");
132 static irqreturn_t mtk_ecc_irq(int irq, void *id)
134 struct mtk_ecc *ecc = id;
137 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
140 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
141 if (dec & ecc->sectors) {
143 * Clear decode IRQ status once again to ensure that
144 * there will be no extra IRQ.
146 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
148 complete(&ecc->done);
153 enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
156 complete(&ecc->done);
164 static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
166 u32 ecc_bit, dec_sz, enc_sz;
169 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
170 if (ecc->caps->ecc_strength[i] == config->strength)
174 if (i == ecc->caps->num_ecc_strength) {
175 dev_err(ecc->dev, "invalid ecc strength %d\n",
182 if (config->op == ECC_ENCODE) {
183 /* configure ECC encoder (in bits) */
184 enc_sz = config->len << 3;
186 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
187 reg |= (enc_sz << ECC_MS_SHIFT);
188 writel(reg, ecc->regs + ECC_ENCCNFG);
190 if (config->mode != ECC_NFI_MODE)
191 writel(lower_32_bits(config->addr),
192 ecc->regs + ECC_ENCDIADDR);
195 /* configure ECC decoder (in bits) */
196 dec_sz = (config->len << 3) +
197 config->strength * ecc->caps->parity_bits;
199 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
200 reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
202 writel(reg, ecc->regs + ECC_DECCNFG);
205 ecc->sectors = 1 << (config->sectors - 1);
211 void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
217 stats->corrected = 0;
220 for (i = 0; i < sectors; i++) {
221 offset = (i >> 2) << 2;
222 err = readl(ecc->regs + ECC_DECENUM0 + offset);
223 err = err >> ((i % 4) * 8);
224 err &= ecc->caps->err_mask;
225 if (err == ecc->caps->err_mask) {
226 /* uncorrectable errors */
231 stats->corrected += err;
232 bitflips = max_t(u32, bitflips, err);
235 stats->bitflips = bitflips;
237 EXPORT_SYMBOL(mtk_ecc_get_stats);
239 void mtk_ecc_release(struct mtk_ecc *ecc)
241 clk_disable_unprepare(ecc->clk);
242 put_device(ecc->dev);
244 EXPORT_SYMBOL(mtk_ecc_release);
246 static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
248 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
249 writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
251 mtk_ecc_wait_idle(ecc, ECC_DECODE);
252 writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
255 static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
257 struct platform_device *pdev;
260 pdev = of_find_device_by_node(np);
262 return ERR_PTR(-EPROBE_DEFER);
264 ecc = platform_get_drvdata(pdev);
266 put_device(&pdev->dev);
267 return ERR_PTR(-EPROBE_DEFER);
270 clk_prepare_enable(ecc->clk);
271 mtk_ecc_hw_init(ecc);
276 struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
278 struct mtk_ecc *ecc = NULL;
279 struct device_node *np;
281 np = of_parse_phandle(of_node, "nand-ecc-engine", 0);
282 /* for backward compatibility */
284 np = of_parse_phandle(of_node, "ecc-engine", 0);
286 ecc = mtk_ecc_get(np);
292 EXPORT_SYMBOL(of_mtk_ecc_get);
294 int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
296 enum mtk_ecc_operation op = config->op;
300 ret = mutex_lock_interruptible(&ecc->lock);
302 dev_err(ecc->dev, "interrupted when attempting to lock\n");
306 mtk_ecc_wait_idle(ecc, op);
308 ret = mtk_ecc_config(ecc, config);
310 mutex_unlock(&ecc->lock);
314 if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
315 init_completion(&ecc->done);
316 reg_val = ECC_IRQ_EN;
318 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
319 * means this chip can only generate one ecc irq during page
320 * read / write. If is 0, generate one ecc irq each ecc step.
322 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
323 reg_val |= ECC_PG_IRQ_SEL;
324 if (op == ECC_ENCODE)
325 writew(reg_val, ecc->regs +
326 ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
328 writew(reg_val, ecc->regs +
329 ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
332 writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
336 EXPORT_SYMBOL(mtk_ecc_enable);
338 void mtk_ecc_disable(struct mtk_ecc *ecc)
340 enum mtk_ecc_operation op = ECC_ENCODE;
342 /* find out the running operation */
343 if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
347 mtk_ecc_wait_idle(ecc, op);
348 if (op == ECC_DECODE) {
350 * Clear decode IRQ status in case there is a timeout to wait
353 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
354 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
356 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
359 writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
361 mutex_unlock(&ecc->lock);
363 EXPORT_SYMBOL(mtk_ecc_disable);
365 int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
369 ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
371 dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
372 (op == ECC_ENCODE) ? "encoder" : "decoder");
378 EXPORT_SYMBOL(mtk_ecc_wait_done);
380 int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
387 addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
388 ret = dma_mapping_error(ecc->dev, addr);
390 dev_err(ecc->dev, "dma mapping error\n");
394 config->op = ECC_ENCODE;
396 ret = mtk_ecc_enable(ecc, config);
398 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
402 ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
406 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
408 /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
409 len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
411 /* write the parity bytes generated by the ECC back to temp buffer */
412 __ioread32_copy(ecc->eccdata,
413 ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
416 /* copy into possibly unaligned OOB region with actual length */
417 memcpy(data + bytes, ecc->eccdata, len);
420 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
421 mtk_ecc_disable(ecc);
425 EXPORT_SYMBOL(mtk_ecc_encode);
427 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
429 const u8 *ecc_strength = ecc->caps->ecc_strength;
432 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
433 if (*p <= ecc_strength[i]) {
435 *p = ecc_strength[i];
436 else if (*p != ecc_strength[i])
437 *p = ecc_strength[i - 1];
442 *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
444 EXPORT_SYMBOL(mtk_ecc_adjust_strength);
446 unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
448 return ecc->caps->parity_bits;
450 EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
452 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
454 .ecc_strength = ecc_strength_mt2701,
455 .ecc_regs = mt2701_ecc_regs,
456 .num_ecc_strength = 20,
462 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
464 .ecc_strength = ecc_strength_mt2712,
465 .ecc_regs = mt2712_ecc_regs,
466 .num_ecc_strength = 23,
472 static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
474 .ecc_strength = ecc_strength_mt7622,
475 .ecc_regs = mt7622_ecc_regs,
476 .num_ecc_strength = 7,
482 static const struct of_device_id mtk_ecc_dt_match[] = {
484 .compatible = "mediatek,mt2701-ecc",
485 .data = &mtk_ecc_caps_mt2701,
487 .compatible = "mediatek,mt2712-ecc",
488 .data = &mtk_ecc_caps_mt2712,
490 .compatible = "mediatek,mt7622-ecc",
491 .data = &mtk_ecc_caps_mt7622,
496 static int mtk_ecc_probe(struct platform_device *pdev)
498 struct device *dev = &pdev->dev;
500 u32 max_eccdata_size;
503 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
507 ecc->caps = of_device_get_match_data(dev);
509 max_eccdata_size = ecc->caps->num_ecc_strength - 1;
510 max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
511 max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
512 max_eccdata_size = round_up(max_eccdata_size, 4);
513 ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
517 ecc->regs = devm_platform_ioremap_resource(pdev, 0);
518 if (IS_ERR(ecc->regs))
519 return PTR_ERR(ecc->regs);
521 ecc->clk = devm_clk_get(dev, NULL);
522 if (IS_ERR(ecc->clk)) {
523 dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
524 return PTR_ERR(ecc->clk);
527 irq = platform_get_irq(pdev, 0);
531 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
533 dev_err(dev, "failed to set DMA mask\n");
537 ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
539 dev_err(dev, "failed to request irq\n");
544 mutex_init(&ecc->lock);
545 platform_set_drvdata(pdev, ecc);
546 dev_info(dev, "probed\n");
551 #ifdef CONFIG_PM_SLEEP
552 static int mtk_ecc_suspend(struct device *dev)
554 struct mtk_ecc *ecc = dev_get_drvdata(dev);
556 clk_disable_unprepare(ecc->clk);
561 static int mtk_ecc_resume(struct device *dev)
563 struct mtk_ecc *ecc = dev_get_drvdata(dev);
566 ret = clk_prepare_enable(ecc->clk);
568 dev_err(dev, "failed to enable clk\n");
575 static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
578 MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
580 static struct platform_driver mtk_ecc_driver = {
581 .probe = mtk_ecc_probe,
584 .of_match_table = mtk_ecc_dt_match,
585 #ifdef CONFIG_PM_SLEEP
586 .pm = &mtk_ecc_pm_ops,
591 module_platform_driver(mtk_ecc_driver);
593 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
594 MODULE_DESCRIPTION("MTK Nand ECC Driver");
595 MODULE_LICENSE("Dual MIT/GPL");