2 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller
4 * Author: Angus Clark <angus.clark@st.com>
6 * Copyright (C) 2010-2014 STicroelectronics Limited
8 * JEDEC probe based on drivers/mtd/devices/m25p80.c
10 * This code is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/regmap.h>
18 #include <linux/platform_device.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/sched.h>
22 #include <linux/delay.h>
26 #include "serial_flash_cmds.h"
29 * FSM SPI Controller Registers
31 #define SPI_CLOCKDIV 0x0010
32 #define SPI_MODESELECT 0x0018
33 #define SPI_CONFIGDATA 0x0020
34 #define SPI_STA_MODE_CHANGE 0x0028
35 #define SPI_FAST_SEQ_TRANSFER_SIZE 0x0100
36 #define SPI_FAST_SEQ_ADD1 0x0104
37 #define SPI_FAST_SEQ_ADD2 0x0108
38 #define SPI_FAST_SEQ_ADD_CFG 0x010c
39 #define SPI_FAST_SEQ_OPC1 0x0110
40 #define SPI_FAST_SEQ_OPC2 0x0114
41 #define SPI_FAST_SEQ_OPC3 0x0118
42 #define SPI_FAST_SEQ_OPC4 0x011c
43 #define SPI_FAST_SEQ_OPC5 0x0120
44 #define SPI_MODE_BITS 0x0124
45 #define SPI_DUMMY_BITS 0x0128
46 #define SPI_FAST_SEQ_FLASH_STA_DATA 0x012c
47 #define SPI_FAST_SEQ_1 0x0130
48 #define SPI_FAST_SEQ_2 0x0134
49 #define SPI_FAST_SEQ_3 0x0138
50 #define SPI_FAST_SEQ_4 0x013c
51 #define SPI_FAST_SEQ_CFG 0x0140
52 #define SPI_FAST_SEQ_STA 0x0144
53 #define SPI_QUAD_BOOT_SEQ_INIT_1 0x0148
54 #define SPI_QUAD_BOOT_SEQ_INIT_2 0x014c
55 #define SPI_QUAD_BOOT_READ_SEQ_1 0x0150
56 #define SPI_QUAD_BOOT_READ_SEQ_2 0x0154
57 #define SPI_PROGRAM_ERASE_TIME 0x0158
58 #define SPI_MULT_PAGE_REPEAT_SEQ_1 0x015c
59 #define SPI_MULT_PAGE_REPEAT_SEQ_2 0x0160
60 #define SPI_STATUS_WR_TIME_REG 0x0164
61 #define SPI_FAST_SEQ_DATA_REG 0x0300
64 * Register: SPI_MODESELECT
66 #define SPI_MODESELECT_CONTIG 0x01
67 #define SPI_MODESELECT_FASTREAD 0x02
68 #define SPI_MODESELECT_DUALIO 0x04
69 #define SPI_MODESELECT_FSM 0x08
70 #define SPI_MODESELECT_QUADBOOT 0x10
73 * Register: SPI_CONFIGDATA
75 #define SPI_CFG_DEVICE_ST 0x1
76 #define SPI_CFG_DEVICE_ATMEL 0x4
77 #define SPI_CFG_MIN_CS_HIGH(x) (((x) & 0xfff) << 4)
78 #define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16)
79 #define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24)
81 #define SPI_CFG_DEFAULT_MIN_CS_HIGH SPI_CFG_MIN_CS_HIGH(0x0AA)
82 #define SPI_CFG_DEFAULT_CS_SETUPHOLD SPI_CFG_CS_SETUPHOLD(0xA0)
83 #define SPI_CFG_DEFAULT_DATA_HOLD SPI_CFG_DATA_HOLD(0x00)
86 * Register: SPI_FAST_SEQ_TRANSFER_SIZE
88 #define TRANSFER_SIZE(x) ((x) * 8)
91 * Register: SPI_FAST_SEQ_ADD_CFG
93 #define ADR_CFG_CYCLES_ADD1(x) ((x) << 0)
94 #define ADR_CFG_PADS_1_ADD1 (0x0 << 6)
95 #define ADR_CFG_PADS_2_ADD1 (0x1 << 6)
96 #define ADR_CFG_PADS_4_ADD1 (0x3 << 6)
97 #define ADR_CFG_CSDEASSERT_ADD1 (1 << 8)
98 #define ADR_CFG_CYCLES_ADD2(x) ((x) << (0+16))
99 #define ADR_CFG_PADS_1_ADD2 (0x0 << (6+16))
100 #define ADR_CFG_PADS_2_ADD2 (0x1 << (6+16))
101 #define ADR_CFG_PADS_4_ADD2 (0x3 << (6+16))
102 #define ADR_CFG_CSDEASSERT_ADD2 (1 << (8+16))
105 * Register: SPI_FAST_SEQ_n
107 #define SEQ_OPC_OPCODE(x) ((x) << 0)
108 #define SEQ_OPC_CYCLES(x) ((x) << 8)
109 #define SEQ_OPC_PADS_1 (0x0 << 14)
110 #define SEQ_OPC_PADS_2 (0x1 << 14)
111 #define SEQ_OPC_PADS_4 (0x3 << 14)
112 #define SEQ_OPC_CSDEASSERT (1 << 16)
115 * Register: SPI_FAST_SEQ_CFG
117 #define SEQ_CFG_STARTSEQ (1 << 0)
118 #define SEQ_CFG_SWRESET (1 << 5)
119 #define SEQ_CFG_CSDEASSERT (1 << 6)
120 #define SEQ_CFG_READNOTWRITE (1 << 7)
121 #define SEQ_CFG_ERASE (1 << 8)
122 #define SEQ_CFG_PADS_1 (0x0 << 16)
123 #define SEQ_CFG_PADS_2 (0x1 << 16)
124 #define SEQ_CFG_PADS_4 (0x3 << 16)
127 * Register: SPI_MODE_BITS
129 #define MODE_DATA(x) (x & 0xff)
130 #define MODE_CYCLES(x) ((x & 0x3f) << 16)
131 #define MODE_PADS_1 (0x0 << 22)
132 #define MODE_PADS_2 (0x1 << 22)
133 #define MODE_PADS_4 (0x3 << 22)
134 #define DUMMY_CSDEASSERT (1 << 24)
137 * Register: SPI_DUMMY_BITS
139 #define DUMMY_CYCLES(x) ((x & 0x3f) << 16)
140 #define DUMMY_PADS_1 (0x0 << 22)
141 #define DUMMY_PADS_2 (0x1 << 22)
142 #define DUMMY_PADS_4 (0x3 << 22)
143 #define DUMMY_CSDEASSERT (1 << 24)
146 * Register: SPI_FAST_SEQ_FLASH_STA_DATA
148 #define STA_DATA_BYTE1(x) ((x & 0xff) << 0)
149 #define STA_DATA_BYTE2(x) ((x & 0xff) << 8)
150 #define STA_PADS_1 (0x0 << 16)
151 #define STA_PADS_2 (0x1 << 16)
152 #define STA_PADS_4 (0x3 << 16)
153 #define STA_CSDEASSERT (0x1 << 20)
154 #define STA_RDNOTWR (0x1 << 21)
157 * FSM SPI Instruction Opcodes
159 #define STFSM_OPC_CMD 0x1
160 #define STFSM_OPC_ADD 0x2
161 #define STFSM_OPC_STA 0x3
162 #define STFSM_OPC_MODE 0x4
163 #define STFSM_OPC_DUMMY 0x5
164 #define STFSM_OPC_DATA 0x6
165 #define STFSM_OPC_WAIT 0x7
166 #define STFSM_OPC_JUMP 0x8
167 #define STFSM_OPC_GOTO 0x9
168 #define STFSM_OPC_STOP 0xF
171 * FSM SPI Instructions (== opcode + operand).
173 #define STFSM_INSTR(cmd, op) ((cmd) | ((op) << 4))
175 #define STFSM_INST_CMD1 STFSM_INSTR(STFSM_OPC_CMD, 1)
176 #define STFSM_INST_CMD2 STFSM_INSTR(STFSM_OPC_CMD, 2)
177 #define STFSM_INST_CMD3 STFSM_INSTR(STFSM_OPC_CMD, 3)
178 #define STFSM_INST_CMD4 STFSM_INSTR(STFSM_OPC_CMD, 4)
179 #define STFSM_INST_CMD5 STFSM_INSTR(STFSM_OPC_CMD, 5)
180 #define STFSM_INST_ADD1 STFSM_INSTR(STFSM_OPC_ADD, 1)
181 #define STFSM_INST_ADD2 STFSM_INSTR(STFSM_OPC_ADD, 2)
183 #define STFSM_INST_DATA_WRITE STFSM_INSTR(STFSM_OPC_DATA, 1)
184 #define STFSM_INST_DATA_READ STFSM_INSTR(STFSM_OPC_DATA, 2)
186 #define STFSM_INST_STA_RD1 STFSM_INSTR(STFSM_OPC_STA, 0x1)
187 #define STFSM_INST_STA_WR1 STFSM_INSTR(STFSM_OPC_STA, 0x1)
188 #define STFSM_INST_STA_RD2 STFSM_INSTR(STFSM_OPC_STA, 0x2)
189 #define STFSM_INST_STA_WR1_2 STFSM_INSTR(STFSM_OPC_STA, 0x3)
191 #define STFSM_INST_MODE STFSM_INSTR(STFSM_OPC_MODE, 0)
192 #define STFSM_INST_DUMMY STFSM_INSTR(STFSM_OPC_DUMMY, 0)
193 #define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0)
194 #define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0)
196 #define STFSM_DEFAULT_EMI_FREQ 100000000UL /* 100 MHz */
197 #define STFSM_DEFAULT_WR_TIME (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */
199 #define STFSM_FLASH_SAFE_FREQ 10000000UL /* 10 MHz */
201 #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */
204 #define FLASH_CMD_WREN 0x06
205 #define FLASH_CMD_WRDI 0x04
206 #define FLASH_CMD_RDID 0x9f
207 #define FLASH_CMD_RDSR 0x05
208 #define FLASH_CMD_RDSR2 0x35
209 #define FLASH_CMD_WRSR 0x01
210 #define FLASH_CMD_SE_4K 0x20
211 #define FLASH_CMD_SE_32K 0x52
212 #define FLASH_CMD_SE 0xd8
213 #define FLASH_CMD_CHIPERASE 0xc7
214 #define FLASH_CMD_WRVCR 0x81
215 #define FLASH_CMD_RDVCR 0x85
217 #define FLASH_CMD_READ 0x03 /* READ */
218 #define FLASH_CMD_READ_FAST 0x0b /* FAST READ */
219 #define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */
220 #define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */
221 #define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */
222 #define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */
224 #define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */
225 #define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
226 #define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
227 #define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
228 #define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
230 #define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */
231 #define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */
233 /* READ commands with 32-bit addressing (N25Q256 and S25FLxxxS) */
234 #define FLASH_CMD_READ4 0x13
235 #define FLASH_CMD_READ4_FAST 0x0c
236 #define FLASH_CMD_READ4_1_1_2 0x3c
237 #define FLASH_CMD_READ4_1_2_2 0xbc
238 #define FLASH_CMD_READ4_1_1_4 0x6c
239 #define FLASH_CMD_READ4_1_4_4 0xec
241 #define FLASH_PAGESIZE 256 /* In Bytes */
242 #define FLASH_PAGESIZE_32 (FLASH_PAGESIZE / 4) /* In uint32_t */
245 * Flags to tweak operation of default read/write/erase routines
247 #define CFG_READ_TOGGLE_32BIT_ADDR 0x00000001
248 #define CFG_WRITE_TOGGLE_32BIT_ADDR 0x00000002
249 #define CFG_WRITE_EX_32BIT_ADDR_DELAY 0x00000004
250 #define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0x00000008
251 #define CFG_S25FL_CHECK_ERROR_FLAGS 0x00000010
256 struct resource *region;
259 struct flash_info *info;
261 uint32_t configuration;
262 uint32_t fifo_dir_delay;
263 bool booted_from_spi;
279 } __packed __aligned(4);
281 /* Parameters to configure a READ or WRITE FSM sequence */
282 struct seq_rw_config {
283 uint32_t flags; /* flags to support config */
284 uint8_t cmd; /* FLASH command */
285 int write; /* Write Sequence */
286 uint8_t addr_pads; /* No. of addr pads (MODE & DUMMY) */
287 uint8_t data_pads; /* No. of data pads */
288 uint8_t mode_data; /* MODE data */
289 uint8_t mode_cycles; /* No. of MODE cycles */
290 uint8_t dummy_cycles; /* No. of DUMMY cycles */
293 /* SPI Flash Device Table */
297 * JEDEC id zero means "no ID" (most older chips); otherwise it has
298 * a high byte of zero plus three data bytes: the manufacturer id,
299 * then a two byte device id.
304 * The size listed here is what works with FLASH_CMD_SE, which isn't
305 * necessarily called a "sector" by the vendor.
307 unsigned sector_size;
311 * Note, where FAST_READ is supported, freq_max specifies the
312 * FAST_READ frequency, not the READ frequency.
315 int (*config)(struct stfsm *);
318 static int stfsm_n25q_config(struct stfsm *fsm);
320 static struct flash_info flash_types[] = {
322 * ST Microelectronics/Numonyx --
323 * (newer production versions may have feature updates
324 * (eg faster operating frequency)
326 #define M25P_FLAG (FLASH_FLAG_READ_WRITE | FLASH_FLAG_READ_FAST)
327 { "m25p40", 0x202013, 0, 64 * 1024, 8, M25P_FLAG, 25, NULL },
328 { "m25p80", 0x202014, 0, 64 * 1024, 16, M25P_FLAG, 25, NULL },
329 { "m25p16", 0x202015, 0, 64 * 1024, 32, M25P_FLAG, 25, NULL },
330 { "m25p32", 0x202016, 0, 64 * 1024, 64, M25P_FLAG, 50, NULL },
331 { "m25p64", 0x202017, 0, 64 * 1024, 128, M25P_FLAG, 50, NULL },
332 { "m25p128", 0x202018, 0, 256 * 1024, 64, M25P_FLAG, 50, NULL },
334 #define M25PX_FLAG (FLASH_FLAG_READ_WRITE | \
335 FLASH_FLAG_READ_FAST | \
336 FLASH_FLAG_READ_1_1_2 | \
337 FLASH_FLAG_WRITE_1_1_2)
338 { "m25px32", 0x207116, 0, 64 * 1024, 64, M25PX_FLAG, 75, NULL },
339 { "m25px64", 0x207117, 0, 64 * 1024, 128, M25PX_FLAG, 75, NULL },
341 #define MX25_FLAG (FLASH_FLAG_READ_WRITE | \
342 FLASH_FLAG_READ_FAST | \
343 FLASH_FLAG_READ_1_1_2 | \
344 FLASH_FLAG_READ_1_2_2 | \
345 FLASH_FLAG_READ_1_1_4 | \
346 FLASH_FLAG_READ_1_4_4 | \
349 { "mx25l25635e", 0xc22019, 0, 64*1024, 512,
350 (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70, NULL }
352 #define N25Q_FLAG (FLASH_FLAG_READ_WRITE | \
353 FLASH_FLAG_READ_FAST | \
354 FLASH_FLAG_READ_1_1_2 | \
355 FLASH_FLAG_READ_1_2_2 | \
356 FLASH_FLAG_READ_1_1_4 | \
357 FLASH_FLAG_READ_1_4_4 | \
358 FLASH_FLAG_WRITE_1_1_2 | \
359 FLASH_FLAG_WRITE_1_2_2 | \
360 FLASH_FLAG_WRITE_1_1_4 | \
361 FLASH_FLAG_WRITE_1_4_4)
362 { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108,
364 { "n25q256", 0x20ba19, 0, 64 * 1024, 512,
365 N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config },
369 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
371 #define S25FLXXXP_FLAG (FLASH_FLAG_READ_WRITE | \
372 FLASH_FLAG_READ_1_1_2 | \
373 FLASH_FLAG_READ_1_2_2 | \
374 FLASH_FLAG_READ_1_1_4 | \
375 FLASH_FLAG_READ_1_4_4 | \
376 FLASH_FLAG_WRITE_1_1_4 | \
377 FLASH_FLAG_READ_FAST)
378 { "s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, S25FLXXXP_FLAG, 80,
380 { "s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, S25FLXXXP_FLAG, 80,
385 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
386 * - RESET# signal supported by die but not bristled out on all
387 * package types. The package type is a function of board design,
388 * so this information is captured in the board's flags.
389 * - Supports 'DYB' sector protection. Depending on variant, sectors
390 * may default to locked state on power-on.
392 #define S25FLXXXS_FLAG (S25FLXXXP_FLAG | \
394 FLASH_FLAG_DYB_LOCKING)
395 { "s25fl128s0", 0x012018, 0x0300, 256 * 1024, 64, S25FLXXXS_FLAG, 80,
397 { "s25fl128s1", 0x012018, 0x0301, 64 * 1024, 256, S25FLXXXS_FLAG, 80,
399 { "s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128,
400 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, NULL },
401 { "s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512,
402 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, NULL },
404 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
405 #define W25X_FLAG (FLASH_FLAG_READ_WRITE | \
406 FLASH_FLAG_READ_FAST | \
407 FLASH_FLAG_READ_1_1_2 | \
408 FLASH_FLAG_WRITE_1_1_2)
409 { "w25x40", 0xef3013, 0, 64 * 1024, 8, W25X_FLAG, 75, NULL },
410 { "w25x80", 0xef3014, 0, 64 * 1024, 16, W25X_FLAG, 75, NULL },
411 { "w25x16", 0xef3015, 0, 64 * 1024, 32, W25X_FLAG, 75, NULL },
412 { "w25x32", 0xef3016, 0, 64 * 1024, 64, W25X_FLAG, 75, NULL },
413 { "w25x64", 0xef3017, 0, 64 * 1024, 128, W25X_FLAG, 75, NULL },
415 /* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */
416 #define W25Q_FLAG (FLASH_FLAG_READ_WRITE | \
417 FLASH_FLAG_READ_FAST | \
418 FLASH_FLAG_READ_1_1_2 | \
419 FLASH_FLAG_READ_1_2_2 | \
420 FLASH_FLAG_READ_1_1_4 | \
421 FLASH_FLAG_READ_1_4_4 | \
422 FLASH_FLAG_WRITE_1_1_4)
423 { "w25q80", 0xef4014, 0, 64 * 1024, 16, W25Q_FLAG, 80, NULL },
424 { "w25q16", 0xef4015, 0, 64 * 1024, 32, W25Q_FLAG, 80, NULL },
425 { "w25q32", 0xef4016, 0, 64 * 1024, 64, W25Q_FLAG, 80, NULL },
426 { "w25q64", 0xef4017, 0, 64 * 1024, 128, W25Q_FLAG, 80, NULL },
429 { NULL, 0x000000, 0, 0, 0, 0, 0, NULL },
433 * FSM message sequence configurations:
435 * All configs are presented in order of preference
438 /* Default READ configurations, in order of preference */
439 static struct seq_rw_config default_read_configs[] = {
440 {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 2, 4},
441 {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 4, 0},
442 {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 4, 0},
443 {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8},
444 {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8},
445 {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0},
446 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
449 /* Default WRITE configurations */
450 static struct seq_rw_config default_write_configs[] = {
451 {FLASH_FLAG_WRITE_1_4_4, FLASH_CMD_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0},
452 {FLASH_FLAG_WRITE_1_1_4, FLASH_CMD_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0},
453 {FLASH_FLAG_WRITE_1_2_2, FLASH_CMD_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0},
454 {FLASH_FLAG_WRITE_1_1_2, FLASH_CMD_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0},
455 {FLASH_FLAG_READ_WRITE, FLASH_CMD_WRITE, 1, 1, 1, 0x00, 0, 0},
456 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
460 * [N25Qxxx] Configuration
462 #define N25Q_VCR_DUMMY_CYCLES(x) (((x) & 0xf) << 4)
463 #define N25Q_VCR_XIP_DISABLED ((uint8_t)0x1 << 3)
464 #define N25Q_VCR_WRAP_CONT 0x3
466 /* N25Q 3-byte Address READ configurations
467 * - 'FAST' variants configured for 8 dummy cycles.
469 * Note, the number of dummy cycles used for 'FAST' READ operations is
470 * configurable and would normally be tuned according to the READ command and
471 * operating frequency. However, this applies universally to all 'FAST' READ
472 * commands, including those used by the SPIBoot controller, and remains in
473 * force until the device is power-cycled. Since the SPIBoot controller is
474 * hard-wired to use 8 dummy cycles, we must configure the device to also use 8
477 static struct seq_rw_config n25q_read3_configs[] = {
478 {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 0, 8},
479 {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 0, 8},
480 {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 0, 8},
481 {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8},
482 {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8},
483 {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0},
484 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
487 /* N25Q 4-byte Address READ configurations
488 * - use special 4-byte address READ commands (reduces overheads, and
489 * reduces risk of hitting watchdog reset issues).
490 * - 'FAST' variants configured for 8 dummy cycles (see note above.)
492 static struct seq_rw_config n25q_read4_configs[] = {
493 {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8},
494 {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
495 {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8},
496 {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
497 {FLASH_FLAG_READ_FAST, FLASH_CMD_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
498 {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ4, 0, 1, 1, 0x00, 0, 0},
499 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
502 static struct stfsm_seq stfsm_seq_read; /* Dynamically populated */
503 static struct stfsm_seq stfsm_seq_write; /* Dynamically populated */
504 static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */
506 static struct stfsm_seq stfsm_seq_read_jedec = {
507 .data_size = TRANSFER_SIZE(8),
508 .seq_opc[0] = (SEQ_OPC_PADS_1 |
510 SEQ_OPC_OPCODE(FLASH_CMD_RDID)),
513 STFSM_INST_DATA_READ,
516 .seq_cfg = (SEQ_CFG_PADS_1 |
517 SEQ_CFG_READNOTWRITE |
522 static struct stfsm_seq stfsm_seq_erase_sector = {
523 /* 'addr_cfg' configured during initialisation */
525 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
526 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT),
528 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
529 SEQ_OPC_OPCODE(FLASH_CMD_SE)),
538 .seq_cfg = (SEQ_CFG_PADS_1 |
539 SEQ_CFG_READNOTWRITE |
544 static struct stfsm_seq stfsm_seq_wrvcr = {
545 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
546 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT),
547 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
548 SEQ_OPC_OPCODE(FLASH_CMD_WRVCR)),
555 .seq_cfg = (SEQ_CFG_PADS_1 |
556 SEQ_CFG_READNOTWRITE |
561 static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)
563 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
564 SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR));
565 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
566 SEQ_OPC_OPCODE(FLASH_CMD_WREN) |
569 seq->seq[0] = STFSM_INST_CMD2;
570 seq->seq[1] = STFSM_INST_CMD1;
571 seq->seq[2] = STFSM_INST_WAIT;
572 seq->seq[3] = STFSM_INST_STOP;
574 seq->seq_cfg = (SEQ_CFG_PADS_1 |
576 SEQ_CFG_READNOTWRITE |
583 static inline int stfsm_is_idle(struct stfsm *fsm)
585 return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10;
588 static inline uint32_t stfsm_fifo_available(struct stfsm *fsm)
590 return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f;
593 static void stfsm_clear_fifo(struct stfsm *fsm)
598 avail = stfsm_fifo_available(fsm);
603 readl(fsm->base + SPI_FAST_SEQ_DATA_REG);
609 static inline void stfsm_load_seq(struct stfsm *fsm,
610 const struct stfsm_seq *seq)
612 void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE;
613 const uint32_t *src = (const uint32_t *)seq;
614 int words = sizeof(*seq) / sizeof(*src);
616 BUG_ON(!stfsm_is_idle(fsm));
625 static void stfsm_wait_seq(struct stfsm *fsm)
627 unsigned long deadline;
630 deadline = jiffies + msecs_to_jiffies(STFSM_MAX_WAIT_SEQ_MS);
633 if (time_after_eq(jiffies, deadline))
636 if (stfsm_is_idle(fsm))
642 dev_err(fsm->dev, "timeout on sequence completion\n");
645 static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf,
648 uint32_t remaining = size >> 2;
652 dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size);
654 BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3));
658 avail = stfsm_fifo_available(fsm);
663 words = min(avail, remaining);
666 readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);
671 static int stfsm_write_fifo(struct stfsm *fsm,
672 const uint32_t *buf, const uint32_t size)
674 uint32_t words = size >> 2;
676 dev_dbg(fsm->dev, "writing %d bytes to FIFO\n", size);
678 BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3));
680 writesl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);
685 static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)
687 struct stfsm_seq *seq = &stfsm_seq_en_32bit_addr;
688 uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR;
690 seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
692 SEQ_OPC_OPCODE(cmd) |
695 stfsm_load_seq(fsm, seq);
702 static int stfsm_wrvcr(struct stfsm *fsm, uint8_t data)
704 struct stfsm_seq *seq = &stfsm_seq_wrvcr;
706 dev_dbg(fsm->dev, "writing VCR 0x%02x\n", data);
708 seq->status = (STA_DATA_BYTE1(data) | STA_PADS_1 | STA_CSDEASSERT);
710 stfsm_load_seq(fsm, seq);
718 * SoC reset on 'boot-from-spi' systems
720 * Certain modes of operation cause the Flash device to enter a particular state
721 * for a period of time (e.g. 'Erase Sector', 'Quad Enable', and 'Enter 32-bit
722 * Addr' commands). On boot-from-spi systems, it is important to consider what
723 * happens if a warm reset occurs during this period. The SPIBoot controller
724 * assumes that Flash device is in its default reset state, 24-bit address mode,
725 * and ready to accept commands. This can be achieved using some form of
726 * on-board logic/controller to force a device POR in response to a SoC-level
727 * reset or by making use of the device reset signal if available (limited
728 * number of devices only).
730 * Failure to take such precautions can cause problems following a warm reset.
731 * For some operations (e.g. ERASE), there is little that can be done. For
732 * other modes of operation (e.g. 32-bit addressing), options are often
733 * available that can help minimise the window in which a reset could cause a
737 static bool stfsm_can_handle_soc_reset(struct stfsm *fsm)
739 /* Reset signal is available on the board and supported by the device */
740 if (fsm->reset_signal && fsm->info->flags & FLASH_FLAG_RESET)
743 /* Board-level logic forces a power-on-reset */
747 /* Reset is not properly handled and may result in failure to reboot */
751 /* Configure 'addr_cfg' according to addressing mode */
752 static void stfsm_prepare_erasesec_seq(struct stfsm *fsm,
753 struct stfsm_seq *seq)
755 int addr1_cycles = fsm->info->flags & FLASH_FLAG_32BIT_ADDR ? 16 : 8;
757 seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(addr1_cycles) |
758 ADR_CFG_PADS_1_ADD1 |
759 ADR_CFG_CYCLES_ADD2(16) |
760 ADR_CFG_PADS_1_ADD2 |
761 ADR_CFG_CSDEASSERT_ADD2);
764 /* Search for preferred configuration based on available flags */
765 static struct seq_rw_config *
766 stfsm_search_seq_rw_configs(struct stfsm *fsm,
767 struct seq_rw_config cfgs[])
769 struct seq_rw_config *config;
770 int flags = fsm->info->flags;
772 for (config = cfgs; config->cmd != 0; config++)
773 if ((config->flags & flags) == config->flags)
779 /* Prepare a READ/WRITE sequence according to configuration parameters */
780 static void stfsm_prepare_rw_seq(struct stfsm *fsm,
781 struct stfsm_seq *seq,
782 struct seq_rw_config *cfg)
784 int addr1_cycles, addr2_cycles;
787 memset(seq, 0, sizeof(*seq));
789 /* Add READ/WRITE OPC */
790 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
792 SEQ_OPC_OPCODE(cfg->cmd));
794 /* Add WREN OPC for a WRITE sequence */
796 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
798 SEQ_OPC_OPCODE(FLASH_CMD_WREN) |
801 /* Address configuration (24 or 32-bit addresses) */
802 addr1_cycles = (fsm->info->flags & FLASH_FLAG_32BIT_ADDR) ? 16 : 8;
803 addr1_cycles /= cfg->addr_pads;
804 addr2_cycles = 16 / cfg->addr_pads;
805 seq->addr_cfg = ((addr1_cycles & 0x3f) << 0 | /* ADD1 cycles */
806 (cfg->addr_pads - 1) << 6 | /* ADD1 pads */
807 (addr2_cycles & 0x3f) << 16 | /* ADD2 cycles */
808 ((cfg->addr_pads - 1) << 22)); /* ADD2 pads */
810 /* Data/Sequence configuration */
811 seq->seq_cfg = ((cfg->data_pads - 1) << 16 |
815 seq->seq_cfg |= SEQ_CFG_READNOTWRITE;
817 /* Mode configuration (no. of pads taken from addr cfg) */
818 seq->mode = ((cfg->mode_data & 0xff) << 0 | /* data */
819 (cfg->mode_cycles & 0x3f) << 16 | /* cycles */
820 (cfg->addr_pads - 1) << 22); /* pads */
822 /* Dummy configuration (no. of pads taken from addr cfg) */
823 seq->dummy = ((cfg->dummy_cycles & 0x3f) << 16 | /* cycles */
824 (cfg->addr_pads - 1) << 22); /* pads */
827 /* Instruction sequence */
830 seq->seq[i++] = STFSM_INST_CMD2;
832 seq->seq[i++] = STFSM_INST_CMD1;
834 seq->seq[i++] = STFSM_INST_ADD1;
835 seq->seq[i++] = STFSM_INST_ADD2;
837 if (cfg->mode_cycles)
838 seq->seq[i++] = STFSM_INST_MODE;
840 if (cfg->dummy_cycles)
841 seq->seq[i++] = STFSM_INST_DUMMY;
844 cfg->write ? STFSM_INST_DATA_WRITE : STFSM_INST_DATA_READ;
845 seq->seq[i++] = STFSM_INST_STOP;
848 static int stfsm_search_prepare_rw_seq(struct stfsm *fsm,
849 struct stfsm_seq *seq,
850 struct seq_rw_config *cfgs)
852 struct seq_rw_config *config;
854 config = stfsm_search_seq_rw_configs(fsm, cfgs);
856 dev_err(fsm->dev, "failed to find suitable config\n");
860 stfsm_prepare_rw_seq(fsm, seq, config);
865 /* Prepare a READ/WRITE/ERASE 'default' sequences */
866 static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm)
868 uint32_t flags = fsm->info->flags;
871 /* Configure 'READ' sequence */
872 ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read,
873 default_read_configs);
876 "failed to prep READ sequence with flags [0x%08x]\n",
881 /* Configure 'WRITE' sequence */
882 ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write,
883 default_write_configs);
886 "failed to prep WRITE sequence with flags [0x%08x]\n",
891 /* Configure 'ERASE_SECTOR' sequence */
892 stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector);
897 static int stfsm_n25q_config(struct stfsm *fsm)
899 uint32_t flags = fsm->info->flags;
904 /* Configure 'READ' sequence */
905 if (flags & FLASH_FLAG_32BIT_ADDR)
906 ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read,
909 ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read,
913 "failed to prepare READ sequence with flags [0x%08x]\n",
918 /* Configure 'WRITE' sequence (default configs) */
919 ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write,
920 default_write_configs);
923 "preparing WRITE sequence using flags [0x%08x] failed\n",
928 /* * Configure 'ERASE_SECTOR' sequence */
929 stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector);
931 /* Configure 32-bit address support */
932 if (flags & FLASH_FLAG_32BIT_ADDR) {
933 stfsm_n25q_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr);
935 soc_reset = stfsm_can_handle_soc_reset(fsm);
936 if (soc_reset || !fsm->booted_from_spi) {
938 * If we can handle SoC resets, we enable 32-bit
939 * address mode pervasively
941 stfsm_enter_32bit_addr(fsm, 1);
944 * If not, enable/disable for WRITE and ERASE
945 * operations (READ uses special commands)
947 fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR |
948 CFG_ERASESEC_TOGGLE_32BIT_ADDR);
953 * Configure device to use 8 dummy cycles
955 vcr = (N25Q_VCR_DUMMY_CYCLES(8) | N25Q_VCR_XIP_DISABLED |
957 stfsm_wrvcr(fsm, vcr);
962 static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size,
965 struct stfsm_seq *seq = &stfsm_seq_read;
972 uint32_t page_buf[FLASH_PAGESIZE_32];
975 dev_dbg(fsm->dev, "reading %d bytes from 0x%08x\n", size, offset);
977 /* Enter 32-bit address mode, if required */
978 if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR)
979 stfsm_enter_32bit_addr(fsm, 1);
981 /* Must read in multiples of 32 cycles (or 32*pads/8 Bytes) */
982 data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1;
983 read_mask = (data_pads << 2) - 1;
985 /* Handle non-aligned buf */
986 p = ((uint32_t)buf & 0x3) ? (uint8_t *)page_buf : buf;
988 /* Handle non-aligned size */
989 size_ub = (size + read_mask) & ~read_mask;
990 size_lb = size & ~read_mask;
991 size_mop = size & read_mask;
993 seq->data_size = TRANSFER_SIZE(size_ub);
994 seq->addr1 = (offset >> 16) & 0xffff;
995 seq->addr2 = offset & 0xffff;
997 stfsm_load_seq(fsm, seq);
1000 stfsm_read_fifo(fsm, (uint32_t *)p, size_lb);
1003 stfsm_read_fifo(fsm, tmp, read_mask + 1);
1004 memcpy(p + size_lb, &tmp, size_mop);
1007 /* Handle non-aligned buf */
1008 if ((uint32_t)buf & 0x3)
1009 memcpy(buf, page_buf, size);
1011 /* Wait for sequence to finish */
1012 stfsm_wait_seq(fsm);
1014 stfsm_clear_fifo(fsm);
1016 /* Exit 32-bit address mode, if required */
1017 if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR)
1018 stfsm_enter_32bit_addr(fsm, 0);
1024 * Read an address range from the flash chip. The address range
1025 * may be any size provided it is within the physical boundaries.
1027 static int stfsm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
1028 size_t *retlen, u_char *buf)
1030 struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);
1033 dev_dbg(fsm->dev, "%s from 0x%08x, len %zd\n",
1034 __func__, (u32)from, len);
1036 mutex_lock(&fsm->lock);
1039 bytes = min_t(size_t, len, FLASH_PAGESIZE);
1041 stfsm_read(fsm, buf, bytes, from);
1050 mutex_unlock(&fsm->lock);
1055 static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec)
1057 const struct stfsm_seq *seq = &stfsm_seq_read_jedec;
1060 stfsm_load_seq(fsm, seq);
1062 stfsm_read_fifo(fsm, tmp, 8);
1064 memcpy(jedec, tmp, 5);
1066 stfsm_wait_seq(fsm);
1069 static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm)
1071 struct flash_info *info;
1076 stfsm_read_jedec(fsm, id);
1078 jedec = id[0] << 16 | id[1] << 8 | id[2];
1080 * JEDEC also defines an optional "extended device information"
1081 * string for after vendor-specific data, after the three bytes
1082 * we use here. Supporting some chips might require using it.
1084 ext_jedec = id[3] << 8 | id[4];
1086 dev_dbg(fsm->dev, "JEDEC = 0x%08x [%02x %02x %02x %02x %02x]\n",
1087 jedec, id[0], id[1], id[2], id[3], id[4]);
1089 for (info = flash_types; info->name; info++) {
1090 if (info->jedec_id == jedec) {
1091 if (info->ext_id && info->ext_id != ext_jedec)
1096 dev_err(fsm->dev, "Unrecognized JEDEC id %06x\n", jedec);
1101 static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)
1103 int ret, timeout = 10;
1105 /* Wait for controller to accept mode change */
1107 ret = readl(fsm->base + SPI_STA_MODE_CHANGE);
1116 writel(mode, fsm->base + SPI_MODESELECT);
1121 static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq)
1126 /* TODO: Make this dynamic */
1127 emi_freq = STFSM_DEFAULT_EMI_FREQ;
1130 * Calculate clk_div - values between 2 and 128
1131 * Multiple of 2, rounded up
1133 clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq);
1136 else if (clk_div > 128)
1140 * Determine a suitable delay for the IP to complete a change of
1141 * direction of the FIFO. The required delay is related to the clock
1142 * divider used. The following heuristics are based on empirical tests,
1143 * using a 100MHz EMI clock.
1146 fsm->fifo_dir_delay = 0;
1147 else if (clk_div <= 10)
1148 fsm->fifo_dir_delay = 1;
1150 fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10);
1152 dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n",
1153 emi_freq, spi_freq, clk_div);
1155 writel(clk_div, fsm->base + SPI_CLOCKDIV);
1158 static int stfsm_init(struct stfsm *fsm)
1162 /* Perform a soft reset of the FSM controller */
1163 writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG);
1165 writel(0, fsm->base + SPI_FAST_SEQ_CFG);
1167 /* Set clock to 'safe' frequency initially */
1168 stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ);
1171 ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM);
1175 /* Set timing parameters */
1176 writel(SPI_CFG_DEVICE_ST |
1177 SPI_CFG_DEFAULT_MIN_CS_HIGH |
1178 SPI_CFG_DEFAULT_CS_SETUPHOLD |
1179 SPI_CFG_DEFAULT_DATA_HOLD,
1180 fsm->base + SPI_CONFIGDATA);
1181 writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG);
1183 /* Clear FIFO, just in case */
1184 stfsm_clear_fifo(fsm);
1189 static void stfsm_fetch_platform_configs(struct platform_device *pdev)
1191 struct stfsm *fsm = platform_get_drvdata(pdev);
1192 struct device_node *np = pdev->dev.of_node;
1193 struct regmap *regmap;
1194 uint32_t boot_device_reg;
1195 uint32_t boot_device_spi;
1196 uint32_t boot_device; /* Value we read from *boot_device_reg */
1199 /* Booting from SPI NOR Flash is the default */
1200 fsm->booted_from_spi = true;
1202 regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1204 goto boot_device_fail;
1206 fsm->reset_signal = of_property_read_bool(np, "st,reset-signal");
1208 fsm->reset_por = of_property_read_bool(np, "st,reset-por");
1210 /* Where in the syscon the boot device information lives */
1211 ret = of_property_read_u32(np, "st,boot-device-reg", &boot_device_reg);
1213 goto boot_device_fail;
1215 /* Boot device value when booted from SPI NOR */
1216 ret = of_property_read_u32(np, "st,boot-device-spi", &boot_device_spi);
1218 goto boot_device_fail;
1220 ret = regmap_read(regmap, boot_device_reg, &boot_device);
1222 goto boot_device_fail;
1224 if (boot_device != boot_device_spi)
1225 fsm->booted_from_spi = false;
1230 dev_warn(&pdev->dev,
1231 "failed to fetch boot device, assuming boot from SPI\n");
1234 static int stfsm_probe(struct platform_device *pdev)
1236 struct device_node *np = pdev->dev.of_node;
1237 struct flash_info *info;
1238 struct resource *res;
1243 dev_err(&pdev->dev, "No DT found\n");
1247 fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL);
1251 fsm->dev = &pdev->dev;
1253 platform_set_drvdata(pdev, fsm);
1255 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1257 dev_err(&pdev->dev, "Resource not found\n");
1261 fsm->base = devm_ioremap_resource(&pdev->dev, res);
1262 if (IS_ERR(fsm->base)) {
1264 "Failed to reserve memory region %pR\n", res);
1265 return PTR_ERR(fsm->base);
1268 mutex_init(&fsm->lock);
1270 ret = stfsm_init(fsm);
1272 dev_err(&pdev->dev, "Failed to initialise FSM Controller\n");
1276 stfsm_fetch_platform_configs(pdev);
1278 /* Detect SPI FLASH device */
1279 info = stfsm_jedec_probe(fsm);
1284 /* Use device size to determine address width */
1285 if (info->sector_size * info->n_sectors > 0x1000000)
1286 info->flags |= FLASH_FLAG_32BIT_ADDR;
1289 * Configure READ/WRITE/ERASE sequences according to platform and
1293 ret = info->config(fsm);
1297 ret = stfsm_prepare_rwe_seqs_default(fsm);
1302 fsm->mtd.dev.parent = &pdev->dev;
1303 fsm->mtd.type = MTD_NORFLASH;
1304 fsm->mtd.writesize = 4;
1305 fsm->mtd.writebufsize = fsm->mtd.writesize;
1306 fsm->mtd.flags = MTD_CAP_NORFLASH;
1307 fsm->mtd.size = info->sector_size * info->n_sectors;
1308 fsm->mtd.erasesize = info->sector_size;
1310 fsm->mtd._read = stfsm_mtd_read;
1313 "Found serial flash device: %s\n"
1314 " size = %llx (%lldMiB) erasesize = 0x%08x (%uKiB)\n",
1316 (long long)fsm->mtd.size, (long long)(fsm->mtd.size >> 20),
1317 fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10));
1319 return mtd_device_parse_register(&fsm->mtd, NULL, NULL, NULL, 0);
1322 static int stfsm_remove(struct platform_device *pdev)
1324 struct stfsm *fsm = platform_get_drvdata(pdev);
1327 err = mtd_device_unregister(&fsm->mtd);
1334 static struct of_device_id stfsm_match[] = {
1335 { .compatible = "st,spi-fsm", },
1338 MODULE_DEVICE_TABLE(of, stfsm_match);
1340 static struct platform_driver stfsm_driver = {
1341 .probe = stfsm_probe,
1342 .remove = stfsm_remove,
1344 .name = "st-spi-fsm",
1345 .owner = THIS_MODULE,
1346 .of_match_table = stfsm_match,
1349 module_platform_driver(stfsm_driver);
1351 MODULE_AUTHOR("Angus Clark <angus.clark@st.com>");
1352 MODULE_DESCRIPTION("ST SPI FSM driver");
1353 MODULE_LICENSE("GPL");