1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (C) 2017-2018 Socionext Inc.
4 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 #include <linux/bitfield.h>
7 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/mfd/tmio.h>
12 #include <linux/mmc/host.h>
13 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
22 #define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16)
23 #define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10)
24 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop
25 #define UNIPHIER_SD_CC_EXT_MODE 0x1b0
26 #define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1)
27 #define UNIPHIER_SD_HOST_MODE 0x1c8
28 #define UNIPHIER_SD_VOLT 0x1e4
29 #define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0)
30 #define UNIPHIER_SD_VOLT_OFF 0
31 #define UNIPHIER_SD_VOLT_330 1 // 3.3V signal
32 #define UNIPHIER_SD_VOLT_180 2 // 1.8V signal
33 #define UNIPHIER_SD_DMA_MODE 0x410
34 #define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16)
35 #define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0
36 #define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1
37 #define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4)
38 #define UNIPHIER_SD_DMA_MODE_WIDTH_8 0
39 #define UNIPHIER_SD_DMA_MODE_WIDTH_16 1
40 #define UNIPHIER_SD_DMA_MODE_WIDTH_32 2
41 #define UNIPHIER_SD_DMA_MODE_WIDTH_64 3
42 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed
43 #define UNIPHIER_SD_DMA_CTL 0x414
44 #define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared)
45 #define UNIPHIER_SD_DMA_RST 0x418
46 #define UNIPHIER_SD_DMA_RST_CH1 BIT(9)
47 #define UNIPHIER_SD_DMA_RST_CH0 BIT(8)
48 #define UNIPHIER_SD_DMA_ADDR_L 0x440
49 #define UNIPHIER_SD_DMA_ADDR_H 0x444
52 * IP is extended to support various features: built-in DMA engine,
53 * 1/1024 divisor, etc.
55 #define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0)
56 /* RX channel of the built-in DMA controller is broken (Pro5) */
57 #define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1)
59 struct uniphier_sd_priv {
60 struct tmio_mmc_data tmio_data;
61 struct pinctrl *pinctrl;
62 struct pinctrl_state *pinstate_uhs;
64 struct reset_control *rst;
65 struct reset_control *rst_br;
66 struct reset_control *rst_hw;
67 struct dma_chan *chan;
68 enum dma_data_direction dma_dir;
69 unsigned long clk_rate;
73 static void *uniphier_sd_priv(struct tmio_mmc_host *host)
75 return container_of(host->pdata, struct uniphier_sd_priv, tmio_data);
78 static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable)
80 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
83 /* external DMA engine */
84 static void uniphier_sd_external_dma_issue(struct tasklet_struct *t)
86 struct tmio_mmc_host *host = from_tasklet(host, t, dma_issue);
87 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
89 uniphier_sd_dma_endisable(host, 1);
90 dma_async_issue_pending(priv->chan);
93 static void uniphier_sd_external_dma_callback(void *param,
94 const struct dmaengine_result *result)
96 struct tmio_mmc_host *host = param;
97 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
100 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
103 spin_lock_irqsave(&host->lock, flags);
105 if (result->result == DMA_TRANS_NOERROR) {
107 * When the external DMA engine is enabled, strangely enough,
108 * the DATAEND flag can be asserted even if the DMA engine has
109 * not been kicked yet. Enable the TMIO_STAT_DATAEND irq only
110 * after we make sure the DMA engine finishes the transfer,
111 * hence, in this callback.
113 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
115 host->data->error = -ETIMEDOUT;
116 tmio_mmc_do_data_irq(host);
119 spin_unlock_irqrestore(&host->lock, flags);
122 static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host,
123 struct mmc_data *data)
125 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
126 enum dma_transfer_direction dma_tx_dir;
127 struct dma_async_tx_descriptor *desc;
134 if (data->flags & MMC_DATA_READ) {
135 priv->dma_dir = DMA_FROM_DEVICE;
136 dma_tx_dir = DMA_DEV_TO_MEM;
138 priv->dma_dir = DMA_TO_DEVICE;
139 dma_tx_dir = DMA_MEM_TO_DEV;
142 sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
147 desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len,
148 dma_tx_dir, DMA_CTRL_ACK);
152 desc->callback_result = uniphier_sd_external_dma_callback;
153 desc->callback_param = host;
155 cookie = dmaengine_submit(desc);
164 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
167 uniphier_sd_dma_endisable(host, 0);
170 static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host,
175 static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host,
176 struct tmio_mmc_data *pdata)
178 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
179 struct dma_chan *chan;
181 chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx");
183 dev_warn(mmc_dev(host->mmc),
184 "failed to request DMA channel. falling back to PIO\n");
185 return; /* just use PIO even for -EPROBE_DEFER */
188 /* this driver uses a single channel for both RX an TX */
190 host->chan_rx = chan;
191 host->chan_tx = chan;
193 tasklet_setup(&host->dma_issue, uniphier_sd_external_dma_issue);
196 static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host)
198 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
201 dma_release_channel(priv->chan);
204 static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host)
206 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
208 uniphier_sd_dma_endisable(host, 0);
211 dmaengine_terminate_sync(priv->chan);
214 static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host)
216 uniphier_sd_dma_endisable(host, 0);
218 tmio_mmc_do_data_irq(host);
221 static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = {
222 .start = uniphier_sd_external_dma_start,
223 .enable = uniphier_sd_external_dma_enable,
224 .request = uniphier_sd_external_dma_request,
225 .release = uniphier_sd_external_dma_release,
226 .abort = uniphier_sd_external_dma_abort,
227 .dataend = uniphier_sd_external_dma_dataend,
230 static void uniphier_sd_internal_dma_issue(struct tasklet_struct *t)
232 struct tmio_mmc_host *host = from_tasklet(host, t, dma_issue);
235 spin_lock_irqsave(&host->lock, flags);
236 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
237 spin_unlock_irqrestore(&host->lock, flags);
239 uniphier_sd_dma_endisable(host, 1);
240 writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL);
243 static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host,
244 struct mmc_data *data)
246 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
247 struct scatterlist *sg = host->sg_ptr;
249 unsigned int dma_mode_dir;
253 if ((data->flags & MMC_DATA_READ) && !host->chan_rx)
256 if (WARN_ON(host->sg_len != 1))
259 if (!IS_ALIGNED(sg->offset, 8))
262 if (data->flags & MMC_DATA_READ) {
263 priv->dma_dir = DMA_FROM_DEVICE;
264 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV;
266 priv->dma_dir = DMA_TO_DEVICE;
267 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV;
270 sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir);
274 dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir);
275 dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK,
276 UNIPHIER_SD_DMA_MODE_WIDTH_64);
277 dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
279 writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE);
281 dma_addr = sg_dma_address(data->sg);
282 writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L);
283 writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H);
289 uniphier_sd_dma_endisable(host, 0);
292 static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host,
297 static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host,
298 struct tmio_mmc_data *pdata)
300 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
303 * Due to a hardware bug, Pro5 cannot use DMA for RX.
304 * We can still use DMA for TX, but PIO for RX.
306 if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX))
307 host->chan_rx = (void *)0xdeadbeaf;
309 host->chan_tx = (void *)0xdeadbeaf;
311 tasklet_setup(&host->dma_issue, uniphier_sd_internal_dma_issue);
314 static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host)
316 /* Each value is set to zero to assume "disabling" each DMA */
317 host->chan_rx = NULL;
318 host->chan_tx = NULL;
321 static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host)
325 uniphier_sd_dma_endisable(host, 0);
327 tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST);
328 tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0);
329 writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
331 tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0;
332 writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
335 static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host)
337 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
339 uniphier_sd_dma_endisable(host, 0);
340 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir);
342 tmio_mmc_do_data_irq(host);
345 static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = {
346 .start = uniphier_sd_internal_dma_start,
347 .enable = uniphier_sd_internal_dma_enable,
348 .request = uniphier_sd_internal_dma_request,
349 .release = uniphier_sd_internal_dma_release,
350 .abort = uniphier_sd_internal_dma_abort,
351 .dataend = uniphier_sd_internal_dma_dataend,
354 static int uniphier_sd_clk_enable(struct tmio_mmc_host *host)
356 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
357 struct mmc_host *mmc = host->mmc;
360 ret = clk_prepare_enable(priv->clk);
364 ret = clk_set_rate(priv->clk, ULONG_MAX);
368 priv->clk_rate = clk_get_rate(priv->clk);
370 /* If max-frequency property is set, use it. */
372 mmc->f_max = priv->clk_rate;
375 * 1/512 is the finest divisor in the original IP. Newer versions
376 * also supports 1/1024 divisor. (UniPhier-specific extension)
378 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
379 mmc->f_min = priv->clk_rate / 1024;
381 mmc->f_min = priv->clk_rate / 512;
383 ret = reset_control_deassert(priv->rst);
387 ret = reset_control_deassert(priv->rst_br);
394 reset_control_assert(priv->rst);
396 clk_disable_unprepare(priv->clk);
401 static void uniphier_sd_clk_disable(struct tmio_mmc_host *host)
403 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
405 reset_control_assert(priv->rst_br);
406 reset_control_assert(priv->rst);
407 clk_disable_unprepare(priv->clk);
410 static void uniphier_sd_hw_reset(struct mmc_host *mmc)
412 struct tmio_mmc_host *host = mmc_priv(mmc);
413 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
415 reset_control_assert(priv->rst_hw);
416 /* For eMMC, minimum is 1us but give it 9us for good measure */
418 reset_control_deassert(priv->rst_hw);
419 /* For eMMC, minimum is 200us but give it 300us for good measure */
420 usleep_range(300, 1000);
423 static void uniphier_sd_set_clock(struct tmio_mmc_host *host,
426 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
427 unsigned long divisor;
430 tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
432 /* stop the clock before changing its rate to avoid a glitch signal */
433 tmp &= ~CLK_CTL_SCLKEN;
434 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
439 tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024;
440 tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1;
441 tmp &= ~CLK_CTL_DIV_MASK;
443 divisor = priv->clk_rate / clock;
446 * In the original IP, bit[7:0] represents the divisor.
447 * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2
449 * The IP does not define a way to achieve 1/1. For UniPhier variants,
450 * bit10 is used for 1/1. Newer versions of UniPhier variants use
454 tmp |= UNIPHIER_SD_CLK_CTL_DIV1;
455 else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512)
456 tmp |= UNIPHIER_SD_CLK_CTL_DIV1024;
458 tmp |= roundup_pow_of_two(divisor) >> 2;
460 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
462 tmp |= CLK_CTL_SCLKEN;
463 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
466 static void uniphier_sd_host_init(struct tmio_mmc_host *host)
468 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
472 * Connected to 32bit AXI.
473 * This register holds settings for SoC-specific internal bus
474 * connection. What is worse, the register spec was changed,
475 * breaking the backward compatibility. Write an appropriate
476 * value depending on a flag associated with a compatible string.
478 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
483 writel(val, host->ctl + UNIPHIER_SD_HOST_MODE);
487 * If supported, the controller can automatically
488 * enable/disable the clock line to the card.
490 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
491 val |= UNIPHIER_SD_CLKCTL_OFFEN;
493 writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
496 static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc,
499 struct tmio_mmc_host *host = mmc_priv(mmc);
500 struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
501 struct pinctrl_state *pinstate = NULL;
504 switch (ios->signal_voltage) {
505 case MMC_SIGNAL_VOLTAGE_330:
506 val = UNIPHIER_SD_VOLT_330;
508 case MMC_SIGNAL_VOLTAGE_180:
509 val = UNIPHIER_SD_VOLT_180;
510 pinstate = priv->pinstate_uhs;
516 tmp = readl(host->ctl + UNIPHIER_SD_VOLT);
517 tmp &= ~UNIPHIER_SD_VOLT_MASK;
518 tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val);
519 writel(tmp, host->ctl + UNIPHIER_SD_VOLT);
522 pinctrl_select_state(priv->pinctrl, pinstate);
524 pinctrl_select_default_state(mmc_dev(mmc));
529 static int uniphier_sd_uhs_init(struct tmio_mmc_host *host,
530 struct uniphier_sd_priv *priv)
532 priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc));
533 if (IS_ERR(priv->pinctrl))
534 return PTR_ERR(priv->pinctrl);
536 priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs");
537 if (IS_ERR(priv->pinstate_uhs))
538 return PTR_ERR(priv->pinstate_uhs);
540 host->ops.start_signal_voltage_switch =
541 uniphier_sd_start_signal_voltage_switch;
546 static int uniphier_sd_probe(struct platform_device *pdev)
548 struct device *dev = &pdev->dev;
549 struct uniphier_sd_priv *priv;
550 struct tmio_mmc_data *tmio_data;
551 struct tmio_mmc_host *host;
554 irq = platform_get_irq(pdev, 0);
558 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
562 priv->caps = (unsigned long)of_device_get_match_data(dev);
564 priv->clk = devm_clk_get(dev, NULL);
565 if (IS_ERR(priv->clk)) {
566 dev_err(dev, "failed to get clock\n");
567 return PTR_ERR(priv->clk);
570 priv->rst = devm_reset_control_get_shared(dev, "host");
571 if (IS_ERR(priv->rst)) {
572 dev_err(dev, "failed to get host reset\n");
573 return PTR_ERR(priv->rst);
576 /* old version has one more reset */
577 if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) {
578 priv->rst_br = devm_reset_control_get_shared(dev, "bridge");
579 if (IS_ERR(priv->rst_br)) {
580 dev_err(dev, "failed to get bridge reset\n");
581 return PTR_ERR(priv->rst_br);
585 tmio_data = &priv->tmio_data;
586 tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT;
587 tmio_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
589 host = tmio_mmc_host_alloc(pdev, tmio_data);
591 return PTR_ERR(host);
593 if (host->mmc->caps & MMC_CAP_HW_RESET) {
594 priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw");
595 if (IS_ERR(priv->rst_hw)) {
596 dev_err(dev, "failed to get hw reset\n");
597 ret = PTR_ERR(priv->rst_hw);
600 host->ops.card_hw_reset = uniphier_sd_hw_reset;
603 if (host->mmc->caps & MMC_CAP_UHS) {
604 ret = uniphier_sd_uhs_init(host, priv);
607 "failed to setup UHS (error %d). Disabling UHS.",
609 host->mmc->caps &= ~MMC_CAP_UHS;
613 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
614 host->dma_ops = &uniphier_sd_internal_dma_ops;
616 host->dma_ops = &uniphier_sd_external_dma_ops;
619 host->clk_enable = uniphier_sd_clk_enable;
620 host->clk_disable = uniphier_sd_clk_disable;
621 host->set_clock = uniphier_sd_set_clock;
623 ret = uniphier_sd_clk_enable(host);
627 uniphier_sd_host_init(host);
629 tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34;
630 if (host->mmc->caps & MMC_CAP_UHS)
631 tmio_data->ocr_mask |= MMC_VDD_165_195;
633 tmio_data->max_segs = 1;
634 tmio_data->max_blk_count = U16_MAX;
636 ret = tmio_mmc_host_probe(host);
640 ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED,
641 dev_name(dev), host);
648 tmio_mmc_host_remove(host);
650 uniphier_sd_clk_disable(host);
652 tmio_mmc_host_free(host);
657 static int uniphier_sd_remove(struct platform_device *pdev)
659 struct tmio_mmc_host *host = platform_get_drvdata(pdev);
661 tmio_mmc_host_remove(host);
662 uniphier_sd_clk_disable(host);
663 tmio_mmc_host_free(host);
668 static const struct of_device_id uniphier_sd_match[] = {
670 .compatible = "socionext,uniphier-sd-v2.91",
673 .compatible = "socionext,uniphier-sd-v3.1",
674 .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP |
675 UNIPHIER_SD_CAP_BROKEN_DMA_RX),
678 .compatible = "socionext,uniphier-sd-v3.1.1",
679 .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP,
683 MODULE_DEVICE_TABLE(of, uniphier_sd_match);
685 static struct platform_driver uniphier_sd_driver = {
686 .probe = uniphier_sd_probe,
687 .remove = uniphier_sd_remove,
689 .name = "uniphier-sd",
690 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
691 .of_match_table = uniphier_sd_match,
694 module_platform_driver(uniphier_sd_driver);
696 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
697 MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver");
698 MODULE_LICENSE("GPL v2");