drivers/mmc/host/sunxi-mmc.c

   1 /*
   2  * Driver for sunxi SD/MMC host controllers
   3  * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
   4  * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
   5  * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
   6  * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
   7  * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
   8  * (C) Copyright 2017 Sootech SA
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/io.h>
  19 #include <linux/device.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23
  24 #include <linux/clk.h>
  25 #include <linux/clk/sunxi-ng.h>
  26 #include <linux/gpio.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/slab.h>
  32 #include <linux/reset.h>
  33 #include <linux/regulator/consumer.h>
  34
  35 #include <linux/of_address.h>
  36 #include <linux/of_gpio.h>
  37 #include <linux/of_platform.h>
  38
  39 #include <linux/mmc/host.h>
  40 #include <linux/mmc/sd.h>
  41 #include <linux/mmc/sdio.h>
  42 #include <linux/mmc/mmc.h>
  43 #include <linux/mmc/core.h>
  44 #include <linux/mmc/card.h>
  45 #include <linux/mmc/slot-gpio.h>
  46
  47 /* register offset definitions */
  48 #define SDXC_REG_GCTRL  (0x00) /* SMC Global Control Register */
  49 #define SDXC_REG_CLKCR  (0x04) /* SMC Clock Control Register */
  50 #define SDXC_REG_TMOUT  (0x08) /* SMC Time Out Register */
  51 #define SDXC_REG_WIDTH  (0x0C) /* SMC Bus Width Register */
  52 #define SDXC_REG_BLKSZ  (0x10) /* SMC Block Size Register */
  53 #define SDXC_REG_BCNTR  (0x14) /* SMC Byte Count Register */
  54 #define SDXC_REG_CMDR   (0x18) /* SMC Command Register */
  55 #define SDXC_REG_CARG   (0x1C) /* SMC Argument Register */
  56 #define SDXC_REG_RESP0  (0x20) /* SMC Response Register 0 */
  57 #define SDXC_REG_RESP1  (0x24) /* SMC Response Register 1 */
  58 #define SDXC_REG_RESP2  (0x28) /* SMC Response Register 2 */
  59 #define SDXC_REG_RESP3  (0x2C) /* SMC Response Register 3 */
  60 #define SDXC_REG_IMASK  (0x30) /* SMC Interrupt Mask Register */
  61 #define SDXC_REG_MISTA  (0x34) /* SMC Masked Interrupt Status Register */
  62 #define SDXC_REG_RINTR  (0x38) /* SMC Raw Interrupt Status Register */
  63 #define SDXC_REG_STAS   (0x3C) /* SMC Status Register */
  64 #define SDXC_REG_FTRGL  (0x40) /* SMC FIFO Threshold Watermark Registe */
  65 #define SDXC_REG_FUNS   (0x44) /* SMC Function Select Register */
  66 #define SDXC_REG_CBCR   (0x48) /* SMC CIU Byte Count Register */
  67 #define SDXC_REG_BBCR   (0x4C) /* SMC BIU Byte Count Register */
  68 #define SDXC_REG_DBGC   (0x50) /* SMC Debug Enable Register */
  69 #define SDXC_REG_HWRST  (0x78) /* SMC Card Hardware Reset for Register */
  70 #define SDXC_REG_DMAC   (0x80) /* SMC IDMAC Control Register */
  71 #define SDXC_REG_DLBA   (0x84) /* SMC IDMAC Descriptor List Base Addre */
  72 #define SDXC_REG_IDST   (0x88) /* SMC IDMAC Status Register */
  73 #define SDXC_REG_IDIE   (0x8C) /* SMC IDMAC Interrupt Enable Register */
  74 #define SDXC_REG_CHDA   (0x90)
  75 #define SDXC_REG_CBDA   (0x94)
  76
  77 /* New registers introduced in A64 */
  78 #define SDXC_REG_A12A           0x058 /* SMC Auto Command 12 Register */
  79 #define SDXC_REG_SD_NTSR        0x05C /* SMC New Timing Set Register */
  80 #define SDXC_REG_DRV_DL         0x140 /* Drive Delay Control Register */
  81 #define SDXC_REG_SAMP_DL_REG    0x144 /* SMC sample delay control */
  82 #define SDXC_REG_DS_DL_REG      0x148 /* SMC data strobe delay control */
  83
  84 #define mmc_readl(host, reg) \
  85         readl((host)->reg_base + SDXC_##reg)
  86 #define mmc_writel(host, reg, value) \
  87         writel((value), (host)->reg_base + SDXC_##reg)
  88
  89 /* global control register bits */
  90 #define SDXC_SOFT_RESET                 BIT(0)
  91 #define SDXC_FIFO_RESET                 BIT(1)
  92 #define SDXC_DMA_RESET                  BIT(2)
  93 #define SDXC_INTERRUPT_ENABLE_BIT       BIT(4)
  94 #define SDXC_DMA_ENABLE_BIT             BIT(5)
  95 #define SDXC_DEBOUNCE_ENABLE_BIT        BIT(8)
  96 #define SDXC_POSEDGE_LATCH_DATA         BIT(9)
  97 #define SDXC_DDR_MODE                   BIT(10)
  98 #define SDXC_MEMORY_ACCESS_DONE         BIT(29)
  99 #define SDXC_ACCESS_DONE_DIRECT         BIT(30)
 100 #define SDXC_ACCESS_BY_AHB              BIT(31)
 101 #define SDXC_ACCESS_BY_DMA              (0 << 31)
 102 #define SDXC_HARDWARE_RESET \
 103         (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
 104
 105 /* clock control bits */
 106 #define SDXC_MASK_DATA0                 BIT(31)
 107 #define SDXC_CARD_CLOCK_ON              BIT(16)
 108 #define SDXC_LOW_POWER_ON               BIT(17)
 109
 110 /* bus width */
 111 #define SDXC_WIDTH1                     0
 112 #define SDXC_WIDTH4                     1
 113 #define SDXC_WIDTH8                     2
 114
 115 /* smc command bits */
 116 #define SDXC_RESP_EXPIRE                BIT(6)
 117 #define SDXC_LONG_RESPONSE              BIT(7)
 118 #define SDXC_CHECK_RESPONSE_CRC         BIT(8)
 119 #define SDXC_DATA_EXPIRE                BIT(9)
 120 #define SDXC_WRITE                      BIT(10)
 121 #define SDXC_SEQUENCE_MODE              BIT(11)
 122 #define SDXC_SEND_AUTO_STOP             BIT(12)
 123 #define SDXC_WAIT_PRE_OVER              BIT(13)
 124 #define SDXC_STOP_ABORT_CMD             BIT(14)
 125 #define SDXC_SEND_INIT_SEQUENCE         BIT(15)
 126 #define SDXC_UPCLK_ONLY                 BIT(21)
 127 #define SDXC_READ_CEATA_DEV             BIT(22)
 128 #define SDXC_CCS_EXPIRE                 BIT(23)
 129 #define SDXC_ENABLE_BIT_BOOT            BIT(24)
 130 #define SDXC_ALT_BOOT_OPTIONS           BIT(25)
 131 #define SDXC_BOOT_ACK_EXPIRE            BIT(26)
 132 #define SDXC_BOOT_ABORT                 BIT(27)
 133 #define SDXC_VOLTAGE_SWITCH             BIT(28)
 134 #define SDXC_USE_HOLD_REGISTER          BIT(29)
 135 #define SDXC_START                      BIT(31)
 136
 137 /* interrupt bits */
 138 #define SDXC_RESP_ERROR                 BIT(1)
 139 #define SDXC_COMMAND_DONE               BIT(2)
 140 #define SDXC_DATA_OVER                  BIT(3)
 141 #define SDXC_TX_DATA_REQUEST            BIT(4)
 142 #define SDXC_RX_DATA_REQUEST            BIT(5)
 143 #define SDXC_RESP_CRC_ERROR             BIT(6)
 144 #define SDXC_DATA_CRC_ERROR             BIT(7)
 145 #define SDXC_RESP_TIMEOUT               BIT(8)
 146 #define SDXC_DATA_TIMEOUT               BIT(9)
 147 #define SDXC_VOLTAGE_CHANGE_DONE        BIT(10)
 148 #define SDXC_FIFO_RUN_ERROR             BIT(11)
 149 #define SDXC_HARD_WARE_LOCKED           BIT(12)
 150 #define SDXC_START_BIT_ERROR            BIT(13)
 151 #define SDXC_AUTO_COMMAND_DONE          BIT(14)
 152 #define SDXC_END_BIT_ERROR              BIT(15)
 153 #define SDXC_SDIO_INTERRUPT             BIT(16)
 154 #define SDXC_CARD_INSERT                BIT(30)
 155 #define SDXC_CARD_REMOVE                BIT(31)
 156 #define SDXC_INTERRUPT_ERROR_BIT \
 157         (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
 158          SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
 159          SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
 160 #define SDXC_INTERRUPT_DONE_BIT \
 161         (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
 162          SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
 163
 164 /* status */
 165 #define SDXC_RXWL_FLAG                  BIT(0)
 166 #define SDXC_TXWL_FLAG                  BIT(1)
 167 #define SDXC_FIFO_EMPTY                 BIT(2)
 168 #define SDXC_FIFO_FULL                  BIT(3)
 169 #define SDXC_CARD_PRESENT               BIT(8)
 170 #define SDXC_CARD_DATA_BUSY             BIT(9)
 171 #define SDXC_DATA_FSM_BUSY              BIT(10)
 172 #define SDXC_DMA_REQUEST                BIT(31)
 173 #define SDXC_FIFO_SIZE                  16
 174
 175 /* Function select */
 176 #define SDXC_CEATA_ON                   (0xceaa << 16)
 177 #define SDXC_SEND_IRQ_RESPONSE          BIT(0)
 178 #define SDXC_SDIO_READ_WAIT             BIT(1)
 179 #define SDXC_ABORT_READ_DATA            BIT(2)
 180 #define SDXC_SEND_CCSD                  BIT(8)
 181 #define SDXC_SEND_AUTO_STOPCCSD         BIT(9)
 182 #define SDXC_CEATA_DEV_IRQ_ENABLE       BIT(10)
 183
 184 /* IDMA controller bus mod bit field */
 185 #define SDXC_IDMAC_SOFT_RESET           BIT(0)
 186 #define SDXC_IDMAC_FIX_BURST            BIT(1)
 187 #define SDXC_IDMAC_IDMA_ON              BIT(7)
 188 #define SDXC_IDMAC_REFETCH_DES          BIT(31)
 189
 190 /* IDMA status bit field */
 191 #define SDXC_IDMAC_TRANSMIT_INTERRUPT           BIT(0)
 192 #define SDXC_IDMAC_RECEIVE_INTERRUPT            BIT(1)
 193 #define SDXC_IDMAC_FATAL_BUS_ERROR              BIT(2)
 194 #define SDXC_IDMAC_DESTINATION_INVALID          BIT(4)
 195 #define SDXC_IDMAC_CARD_ERROR_SUM               BIT(5)
 196 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM         BIT(8)
 197 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM       BIT(9)
 198 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT         BIT(10)
 199 #define SDXC_IDMAC_IDLE                         (0 << 13)
 200 #define SDXC_IDMAC_SUSPEND                      (1 << 13)
 201 #define SDXC_IDMAC_DESC_READ                    (2 << 13)
 202 #define SDXC_IDMAC_DESC_CHECK                   (3 << 13)
 203 #define SDXC_IDMAC_READ_REQUEST_WAIT            (4 << 13)
 204 #define SDXC_IDMAC_WRITE_REQUEST_WAIT           (5 << 13)
 205 #define SDXC_IDMAC_READ                         (6 << 13)
 206 #define SDXC_IDMAC_WRITE                        (7 << 13)
 207 #define SDXC_IDMAC_DESC_CLOSE                   (8 << 13)
 208
 209 /*
 210 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
 211 *  Bits  0-12: buf1 size
 212 *  Bits 13-25: buf2 size
 213 *  Bits 26-31: not used
 214 * Since we only ever set buf1 size, we can simply store it directly.
 215 */
 216 #define SDXC_IDMAC_DES0_DIC     BIT(1)  /* disable interrupt on completion */
 217 #define SDXC_IDMAC_DES0_LD      BIT(2)  /* last descriptor */
 218 #define SDXC_IDMAC_DES0_FD      BIT(3)  /* first descriptor */
 219 #define SDXC_IDMAC_DES0_CH      BIT(4)  /* chain mode */
 220 #define SDXC_IDMAC_DES0_ER      BIT(5)  /* end of ring */
 221 #define SDXC_IDMAC_DES0_CES     BIT(30) /* card error summary */
 222 #define SDXC_IDMAC_DES0_OWN     BIT(31) /* 1-idma owns it, 0-host owns it */
 223
 224 #define SDXC_CLK_400K           0
 225 #define SDXC_CLK_25M            1
 226 #define SDXC_CLK_50M            2
 227 #define SDXC_CLK_50M_DDR        3
 228 #define SDXC_CLK_50M_DDR_8BIT   4
 229
 230 #define SDXC_2X_TIMING_MODE     BIT(31)
 231
 232 #define SDXC_CAL_START          BIT(15)
 233 #define SDXC_CAL_DONE           BIT(14)
 234 #define SDXC_CAL_DL_SHIFT       8
 235 #define SDXC_CAL_DL_SW_EN       BIT(7)
 236 #define SDXC_CAL_DL_SW_SHIFT    0
 237 #define SDXC_CAL_DL_MASK        0x3f
 238
 239 #define SDXC_CAL_TIMEOUT        3       /* in seconds, 3s is enough*/
 240
 241 struct sunxi_mmc_clk_delay {
 242         u32 output;
 243         u32 sample;
 244 };
 245
 246 struct sunxi_idma_des {
 247         __le32 config;
 248         __le32 buf_size;
 249         __le32 buf_addr_ptr1;
 250         __le32 buf_addr_ptr2;
 251 };
 252
 253 struct sunxi_mmc_cfg {
 254         u32 idma_des_size_bits;
 255         const struct sunxi_mmc_clk_delay *clk_delays;
 256
 257         /* does the IP block support autocalibration? */
 258         bool can_calibrate;
 259
 260         /* Does DATA0 needs to be masked while the clock is updated */
 261         bool mask_data0;
 262
 263         /* hardware only supports new timing mode */
 264         bool needs_new_timings;
 265
 266         /* hardware can switch between old and new timing modes */
 267         bool has_timings_switch;
 268 };
 269
 270 struct sunxi_mmc_host {
 271         struct mmc_host *mmc;
 272         struct reset_control *reset;
 273         const struct sunxi_mmc_cfg *cfg;
 274
 275         /* IO mapping base */
 276         void __iomem    *reg_base;
 277
 278         /* clock management */
 279         struct clk      *clk_ahb;
 280         struct clk      *clk_mmc;
 281         struct clk      *clk_sample;
 282         struct clk      *clk_output;
 283
 284         /* irq */
 285         spinlock_t      lock;
 286         int             irq;
 287         u32             int_sum;
 288         u32             sdio_imask;
 289
 290         /* dma */
 291         dma_addr_t      sg_dma;
 292         void            *sg_cpu;
 293         bool            wait_dma;
 294
 295         struct mmc_request *mrq;
 296         struct mmc_request *manual_stop_mrq;
 297         int             ferror;
 298
 299         /* vqmmc */
 300         bool            vqmmc_enabled;
 301
 302         /* timings */
 303         bool            use_new_timings;
 304 };
 305
 306 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
 307 {
 308         unsigned long expire = jiffies + msecs_to_jiffies(250);
 309         u32 rval;
 310
 311         mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
 312         do {
 313                 rval = mmc_readl(host, REG_GCTRL);
 314         } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
 315
 316         if (rval & SDXC_HARDWARE_RESET) {
 317                 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
 318                 return -EIO;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int sunxi_mmc_init_host(struct mmc_host *mmc)
 325 {
 326         u32 rval;
 327         struct sunxi_mmc_host *host = mmc_priv(mmc);
 328
 329         if (sunxi_mmc_reset_host(host))
 330                 return -EIO;
 331
 332         /*
 333          * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
 334          *
 335          * TODO: sun9i has a larger FIFO and supports higher trigger values
 336          */
 337         mmc_writel(host, REG_FTRGL, 0x20070008);
 338         /* Maximum timeout value */
 339         mmc_writel(host, REG_TMOUT, 0xffffffff);
 340         /* Unmask SDIO interrupt if needed */
 341         mmc_writel(host, REG_IMASK, host->sdio_imask);
 342         /* Clear all pending interrupts */
 343         mmc_writel(host, REG_RINTR, 0xffffffff);
 344         /* Debug register? undocumented */
 345         mmc_writel(host, REG_DBGC, 0xdeb);
 346         /* Enable CEATA support */
 347         mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
 348         /* Set DMA descriptor list base address */
 349         mmc_writel(host, REG_DLBA, host->sg_dma);
 350
 351         rval = mmc_readl(host, REG_GCTRL);
 352         rval |= SDXC_INTERRUPT_ENABLE_BIT;
 353         /* Undocumented, but found in Allwinner code */
 354         rval &= ~SDXC_ACCESS_DONE_DIRECT;
 355         mmc_writel(host, REG_GCTRL, rval);
 356
 357         return 0;
 358 }
 359
 360 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
 361                                     struct mmc_data *data)
 362 {
 363         struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
 364         dma_addr_t next_desc = host->sg_dma;
 365         int i, max_len = (1 << host->cfg->idma_des_size_bits);
 366
 367         for (i = 0; i < data->sg_len; i++) {
 368                 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
 369                                              SDXC_IDMAC_DES0_OWN |
 370                                              SDXC_IDMAC_DES0_DIC);
 371
 372                 if (data->sg[i].length == max_len)
 373                         pdes[i].buf_size = 0; /* 0 == max_len */
 374                 else
 375                         pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
 376
 377                 next_desc += sizeof(struct sunxi_idma_des);
 378                 pdes[i].buf_addr_ptr1 =
 379                         cpu_to_le32(sg_dma_address(&data->sg[i]));
 380                 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
 381         }
 382
 383         pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
 384         pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
 385                                           SDXC_IDMAC_DES0_ER);
 386         pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
 387         pdes[i - 1].buf_addr_ptr2 = 0;
 388
 389         /*
 390          * Avoid the io-store starting the idmac hitting io-mem before the
 391          * descriptors hit the main-mem.
 392          */
 393         wmb();
 394 }
 395
 396 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
 397                              struct mmc_data *data)
 398 {
 399         u32 i, dma_len;
 400         struct scatterlist *sg;
 401
 402         dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 403                              mmc_get_dma_dir(data));
 404         if (dma_len == 0) {
 405                 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
 406                 return -ENOMEM;
 407         }
 408
 409         for_each_sg(data->sg, sg, data->sg_len, i) {
 410                 if (sg->offset & 3 || sg->length & 3) {
 411                         dev_err(mmc_dev(host->mmc),
 412                                 "unaligned scatterlist: os %x length %d\n",
 413                                 sg->offset, sg->length);
 414                         return -EINVAL;
 415                 }
 416         }
 417
 418         return 0;
 419 }
 420
 421 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
 422                                 struct mmc_data *data)
 423 {
 424         u32 rval;
 425
 426         sunxi_mmc_init_idma_des(host, data);
 427
 428         rval = mmc_readl(host, REG_GCTRL);
 429         rval |= SDXC_DMA_ENABLE_BIT;
 430         mmc_writel(host, REG_GCTRL, rval);
 431         rval |= SDXC_DMA_RESET;
 432         mmc_writel(host, REG_GCTRL, rval);
 433
 434         mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
 435
 436         if (!(data->flags & MMC_DATA_WRITE))
 437                 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
 438
 439         mmc_writel(host, REG_DMAC,
 440                    SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
 441 }
 442
 443 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
 444                                        struct mmc_request *req)
 445 {
 446         u32 arg, cmd_val, ri;
 447         unsigned long expire = jiffies + msecs_to_jiffies(1000);
 448
 449         cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
 450                   SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
 451
 452         if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
 453                 cmd_val |= SD_IO_RW_DIRECT;
 454                 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 455                       ((req->cmd->arg >> 28) & 0x7);
 456         } else {
 457                 cmd_val |= MMC_STOP_TRANSMISSION;
 458                 arg = 0;
 459         }
 460
 461         mmc_writel(host, REG_CARG, arg);
 462         mmc_writel(host, REG_CMDR, cmd_val);
 463
 464         do {
 465                 ri = mmc_readl(host, REG_RINTR);
 466         } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
 467                  time_before(jiffies, expire));
 468
 469         if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
 470                 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
 471                 if (req->stop)
 472                         req->stop->resp[0] = -ETIMEDOUT;
 473         } else {
 474                 if (req->stop)
 475                         req->stop->resp[0] = mmc_readl(host, REG_RESP0);
 476         }
 477
 478         mmc_writel(host, REG_RINTR, 0xffff);
 479 }
 480
 481 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
 482 {
 483         struct mmc_command *cmd = host->mrq->cmd;
 484         struct mmc_data *data = host->mrq->data;
 485
 486         /* For some cmds timeout is normal with sd/mmc cards */
 487         if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
 488                 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
 489                                       cmd->opcode == SD_IO_RW_DIRECT))
 490                 return;
 491
 492         dev_dbg(mmc_dev(host->mmc),
 493                 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
 494                 host->mmc->index, cmd->opcode,
 495                 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
 496                 host->int_sum & SDXC_RESP_ERROR     ? " RE"     : "",
 497                 host->int_sum & SDXC_RESP_CRC_ERROR  ? " RCE"    : "",
 498                 host->int_sum & SDXC_DATA_CRC_ERROR  ? " DCE"    : "",
 499                 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO"    : "",
 500                 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO"    : "",
 501                 host->int_sum & SDXC_FIFO_RUN_ERROR  ? " FE"     : "",
 502                 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL"     : "",
 503                 host->int_sum & SDXC_START_BIT_ERROR ? " SBE"    : "",
 504                 host->int_sum & SDXC_END_BIT_ERROR   ? " EBE"    : ""
 505                 );
 506 }
 507
 508 /* Called in interrupt context! */
 509 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
 510 {
 511         struct mmc_request *mrq = host->mrq;
 512         struct mmc_data *data = mrq->data;
 513         u32 rval;
 514
 515         mmc_writel(host, REG_IMASK, host->sdio_imask);
 516         mmc_writel(host, REG_IDIE, 0);
 517
 518         if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
 519                 sunxi_mmc_dump_errinfo(host);
 520                 mrq->cmd->error = -ETIMEDOUT;
 521
 522                 if (data) {
 523                         data->error = -ETIMEDOUT;
 524                         host->manual_stop_mrq = mrq;
 525                 }
 526
 527                 if (mrq->stop)
 528                         mrq->stop->error = -ETIMEDOUT;
 529         } else {
 530                 if (mrq->cmd->flags & MMC_RSP_136) {
 531                         mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
 532                         mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
 533                         mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
 534                         mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
 535                 } else {
 536                         mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
 537                 }
 538
 539                 if (data)
 540                         data->bytes_xfered = data->blocks * data->blksz;
 541         }
 542
 543         if (data) {
 544                 mmc_writel(host, REG_IDST, 0x337);
 545                 mmc_writel(host, REG_DMAC, 0);
 546                 rval = mmc_readl(host, REG_GCTRL);
 547                 rval |= SDXC_DMA_RESET;
 548                 mmc_writel(host, REG_GCTRL, rval);
 549                 rval &= ~SDXC_DMA_ENABLE_BIT;
 550                 mmc_writel(host, REG_GCTRL, rval);
 551                 rval |= SDXC_FIFO_RESET;
 552                 mmc_writel(host, REG_GCTRL, rval);
 553                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 554                              mmc_get_dma_dir(data));
 555         }
 556
 557         mmc_writel(host, REG_RINTR, 0xffff);
 558
 559         host->mrq = NULL;
 560         host->int_sum = 0;
 561         host->wait_dma = false;
 562
 563         return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
 564 }
 565
 566 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
 567 {
 568         struct sunxi_mmc_host *host = dev_id;
 569         struct mmc_request *mrq;
 570         u32 msk_int, idma_int;
 571         bool finalize = false;
 572         bool sdio_int = false;
 573         irqreturn_t ret = IRQ_HANDLED;
 574
 575         spin_lock(&host->lock);
 576
 577         idma_int  = mmc_readl(host, REG_IDST);
 578         msk_int   = mmc_readl(host, REG_MISTA);
 579
 580         dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
 581                 host->mrq, msk_int, idma_int);
 582
 583         mrq = host->mrq;
 584         if (mrq) {
 585                 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
 586                         host->wait_dma = false;
 587
 588                 host->int_sum |= msk_int;
 589
 590                 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
 591                 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
 592                                 !(host->int_sum & SDXC_COMMAND_DONE))
 593                         mmc_writel(host, REG_IMASK,
 594                                    host->sdio_imask | SDXC_COMMAND_DONE);
 595                 /* Don't wait for dma on error */
 596                 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
 597                         finalize = true;
 598                 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
 599                                 !host->wait_dma)
 600                         finalize = true;
 601         }
 602
 603         if (msk_int & SDXC_SDIO_INTERRUPT)
 604                 sdio_int = true;
 605
 606         mmc_writel(host, REG_RINTR, msk_int);
 607         mmc_writel(host, REG_IDST, idma_int);
 608
 609         if (finalize)
 610                 ret = sunxi_mmc_finalize_request(host);
 611
 612         spin_unlock(&host->lock);
 613
 614         if (finalize && ret == IRQ_HANDLED)
 615                 mmc_request_done(host->mmc, mrq);
 616
 617         if (sdio_int)
 618                 mmc_signal_sdio_irq(host->mmc);
 619
 620         return ret;
 621 }
 622
 623 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
 624 {
 625         struct sunxi_mmc_host *host = dev_id;
 626         struct mmc_request *mrq;
 627         unsigned long iflags;
 628
 629         spin_lock_irqsave(&host->lock, iflags);
 630         mrq = host->manual_stop_mrq;
 631         spin_unlock_irqrestore(&host->lock, iflags);
 632
 633         if (!mrq) {
 634                 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
 635                 return IRQ_HANDLED;
 636         }
 637
 638         dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
 639
 640         /*
 641          * We will never have more than one outstanding request,
 642          * and we do not complete the request until after
 643          * we've cleared host->manual_stop_mrq so we do not need to
 644          * spin lock this function.
 645          * Additionally we have wait states within this function
 646          * so having it in a lock is a very bad idea.
 647          */
 648         sunxi_mmc_send_manual_stop(host, mrq);
 649
 650         spin_lock_irqsave(&host->lock, iflags);
 651         host->manual_stop_mrq = NULL;
 652         spin_unlock_irqrestore(&host->lock, iflags);
 653
 654         mmc_request_done(host->mmc, mrq);
 655
 656         return IRQ_HANDLED;
 657 }
 658
 659 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
 660 {
 661         unsigned long expire = jiffies + msecs_to_jiffies(750);
 662         u32 rval;
 663
 664         dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
 665                 oclk_en ? "en" : "dis");
 666
 667         rval = mmc_readl(host, REG_CLKCR);
 668         rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
 669
 670         if (oclk_en)
 671                 rval |= SDXC_CARD_CLOCK_ON;
 672         if (host->cfg->mask_data0)
 673                 rval |= SDXC_MASK_DATA0;
 674
 675         mmc_writel(host, REG_CLKCR, rval);
 676
 677         rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
 678         mmc_writel(host, REG_CMDR, rval);
 679
 680         do {
 681                 rval = mmc_readl(host, REG_CMDR);
 682         } while (time_before(jiffies, expire) && (rval & SDXC_START));
 683
 684         /* clear irq status bits set by the command */
 685         mmc_writel(host, REG_RINTR,
 686                    mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
 687
 688         if (rval & SDXC_START) {
 689                 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
 690                 return -EIO;
 691         }
 692
 693         if (host->cfg->mask_data0) {
 694                 rval = mmc_readl(host, REG_CLKCR);
 695                 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
 696         }
 697
 698         return 0;
 699 }
 700
 701 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
 702 {
 703         if (!host->cfg->can_calibrate)
 704                 return 0;
 705
 706         /*
 707          * FIXME:
 708          * This is not clear how the calibration is supposed to work
 709          * yet. The best rate have been obtained by simply setting the
 710          * delay to 0, as Allwinner does in its BSP.
 711          *
 712          * The only mode that doesn't have such a delay is HS400, that
 713          * is in itself a TODO.
 714          */
 715         writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
 716
 717         return 0;
 718 }
 719
 720 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
 721                                    struct mmc_ios *ios, u32 rate)
 722 {
 723         int index;
 724
 725         if (host->use_new_timings)
 726                 return 0;
 727
 728         /* determine delays */
 729         if (rate <= 400000) {
 730                 index = SDXC_CLK_400K;
 731         } else if (rate <= 25000000) {
 732                 index = SDXC_CLK_25M;
 733         } else if (rate <= 52000000) {
 734                 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
 735                     ios->timing != MMC_TIMING_MMC_DDR52) {
 736                         index = SDXC_CLK_50M;
 737                 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
 738                         index = SDXC_CLK_50M_DDR_8BIT;
 739                 } else {
 740                         index = SDXC_CLK_50M_DDR;
 741                 }
 742         } else {
 743                 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
 744                 return -EINVAL;
 745         }
 746
 747         clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
 748         clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
 749
 750         return 0;
 751 }
 752
 753 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 754                                   struct mmc_ios *ios)
 755 {
 756         struct mmc_host *mmc = host->mmc;
 757         long rate;
 758         u32 rval, clock = ios->clock, div = 1;
 759         int ret;
 760
 761         ret = sunxi_mmc_oclk_onoff(host, 0);
 762         if (ret)
 763                 return ret;
 764
 765         /* Our clock is gated now */
 766         mmc->actual_clock = 0;
 767
 768         if (!ios->clock)
 769                 return 0;
 770
 771         /*
 772          * Under the old timing mode, 8 bit DDR requires the module
 773          * clock to be double the card clock. Under the new timing
 774          * mode, all DDR modes require a doubled module clock.
 775          *
 776          * We currently only support the standard MMC DDR52 mode.
 777          * This block should be updated once support for other DDR
 778          * modes is added.
 779          */
 780         if (ios->timing == MMC_TIMING_MMC_DDR52 &&
 781             (host->use_new_timings ||
 782              ios->bus_width == MMC_BUS_WIDTH_8)) {
 783                 div = 2;
 784                 clock <<= 1;
 785         }
 786
 787         if (host->use_new_timings) {
 788                 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
 789                 if (ret) {
 790                         dev_err(mmc_dev(mmc),
 791                                 "error setting new timing mode\n");
 792                         return ret;
 793                 }
 794         }
 795
 796         rate = clk_round_rate(host->clk_mmc, clock);
 797         if (rate < 0) {
 798                 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
 799                         clock, rate);
 800                 return rate;
 801         }
 802         dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
 803                 clock, rate);
 804
 805         /* setting clock rate */
 806         ret = clk_set_rate(host->clk_mmc, rate);
 807         if (ret) {
 808                 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
 809                         rate, ret);
 810                 return ret;
 811         }
 812
 813         /* set internal divider */
 814         rval = mmc_readl(host, REG_CLKCR);
 815         rval &= ~0xff;
 816         rval |= div - 1;
 817         mmc_writel(host, REG_CLKCR, rval);
 818
 819         if (host->use_new_timings) {
 820                 /* Don't touch the delay bits */
 821                 rval = mmc_readl(host, REG_SD_NTSR);
 822                 rval |= SDXC_2X_TIMING_MODE;
 823                 mmc_writel(host, REG_SD_NTSR, rval);
 824         }
 825
 826         ret = sunxi_mmc_clk_set_phase(host, ios, rate);
 827         if (ret)
 828                 return ret;
 829
 830         ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
 831         if (ret)
 832                 return ret;
 833
 834         /*
 835          * FIXME:
 836          *
 837          * In HS400 we'll also need to calibrate the data strobe
 838          * signal. This should only happen on the MMC2 controller (at
 839          * least on the A64).
 840          */
 841
 842         ret = sunxi_mmc_oclk_onoff(host, 1);
 843         if (ret)
 844                 return ret;
 845
 846         /* And we just enabled our clock back */
 847         mmc->actual_clock = rate / div;
 848
 849         return 0;
 850 }
 851
 852 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 853 {
 854         struct sunxi_mmc_host *host = mmc_priv(mmc);
 855         u32 rval;
 856
 857         /* Set the power state */
 858         switch (ios->power_mode) {
 859         case MMC_POWER_ON:
 860                 break;
 861
 862         case MMC_POWER_UP:
 863                 if (!IS_ERR(mmc->supply.vmmc)) {
 864                         host->ferror = mmc_regulator_set_ocr(mmc,
 865                                                              mmc->supply.vmmc,
 866                                                              ios->vdd);
 867                         if (host->ferror)
 868                                 return;
 869                 }
 870
 871                 if (!IS_ERR(mmc->supply.vqmmc)) {
 872                         host->ferror = regulator_enable(mmc->supply.vqmmc);
 873                         if (host->ferror) {
 874                                 dev_err(mmc_dev(mmc),
 875                                         "failed to enable vqmmc\n");
 876                                 return;
 877                         }
 878                         host->vqmmc_enabled = true;
 879                 }
 880
 881                 host->ferror = sunxi_mmc_init_host(mmc);
 882                 if (host->ferror)
 883                         return;
 884
 885                 dev_dbg(mmc_dev(mmc), "power on!\n");
 886                 break;
 887
 888         case MMC_POWER_OFF:
 889                 dev_dbg(mmc_dev(mmc), "power off!\n");
 890                 sunxi_mmc_reset_host(host);
 891                 if (!IS_ERR(mmc->supply.vmmc))
 892                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
 893
 894                 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
 895                         regulator_disable(mmc->supply.vqmmc);
 896                 host->vqmmc_enabled = false;
 897                 break;
 898         }
 899
 900         /* set bus width */
 901         switch (ios->bus_width) {
 902         case MMC_BUS_WIDTH_1:
 903                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
 904                 break;
 905         case MMC_BUS_WIDTH_4:
 906                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
 907                 break;
 908         case MMC_BUS_WIDTH_8:
 909                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
 910                 break;
 911         }
 912
 913         /* set ddr mode */
 914         rval = mmc_readl(host, REG_GCTRL);
 915         if (ios->timing == MMC_TIMING_UHS_DDR50 ||
 916             ios->timing == MMC_TIMING_MMC_DDR52)
 917                 rval |= SDXC_DDR_MODE;
 918         else
 919                 rval &= ~SDXC_DDR_MODE;
 920         mmc_writel(host, REG_GCTRL, rval);
 921
 922         /* set up clock */
 923         if (ios->power_mode) {
 924                 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
 925                 /* Android code had a usleep_range(50000, 55000); here */
 926         }
 927 }
 928
 929 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
 930 {
 931         /* vqmmc regulator is available */
 932         if (!IS_ERR(mmc->supply.vqmmc))
 933                 return mmc_regulator_set_vqmmc(mmc, ios);
 934
 935         /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
 936         if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 937                 return 0;
 938
 939         return -EINVAL;
 940 }
 941
 942 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 943 {
 944         struct sunxi_mmc_host *host = mmc_priv(mmc);
 945         unsigned long flags;
 946         u32 imask;
 947
 948         spin_lock_irqsave(&host->lock, flags);
 949
 950         imask = mmc_readl(host, REG_IMASK);
 951         if (enable) {
 952                 host->sdio_imask = SDXC_SDIO_INTERRUPT;
 953                 imask |= SDXC_SDIO_INTERRUPT;
 954         } else {
 955                 host->sdio_imask = 0;
 956                 imask &= ~SDXC_SDIO_INTERRUPT;
 957         }
 958         mmc_writel(host, REG_IMASK, imask);
 959         spin_unlock_irqrestore(&host->lock, flags);
 960 }
 961
 962 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
 963 {
 964         struct sunxi_mmc_host *host = mmc_priv(mmc);
 965         mmc_writel(host, REG_HWRST, 0);
 966         udelay(10);
 967         mmc_writel(host, REG_HWRST, 1);
 968         udelay(300);
 969 }
 970
 971 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 972 {
 973         struct sunxi_mmc_host *host = mmc_priv(mmc);
 974         struct mmc_command *cmd = mrq->cmd;
 975         struct mmc_data *data = mrq->data;
 976         unsigned long iflags;
 977         u32 imask = SDXC_INTERRUPT_ERROR_BIT;
 978         u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
 979         bool wait_dma = host->wait_dma;
 980         int ret;
 981
 982         /* Check for set_ios errors (should never happen) */
 983         if (host->ferror) {
 984                 mrq->cmd->error = host->ferror;
 985                 mmc_request_done(mmc, mrq);
 986                 return;
 987         }
 988
 989         if (data) {
 990                 ret = sunxi_mmc_map_dma(host, data);
 991                 if (ret < 0) {
 992                         dev_err(mmc_dev(mmc), "map DMA failed\n");
 993                         cmd->error = ret;
 994                         data->error = ret;
 995                         mmc_request_done(mmc, mrq);
 996                         return;
 997                 }
 998         }
 999
1000         if (cmd->opcode == MMC_GO_IDLE_STATE) {
1001                 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
1002                 imask |= SDXC_COMMAND_DONE;
1003         }
1004
1005         if (cmd->flags & MMC_RSP_PRESENT) {
1006                 cmd_val |= SDXC_RESP_EXPIRE;
1007                 if (cmd->flags & MMC_RSP_136)
1008                         cmd_val |= SDXC_LONG_RESPONSE;
1009                 if (cmd->flags & MMC_RSP_CRC)
1010                         cmd_val |= SDXC_CHECK_RESPONSE_CRC;
1011
1012                 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
1013                         cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
1014
1015                         if (cmd->data->stop) {
1016                                 imask |= SDXC_AUTO_COMMAND_DONE;
1017                                 cmd_val |= SDXC_SEND_AUTO_STOP;
1018                         } else {
1019                                 imask |= SDXC_DATA_OVER;
1020                         }
1021
1022                         if (cmd->data->flags & MMC_DATA_WRITE)
1023                                 cmd_val |= SDXC_WRITE;
1024                         else
1025                                 wait_dma = true;
1026                 } else {
1027                         imask |= SDXC_COMMAND_DONE;
1028                 }
1029         } else {
1030                 imask |= SDXC_COMMAND_DONE;
1031         }
1032
1033         dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
1034                 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1035                 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1036
1037         spin_lock_irqsave(&host->lock, iflags);
1038
1039         if (host->mrq || host->manual_stop_mrq) {
1040                 spin_unlock_irqrestore(&host->lock, iflags);
1041
1042                 if (data)
1043                         dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1044                                      mmc_get_dma_dir(data));
1045
1046                 dev_err(mmc_dev(mmc), "request already pending\n");
1047                 mrq->cmd->error = -EBUSY;
1048                 mmc_request_done(mmc, mrq);
1049                 return;
1050         }
1051
1052         if (data) {
1053                 mmc_writel(host, REG_BLKSZ, data->blksz);
1054                 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1055                 sunxi_mmc_start_dma(host, data);
1056         }
1057
1058         host->mrq = mrq;
1059         host->wait_dma = wait_dma;
1060         mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1061         mmc_writel(host, REG_CARG, cmd->arg);
1062         mmc_writel(host, REG_CMDR, cmd_val);
1063
1064         spin_unlock_irqrestore(&host->lock, iflags);
1065 }
1066
1067 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1068 {
1069         struct sunxi_mmc_host *host = mmc_priv(mmc);
1070
1071         return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1072 }
1073
1074 static const struct mmc_host_ops sunxi_mmc_ops = {
1075         .request         = sunxi_mmc_request,
1076         .set_ios         = sunxi_mmc_set_ios,
1077         .get_ro          = mmc_gpio_get_ro,
1078         .get_cd          = mmc_gpio_get_cd,
1079         .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
1080         .start_signal_voltage_switch = sunxi_mmc_volt_switch,
1081         .hw_reset        = sunxi_mmc_hw_reset,
1082         .card_busy       = sunxi_mmc_card_busy,
1083 };
1084
1085 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1086         [SDXC_CLK_400K]         = { .output = 180, .sample = 180 },
1087         [SDXC_CLK_25M]          = { .output = 180, .sample =  75 },
1088         [SDXC_CLK_50M]          = { .output =  90, .sample = 120 },
1089         [SDXC_CLK_50M_DDR]      = { .output =  60, .sample = 120 },
1090         /* Value from A83T "new timing mode". Works but might not be right. */
1091         [SDXC_CLK_50M_DDR_8BIT] = { .output =  90, .sample = 180 },
1092 };
1093
1094 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1095         [SDXC_CLK_400K]         = { .output = 180, .sample = 180 },
1096         [SDXC_CLK_25M]          = { .output = 180, .sample =  75 },
1097         [SDXC_CLK_50M]          = { .output = 150, .sample = 120 },
1098         [SDXC_CLK_50M_DDR]      = { .output =  54, .sample =  36 },
1099         [SDXC_CLK_50M_DDR_8BIT] = { .output =  72, .sample =  72 },
1100 };
1101
1102 static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1103         .idma_des_size_bits = 13,
1104         .clk_delays = NULL,
1105         .can_calibrate = false,
1106 };
1107
1108 static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
1109         .idma_des_size_bits = 16,
1110         .clk_delays = NULL,
1111         .can_calibrate = false,
1112 };
1113
1114 static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
1115         .idma_des_size_bits = 16,
1116         .clk_delays = sunxi_mmc_clk_delays,
1117         .can_calibrate = false,
1118 };
1119
1120 static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {
1121         .idma_des_size_bits = 16,
1122         .clk_delays = sunxi_mmc_clk_delays,
1123         .can_calibrate = false,
1124         .has_timings_switch = true,
1125 };
1126
1127 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1128         .idma_des_size_bits = 16,
1129         .clk_delays = sun9i_mmc_clk_delays,
1130         .can_calibrate = false,
1131 };
1132
1133 static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1134         .idma_des_size_bits = 16,
1135         .clk_delays = NULL,
1136         .can_calibrate = true,
1137         .mask_data0 = true,
1138         .needs_new_timings = true,
1139 };
1140
1141 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
1142         .idma_des_size_bits = 13,
1143         .clk_delays = NULL,
1144         .can_calibrate = true,
1145 };
1146
1147 static const struct of_device_id sunxi_mmc_of_match[] = {
1148         { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1149         { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1150         { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1151         { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },
1152         { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1153         { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
1154         { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
1155         { /* sentinel */ }
1156 };
1157 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1158
1159 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1160                                       struct platform_device *pdev)
1161 {
1162         int ret;
1163
1164         host->cfg = of_device_get_match_data(&pdev->dev);
1165         if (!host->cfg)
1166                 return -EINVAL;
1167
1168         ret = mmc_regulator_get_supply(host->mmc);
1169         if (ret) {
1170                 if (ret != -EPROBE_DEFER)
1171                         dev_err(&pdev->dev, "Could not get vmmc supply\n");
1172                 return ret;
1173         }
1174
1175         host->reg_base = devm_ioremap_resource(&pdev->dev,
1176                               platform_get_resource(pdev, IORESOURCE_MEM, 0));
1177         if (IS_ERR(host->reg_base))
1178                 return PTR_ERR(host->reg_base);
1179
1180         host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1181         if (IS_ERR(host->clk_ahb)) {
1182                 dev_err(&pdev->dev, "Could not get ahb clock\n");
1183                 return PTR_ERR(host->clk_ahb);
1184         }
1185
1186         host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1187         if (IS_ERR(host->clk_mmc)) {
1188                 dev_err(&pdev->dev, "Could not get mmc clock\n");
1189                 return PTR_ERR(host->clk_mmc);
1190         }
1191
1192         if (host->cfg->clk_delays) {
1193                 host->clk_output = devm_clk_get(&pdev->dev, "output");
1194                 if (IS_ERR(host->clk_output)) {
1195                         dev_err(&pdev->dev, "Could not get output clock\n");
1196                         return PTR_ERR(host->clk_output);
1197                 }
1198
1199                 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1200                 if (IS_ERR(host->clk_sample)) {
1201                         dev_err(&pdev->dev, "Could not get sample clock\n");
1202                         return PTR_ERR(host->clk_sample);
1203                 }
1204         }
1205
1206         host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1207                                                                 "ahb");
1208         if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1209                 return PTR_ERR(host->reset);
1210
1211         ret = clk_prepare_enable(host->clk_ahb);
1212         if (ret) {
1213                 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1214                 return ret;
1215         }
1216
1217         ret = clk_prepare_enable(host->clk_mmc);
1218         if (ret) {
1219                 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1220                 goto error_disable_clk_ahb;
1221         }
1222
1223         ret = clk_prepare_enable(host->clk_output);
1224         if (ret) {
1225                 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1226                 goto error_disable_clk_mmc;
1227         }
1228
1229         ret = clk_prepare_enable(host->clk_sample);
1230         if (ret) {
1231                 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1232                 goto error_disable_clk_output;
1233         }
1234
1235         if (!IS_ERR(host->reset)) {
1236                 ret = reset_control_deassert(host->reset);
1237                 if (ret) {
1238                         dev_err(&pdev->dev, "reset err %d\n", ret);
1239                         goto error_disable_clk_sample;
1240                 }
1241         }
1242
1243         /*
1244          * Sometimes the controller asserts the irq on boot for some reason,
1245          * make sure the controller is in a sane state before enabling irqs.
1246          */
1247         ret = sunxi_mmc_reset_host(host);
1248         if (ret)
1249                 goto error_assert_reset;
1250
1251         host->irq = platform_get_irq(pdev, 0);
1252         return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1253                         sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1254
1255 error_assert_reset:
1256         if (!IS_ERR(host->reset))
1257                 reset_control_assert(host->reset);
1258 error_disable_clk_sample:
1259         clk_disable_unprepare(host->clk_sample);
1260 error_disable_clk_output:
1261         clk_disable_unprepare(host->clk_output);
1262 error_disable_clk_mmc:
1263         clk_disable_unprepare(host->clk_mmc);
1264 error_disable_clk_ahb:
1265         clk_disable_unprepare(host->clk_ahb);
1266         return ret;
1267 }
1268
1269 static int sunxi_mmc_probe(struct platform_device *pdev)
1270 {
1271         struct sunxi_mmc_host *host;
1272         struct mmc_host *mmc;
1273         int ret;
1274
1275         mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1276         if (!mmc) {
1277                 dev_err(&pdev->dev, "mmc alloc host failed\n");
1278                 return -ENOMEM;
1279         }
1280
1281         host = mmc_priv(mmc);
1282         host->mmc = mmc;
1283         spin_lock_init(&host->lock);
1284
1285         ret = sunxi_mmc_resource_request(host, pdev);
1286         if (ret)
1287                 goto error_free_host;
1288
1289         host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1290                                           &host->sg_dma, GFP_KERNEL);
1291         if (!host->sg_cpu) {
1292                 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1293                 ret = -ENOMEM;
1294                 goto error_free_host;
1295         }
1296
1297         if (host->cfg->has_timings_switch) {
1298                 /*
1299                  * Supports both old and new timing modes.
1300                  * Try setting the clk to new timing mode.
1301                  */
1302                 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
1303
1304                 /* And check the result */
1305                 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc);
1306                 if (ret < 0) {
1307                         /*
1308                          * For whatever reason we were not able to get
1309                          * the current active mode. Default to old mode.
1310                          */
1311                         dev_warn(&pdev->dev, "MMC clk timing mode unknown\n");
1312                         host->use_new_timings = false;
1313                 } else {
1314                         host->use_new_timings = !!ret;
1315                 }
1316         } else if (host->cfg->needs_new_timings) {
1317                 /* Supports new timing mode only */
1318                 host->use_new_timings = true;
1319         }
1320
1321         mmc->ops                = &sunxi_mmc_ops;
1322         mmc->max_blk_count      = 8192;
1323         mmc->max_blk_size       = 4096;
1324         mmc->max_segs           = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1325         mmc->max_seg_size       = (1 << host->cfg->idma_des_size_bits);
1326         mmc->max_req_size       = mmc->max_seg_size * mmc->max_segs;
1327         /* 400kHz ~ 52MHz */
1328         mmc->f_min              =   400000;
1329         mmc->f_max              = 52000000;
1330         mmc->caps              |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1331                                   MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1332
1333         if (host->cfg->clk_delays || host->use_new_timings)
1334                 mmc->caps      |= MMC_CAP_1_8V_DDR;
1335
1336         ret = mmc_of_parse(mmc);
1337         if (ret)
1338                 goto error_free_dma;
1339
1340         ret = mmc_add_host(mmc);
1341         if (ret)
1342                 goto error_free_dma;
1343
1344         dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1345         platform_set_drvdata(pdev, mmc);
1346         return 0;
1347
1348 error_free_dma:
1349         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1350 error_free_host:
1351         mmc_free_host(mmc);
1352         return ret;
1353 }
1354
1355 static int sunxi_mmc_remove(struct platform_device *pdev)
1356 {
1357         struct mmc_host *mmc = platform_get_drvdata(pdev);
1358         struct sunxi_mmc_host *host = mmc_priv(mmc);
1359
1360         mmc_remove_host(mmc);
1361         disable_irq(host->irq);
1362         sunxi_mmc_reset_host(host);
1363
1364         if (!IS_ERR(host->reset))
1365                 reset_control_assert(host->reset);
1366
1367         clk_disable_unprepare(host->clk_sample);
1368         clk_disable_unprepare(host->clk_output);
1369         clk_disable_unprepare(host->clk_mmc);
1370         clk_disable_unprepare(host->clk_ahb);
1371
1372         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1373         mmc_free_host(mmc);
1374
1375         return 0;
1376 }
1377
1378 static struct platform_driver sunxi_mmc_driver = {
1379         .driver = {
1380                 .name   = "sunxi-mmc",
1381                 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1382         },
1383         .probe          = sunxi_mmc_probe,
1384         .remove         = sunxi_mmc_remove,
1385 };
1386 module_platform_driver(sunxi_mmc_driver);
1387
1388 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1389 MODULE_LICENSE("GPL v2");
1390 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1391 MODULE_ALIAS("platform:sunxi-mmc");