1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
9 #include <linux/iopoll.h>
11 #include <linux/module.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/property.h>
14 #include <linux/regmap.h>
15 #include <linux/sys_soc.h>
18 #include "sdhci-pltfm.h"
20 /* CTL_CFG Registers */
21 #define CTL_CFG_2 0x14
22 #define CTL_CFG_3 0x18
24 #define SLOTTYPE_MASK GENMASK(31, 30)
25 #define SLOTTYPE_EMBEDDED BIT(30)
26 #define TUNINGFORSDR50_MASK BIT(13)
29 #define PHY_CTRL1 0x100
30 #define PHY_CTRL2 0x104
31 #define PHY_CTRL3 0x108
32 #define PHY_CTRL4 0x10C
33 #define PHY_CTRL5 0x110
34 #define PHY_CTRL6 0x114
35 #define PHY_STAT1 0x130
36 #define PHY_STAT2 0x134
38 #define IOMUX_ENABLE_SHIFT 31
39 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
40 #define OTAPDLYENA_SHIFT 20
41 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
42 #define OTAPDLYSEL_SHIFT 12
43 #define OTAPDLYSEL_MASK GENMASK(15, 12)
44 #define STRBSEL_SHIFT 24
45 #define STRBSEL_4BIT_MASK GENMASK(27, 24)
46 #define STRBSEL_8BIT_MASK GENMASK(31, 24)
48 #define SEL50_MASK BIT(SEL50_SHIFT)
49 #define SEL100_SHIFT 9
50 #define SEL100_MASK BIT(SEL100_SHIFT)
51 #define FREQSEL_SHIFT 8
52 #define FREQSEL_MASK GENMASK(10, 8)
53 #define CLKBUFSEL_SHIFT 0
54 #define CLKBUFSEL_MASK GENMASK(2, 0)
55 #define DLL_TRIM_ICP_SHIFT 4
56 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
57 #define DR_TY_SHIFT 20
58 #define DR_TY_MASK GENMASK(22, 20)
60 #define ENDLL_MASK BIT(ENDLL_SHIFT)
61 #define DLLRDY_SHIFT 0
62 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
64 #define PDB_MASK BIT(PDB_SHIFT)
65 #define CALDONE_SHIFT 1
66 #define CALDONE_MASK BIT(CALDONE_SHIFT)
67 #define RETRIM_SHIFT 17
68 #define RETRIM_MASK BIT(RETRIM_SHIFT)
69 #define SELDLYTXCLK_SHIFT 17
70 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
71 #define SELDLYRXCLK_SHIFT 16
72 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
73 #define ITAPDLYSEL_SHIFT 0
74 #define ITAPDLYSEL_MASK GENMASK(4, 0)
75 #define ITAPDLYENA_SHIFT 8
76 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
77 #define ITAPCHGWIN_SHIFT 9
78 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
80 #define DRIVER_STRENGTH_50_OHM 0x0
81 #define DRIVER_STRENGTH_33_OHM 0x1
82 #define DRIVER_STRENGTH_66_OHM 0x2
83 #define DRIVER_STRENGTH_100_OHM 0x3
84 #define DRIVER_STRENGTH_40_OHM 0x4
86 #define CLOCK_TOO_SLOW_HZ 50000000
88 /* Command Queue Host Controller Interface Base address */
89 #define SDHCI_AM654_CQE_BASE_ADDR 0x200
91 static struct regmap_config sdhci_am654_regmap_config = {
99 const char *otap_binding;
100 const char *itap_binding;
104 static const struct timing_data td[] = {
105 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
106 "ti,itap-del-sel-legacy",
108 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
109 "ti,itap-del-sel-mmc-hs",
110 MMC_CAP_MMC_HIGHSPEED},
111 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
112 "ti,itap-del-sel-sd-hs",
113 MMC_CAP_SD_HIGHSPEED},
114 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
115 "ti,itap-del-sel-sdr12",
117 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
118 "ti,itap-del-sel-sdr25",
120 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
123 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
126 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
129 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
130 "ti,itap-del-sel-ddr52",
132 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
135 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
140 struct sdhci_am654_data {
143 int otap_del_sel[ARRAY_SIZE(td)];
144 int itap_del_sel[ARRAY_SIZE(td)];
152 struct sdhci_am654_driver_data {
153 const struct sdhci_pltfm_data *pdata;
155 #define IOMUX_PRESENT (1 << 0)
156 #define FREQSEL_2_BIT (1 << 1)
157 #define STRBSEL_4_BIT (1 << 2)
158 #define DLL_PRESENT (1 << 3)
159 #define DLL_CALIB (1 << 4)
162 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
164 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
165 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
166 int sel50, sel100, freqsel;
170 /* Disable delay chain mode */
171 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
172 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
174 if (sdhci_am654->flags & FREQSEL_2_BIT) {
189 /* Configure PHY DLL frequency */
190 mask = SEL50_MASK | SEL100_MASK;
191 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
192 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
203 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
204 freqsel << FREQSEL_SHIFT);
206 /* Configure DLL TRIM */
207 mask = DLL_TRIM_ICP_MASK;
208 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
210 /* Configure DLL driver strength */
212 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
213 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
216 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
219 * Poll for DLL ready. Use a one second timeout.
220 * Works in all experiments done so far
222 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
223 val & DLLRDY_MASK, 1000, 1000000);
225 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
230 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
233 /* Set ITAPCHGWIN before writing to ITAPDLY */
234 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
235 1 << ITAPCHGWIN_SHIFT);
236 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
237 itapdly << ITAPDLYSEL_SHIFT);
238 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
241 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
242 unsigned char timing)
246 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
248 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
249 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
252 sdhci_am654_write_itapdly(sdhci_am654,
253 sdhci_am654->itap_del_sel[timing]);
256 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
258 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
259 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
260 unsigned char timing = host->mmc->ios.timing;
265 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
267 sdhci_set_clock(host, clock);
269 /* Setup DLL Output TAP delay */
270 if (sdhci_am654->legacy_otapdly)
271 otap_del_sel = sdhci_am654->otap_del_sel[0];
273 otap_del_sel = sdhci_am654->otap_del_sel[timing];
275 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
277 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
278 val = (otap_del_ena << OTAPDLYENA_SHIFT) |
279 (otap_del_sel << OTAPDLYSEL_SHIFT);
281 /* Write to STRBSEL for HS400 speed mode */
282 if (timing == MMC_TIMING_MMC_HS400) {
283 if (sdhci_am654->flags & STRBSEL_4_BIT)
284 mask |= STRBSEL_4BIT_MASK;
286 mask |= STRBSEL_8BIT_MASK;
288 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
291 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
293 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ)
294 sdhci_am654_setup_dll(host, clock);
296 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
298 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
299 sdhci_am654->clkbuf_sel);
302 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
305 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
306 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
307 unsigned char timing = host->mmc->ios.timing;
311 /* Setup DLL Output TAP delay */
312 if (sdhci_am654->legacy_otapdly)
313 otap_del_sel = sdhci_am654->otap_del_sel[0];
315 otap_del_sel = sdhci_am654->otap_del_sel[timing];
317 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
318 val = (0x1 << OTAPDLYENA_SHIFT) |
319 (otap_del_sel << OTAPDLYSEL_SHIFT);
320 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
322 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
323 sdhci_am654->clkbuf_sel);
325 sdhci_set_clock(host, clock);
328 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
330 writeb(val, host->ioaddr + reg);
331 usleep_range(1000, 10000);
332 return readb(host->ioaddr + reg);
335 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */
336 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
338 unsigned char timing = host->mmc->ios.timing;
342 if (reg == SDHCI_HOST_CONTROL) {
345 * According to the data manual, HISPD bit
346 * should not be set in these speed modes.
348 case MMC_TIMING_SD_HS:
349 case MMC_TIMING_MMC_HS:
350 case MMC_TIMING_UHS_SDR12:
351 case MMC_TIMING_UHS_SDR25:
352 val &= ~SDHCI_CTRL_HISPD;
356 writeb(val, host->ioaddr + reg);
357 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
359 * Power on will not happen until the card detect debounce
360 * timer expires. Wait at least 1.5 seconds for the power on
363 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
364 pwr & SDHCI_POWER_ON, 0,
365 MAX_POWER_ON_TIMEOUT, false, host, val,
368 dev_warn(mmc_dev(host->mmc), "Power on failed\n");
372 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
374 struct sdhci_host *host = mmc_priv(mmc);
375 int err = sdhci_execute_tuning(mmc, opcode);
380 * Tuning data remains in the buffer after tuning.
381 * Do a command and data reset to get rid of it
383 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
388 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
393 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
396 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
402 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
405 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
406 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
407 int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
411 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
412 1 << ITAPDLYENA_SHIFT);
414 for (itap = 0; itap < ITAP_MAX; itap++) {
415 sdhci_am654_write_itapdly(sdhci_am654, itap);
417 cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
418 if (cur_val && !prev_val)
427 * Having determined the length of the failing window and start of
428 * the passing window calculate the length of the passing window and
429 * set the final value halfway through it considering the range as a
432 pass_len = ITAP_MAX - fail_len;
433 itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
434 sdhci_am654_write_itapdly(sdhci_am654, itap);
439 static struct sdhci_ops sdhci_am654_ops = {
440 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
441 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
442 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
443 .set_uhs_signaling = sdhci_set_uhs_signaling,
444 .set_bus_width = sdhci_set_bus_width,
445 .set_power = sdhci_set_power_and_bus_voltage,
446 .set_clock = sdhci_am654_set_clock,
447 .write_b = sdhci_am654_write_b,
448 .irq = sdhci_am654_cqhci_irq,
449 .reset = sdhci_reset,
452 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
453 .ops = &sdhci_am654_ops,
454 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
455 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
458 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
459 .pdata = &sdhci_am654_pdata,
460 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
464 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
465 .pdata = &sdhci_am654_pdata,
466 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
469 static struct sdhci_ops sdhci_j721e_8bit_ops = {
470 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
471 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
472 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
473 .set_uhs_signaling = sdhci_set_uhs_signaling,
474 .set_bus_width = sdhci_set_bus_width,
475 .set_power = sdhci_set_power_and_bus_voltage,
476 .set_clock = sdhci_am654_set_clock,
477 .write_b = sdhci_am654_write_b,
478 .irq = sdhci_am654_cqhci_irq,
479 .reset = sdhci_reset,
482 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
483 .ops = &sdhci_j721e_8bit_ops,
484 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
485 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
488 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
489 .pdata = &sdhci_j721e_8bit_pdata,
490 .flags = DLL_PRESENT | DLL_CALIB,
493 static struct sdhci_ops sdhci_j721e_4bit_ops = {
494 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
495 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
496 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
497 .set_uhs_signaling = sdhci_set_uhs_signaling,
498 .set_bus_width = sdhci_set_bus_width,
499 .set_power = sdhci_set_power_and_bus_voltage,
500 .set_clock = sdhci_j721e_4bit_set_clock,
501 .write_b = sdhci_am654_write_b,
502 .irq = sdhci_am654_cqhci_irq,
503 .reset = sdhci_reset,
506 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
507 .ops = &sdhci_j721e_4bit_ops,
508 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
509 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
512 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
513 .pdata = &sdhci_j721e_4bit_pdata,
514 .flags = IOMUX_PRESENT,
517 static const struct sdhci_pltfm_data sdhci_am64_8bit_pdata = {
518 .ops = &sdhci_j721e_8bit_ops,
519 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
522 static const struct sdhci_am654_driver_data sdhci_am64_8bit_drvdata = {
523 .pdata = &sdhci_am64_8bit_pdata,
524 .flags = DLL_PRESENT | DLL_CALIB,
527 static const struct sdhci_pltfm_data sdhci_am64_4bit_pdata = {
528 .ops = &sdhci_j721e_4bit_ops,
529 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
532 static const struct sdhci_am654_driver_data sdhci_am64_4bit_drvdata = {
533 .pdata = &sdhci_am64_4bit_pdata,
534 .flags = IOMUX_PRESENT,
537 static const struct soc_device_attribute sdhci_am654_devices[] = {
540 .data = &sdhci_am654_sr1_drvdata
545 static void sdhci_am654_dumpregs(struct mmc_host *mmc)
547 sdhci_dumpregs(mmc_priv(mmc));
550 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
551 .enable = sdhci_cqe_enable,
552 .disable = sdhci_cqe_disable,
553 .dumpregs = sdhci_am654_dumpregs,
556 static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
558 struct cqhci_host *cq_host;
561 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
566 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
567 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
568 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
569 cq_host->ops = &sdhci_am654_cqhci_ops;
571 host->mmc->caps2 |= MMC_CAP2_CQE;
573 ret = cqhci_init(cq_host, host->mmc, 1);
578 static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
579 struct sdhci_am654_data *sdhci_am654)
581 struct device *dev = mmc_dev(host->mmc);
585 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding,
586 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
589 * ti,otap-del-sel-legacy is mandatory, look for old binding
592 ret = device_property_read_u32(dev, "ti,otap-del-sel",
593 &sdhci_am654->otap_del_sel[0]);
595 dev_err(dev, "Couldn't find otap-del-sel\n");
600 dev_info(dev, "Using legacy binding ti,otap-del-sel\n");
601 sdhci_am654->legacy_otapdly = true;
606 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) {
608 ret = device_property_read_u32(dev, td[i].otap_binding,
609 &sdhci_am654->otap_del_sel[i]);
611 dev_dbg(dev, "Couldn't find %s\n",
614 * Remove the corresponding capability
615 * if an otap-del-sel value is not found
617 if (i <= MMC_TIMING_MMC_DDR52)
618 host->mmc->caps &= ~td[i].capability;
620 host->mmc->caps2 &= ~td[i].capability;
623 if (td[i].itap_binding)
624 device_property_read_u32(dev, td[i].itap_binding,
625 &sdhci_am654->itap_del_sel[i]);
631 static int sdhci_am654_init(struct sdhci_host *host)
633 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
634 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
640 /* Reset OTAP to default value */
641 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
642 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
644 if (sdhci_am654->flags & DLL_CALIB) {
645 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
646 if (~val & CALDONE_MASK) {
647 /* Calibrate IO lines */
648 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
650 ret = regmap_read_poll_timeout(sdhci_am654->base,
659 /* Enable pins by setting IO mux to 0 */
660 if (sdhci_am654->flags & IOMUX_PRESENT)
661 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
662 IOMUX_ENABLE_MASK, 0);
664 /* Set slot type based on SD or eMMC */
665 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
666 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
668 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
671 /* Enable tuning for SDR50 */
672 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
673 TUNINGFORSDR50_MASK);
675 ret = sdhci_setup_host(host);
679 ret = sdhci_am654_cqe_add_host(host);
681 goto err_cleanup_host;
683 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
685 goto err_cleanup_host;
687 ret = __sdhci_add_host(host);
689 goto err_cleanup_host;
694 sdhci_cleanup_host(host);
698 static int sdhci_am654_get_of_property(struct platform_device *pdev,
699 struct sdhci_am654_data *sdhci_am654)
701 struct device *dev = &pdev->dev;
705 if (sdhci_am654->flags & DLL_PRESENT) {
706 ret = device_property_read_u32(dev, "ti,trm-icp",
707 &sdhci_am654->trm_icp);
711 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
716 switch (drv_strength) {
718 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
721 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
724 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
727 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
730 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
733 dev_err(dev, "Invalid driver strength\n");
738 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
739 device_property_read_u32(dev, "ti,clkbuf-sel",
740 &sdhci_am654->clkbuf_sel);
742 sdhci_get_of_property(pdev);
747 static const struct of_device_id sdhci_am654_of_match[] = {
749 .compatible = "ti,am654-sdhci-5.1",
750 .data = &sdhci_am654_drvdata,
753 .compatible = "ti,j721e-sdhci-8bit",
754 .data = &sdhci_j721e_8bit_drvdata,
757 .compatible = "ti,j721e-sdhci-4bit",
758 .data = &sdhci_j721e_4bit_drvdata,
761 .compatible = "ti,am64-sdhci-8bit",
762 .data = &sdhci_am64_8bit_drvdata,
765 .compatible = "ti,am64-sdhci-4bit",
766 .data = &sdhci_am64_4bit_drvdata,
770 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
772 static int sdhci_am654_probe(struct platform_device *pdev)
774 const struct sdhci_am654_driver_data *drvdata;
775 const struct soc_device_attribute *soc;
776 struct sdhci_pltfm_host *pltfm_host;
777 struct sdhci_am654_data *sdhci_am654;
778 const struct of_device_id *match;
779 struct sdhci_host *host;
781 struct device *dev = &pdev->dev;
785 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
786 drvdata = match->data;
788 /* Update drvdata based on SoC revision */
789 soc = soc_device_match(sdhci_am654_devices);
790 if (soc && soc->data)
793 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
795 return PTR_ERR(host);
797 pltfm_host = sdhci_priv(host);
798 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
799 sdhci_am654->flags = drvdata->flags;
801 clk_xin = devm_clk_get(dev, "clk_xin");
802 if (IS_ERR(clk_xin)) {
803 dev_err(dev, "clk_xin clock not found.\n");
804 ret = PTR_ERR(clk_xin);
808 pltfm_host->clk = clk_xin;
810 /* Clocks are enabled using pm_runtime */
811 pm_runtime_enable(dev);
812 ret = pm_runtime_resume_and_get(dev);
814 goto pm_runtime_disable;
816 base = devm_platform_ioremap_resource(pdev, 1);
822 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
823 &sdhci_am654_regmap_config);
824 if (IS_ERR(sdhci_am654->base)) {
825 dev_err(dev, "Failed to initialize regmap\n");
826 ret = PTR_ERR(sdhci_am654->base);
830 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
834 ret = mmc_of_parse(host->mmc);
836 dev_err(dev, "parsing dt failed (%d)\n", ret);
840 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
842 ret = sdhci_am654_init(host);
849 pm_runtime_put_sync(dev);
851 pm_runtime_disable(dev);
853 sdhci_pltfm_free(pdev);
857 static int sdhci_am654_remove(struct platform_device *pdev)
859 struct sdhci_host *host = platform_get_drvdata(pdev);
862 sdhci_remove_host(host, true);
863 ret = pm_runtime_put_sync(&pdev->dev);
867 pm_runtime_disable(&pdev->dev);
868 sdhci_pltfm_free(pdev);
873 static struct platform_driver sdhci_am654_driver = {
875 .name = "sdhci-am654",
876 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
877 .of_match_table = sdhci_am654_of_match,
879 .probe = sdhci_am654_probe,
880 .remove = sdhci_am654_remove,
883 module_platform_driver(sdhci_am654_driver);
885 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
886 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
887 MODULE_LICENSE("GPL");