1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/property.h>
12 #include <linux/regmap.h>
14 #include "sdhci-pltfm.h"
16 /* CTL_CFG Registers */
17 #define CTL_CFG_2 0x14
19 #define SLOTTYPE_MASK GENMASK(31, 30)
20 #define SLOTTYPE_EMBEDDED BIT(30)
23 #define PHY_CTRL1 0x100
24 #define PHY_CTRL2 0x104
25 #define PHY_CTRL3 0x108
26 #define PHY_CTRL4 0x10C
27 #define PHY_CTRL5 0x110
28 #define PHY_CTRL6 0x114
29 #define PHY_STAT1 0x130
30 #define PHY_STAT2 0x134
32 #define IOMUX_ENABLE_SHIFT 31
33 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
34 #define OTAPDLYENA_SHIFT 20
35 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
36 #define OTAPDLYSEL_SHIFT 12
37 #define OTAPDLYSEL_MASK GENMASK(15, 12)
38 #define STRBSEL_SHIFT 24
39 #define STRBSEL_MASK GENMASK(27, 24)
41 #define SEL50_MASK BIT(SEL50_SHIFT)
42 #define SEL100_SHIFT 9
43 #define SEL100_MASK BIT(SEL100_SHIFT)
44 #define DLL_TRIM_ICP_SHIFT 4
45 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
46 #define DR_TY_SHIFT 20
47 #define DR_TY_MASK GENMASK(22, 20)
49 #define ENDLL_MASK BIT(ENDLL_SHIFT)
50 #define DLLRDY_SHIFT 0
51 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
53 #define PDB_MASK BIT(PDB_SHIFT)
54 #define CALDONE_SHIFT 1
55 #define CALDONE_MASK BIT(CALDONE_SHIFT)
56 #define RETRIM_SHIFT 17
57 #define RETRIM_MASK BIT(RETRIM_SHIFT)
59 #define DRIVER_STRENGTH_50_OHM 0x0
60 #define DRIVER_STRENGTH_33_OHM 0x1
61 #define DRIVER_STRENGTH_66_OHM 0x2
62 #define DRIVER_STRENGTH_100_OHM 0x3
63 #define DRIVER_STRENGTH_40_OHM 0x4
65 #define CLOCK_TOO_SLOW_HZ 400000
67 static struct regmap_config sdhci_am654_regmap_config = {
74 struct sdhci_am654_data {
82 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
84 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
85 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
90 if (sdhci_am654->dll_on) {
91 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
94 sdhci_am654->dll_on = false;
97 sdhci_set_clock(host, clock);
99 if (clock > CLOCK_TOO_SLOW_HZ) {
100 /* Setup DLL Output TAP delay */
101 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
102 val = (1 << OTAPDLYENA_SHIFT) |
103 (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
104 regmap_update_bits(sdhci_am654->base, PHY_CTRL4,
120 /* Configure PHY DLL frequency */
121 mask = SEL50_MASK | SEL100_MASK;
122 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
123 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
125 /* Configure DLL TRIM */
126 mask = DLL_TRIM_ICP_MASK;
127 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
129 /* Configure DLL driver strength */
131 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
132 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
135 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
136 ENDLL_MASK, 0x1 << ENDLL_SHIFT);
138 * Poll for DLL ready. Use a one second timeout.
139 * Works in all experiments done so far
141 ret = regmap_read_poll_timeout(sdhci_am654->base,
146 sdhci_am654->dll_on = true;
150 static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode,
153 if (!IS_ERR(host->mmc->supply.vmmc)) {
154 struct mmc_host *mmc = host->mmc;
156 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
158 sdhci_set_power_noreg(host, mode, vdd);
161 struct sdhci_ops sdhci_am654_ops = {
162 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
163 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
164 .set_uhs_signaling = sdhci_set_uhs_signaling,
165 .set_bus_width = sdhci_set_bus_width,
166 .set_power = sdhci_am654_set_power,
167 .set_clock = sdhci_am654_set_clock,
168 .reset = sdhci_reset,
171 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
172 .ops = &sdhci_am654_ops,
173 .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
174 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
175 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
178 static int sdhci_am654_init(struct sdhci_host *host)
180 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
181 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
187 /* Reset OTAP to default value */
188 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
189 regmap_update_bits(sdhci_am654->base, PHY_CTRL4,
192 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
193 if (~val & CALDONE_MASK) {
194 /* Calibrate IO lines */
195 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
197 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1,
198 val, val & CALDONE_MASK, 1, 20);
203 /* Enable pins by setting IO mux to 0 */
204 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
205 IOMUX_ENABLE_MASK, 0);
207 /* Set slot type based on SD or eMMC */
208 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
209 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
211 regmap_update_bits(sdhci_am654->base, CTL_CFG_2,
212 ctl_cfg_2, SLOTTYPE_MASK);
214 return sdhci_add_host(host);
217 static int sdhci_am654_get_of_property(struct platform_device *pdev,
218 struct sdhci_am654_data *sdhci_am654)
220 struct device *dev = &pdev->dev;
224 ret = device_property_read_u32(dev, "ti,trm-icp",
225 &sdhci_am654->trm_icp);
229 ret = device_property_read_u32(dev, "ti,otap-del-sel",
230 &sdhci_am654->otap_del_sel);
234 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
239 switch (drv_strength) {
241 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
244 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
247 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
250 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
253 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
256 dev_err(dev, "Invalid driver strength\n");
260 sdhci_get_of_property(pdev);
265 static int sdhci_am654_probe(struct platform_device *pdev)
267 struct sdhci_pltfm_host *pltfm_host;
268 struct sdhci_am654_data *sdhci_am654;
269 struct sdhci_host *host;
270 struct resource *res;
272 struct device *dev = &pdev->dev;
276 host = sdhci_pltfm_init(pdev, &sdhci_am654_pdata, sizeof(*sdhci_am654));
278 return PTR_ERR(host);
280 pltfm_host = sdhci_priv(host);
281 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
283 clk_xin = devm_clk_get(dev, "clk_xin");
284 if (IS_ERR(clk_xin)) {
285 dev_err(dev, "clk_xin clock not found.\n");
286 ret = PTR_ERR(clk_xin);
290 pltfm_host->clk = clk_xin;
292 /* Clocks are enabled using pm_runtime */
293 pm_runtime_enable(dev);
294 ret = pm_runtime_get_sync(dev);
296 pm_runtime_put_noidle(dev);
297 goto pm_runtime_disable;
300 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
301 base = devm_ioremap_resource(dev, res);
307 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
308 &sdhci_am654_regmap_config);
309 if (IS_ERR(sdhci_am654->base)) {
310 dev_err(dev, "Failed to initialize regmap\n");
311 ret = PTR_ERR(sdhci_am654->base);
315 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
319 ret = mmc_of_parse(host->mmc);
321 dev_err(dev, "parsing dt failed (%d)\n", ret);
325 ret = sdhci_am654_init(host);
332 pm_runtime_put_sync(dev);
334 pm_runtime_disable(dev);
336 sdhci_pltfm_free(pdev);
340 static int sdhci_am654_remove(struct platform_device *pdev)
342 struct sdhci_host *host = platform_get_drvdata(pdev);
345 sdhci_remove_host(host, true);
346 ret = pm_runtime_put_sync(&pdev->dev);
350 pm_runtime_disable(&pdev->dev);
351 sdhci_pltfm_free(pdev);
356 static const struct of_device_id sdhci_am654_of_match[] = {
357 { .compatible = "ti,am654-sdhci-5.1" },
361 static struct platform_driver sdhci_am654_driver = {
363 .name = "sdhci-am654",
364 .of_match_table = sdhci_am654_of_match,
366 .probe = sdhci_am654_probe,
367 .remove = sdhci_am654_remove,
370 module_platform_driver(sdhci_am654_driver);
372 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
373 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
374 MODULE_LICENSE("GPL");