drivers/mmc/host/sdhci_am654.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
   4  *
   5  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/of.h>
  10 #include <linux/module.h>
  11 #include <linux/pm_runtime.h>
  12 #include <linux/property.h>
  13 #include <linux/regmap.h>
  14
  15 #include "cqhci.h"
  16 #include "sdhci-pltfm.h"
  17
  18 /* CTL_CFG Registers */
  19 #define CTL_CFG_2               0x14
  20
  21 #define SLOTTYPE_MASK           GENMASK(31, 30)
  22 #define SLOTTYPE_EMBEDDED       BIT(30)
  23
  24 /* PHY Registers */
  25 #define PHY_CTRL1       0x100
  26 #define PHY_CTRL2       0x104
  27 #define PHY_CTRL3       0x108
  28 #define PHY_CTRL4       0x10C
  29 #define PHY_CTRL5       0x110
  30 #define PHY_CTRL6       0x114
  31 #define PHY_STAT1       0x130
  32 #define PHY_STAT2       0x134
  33
  34 #define IOMUX_ENABLE_SHIFT      31
  35 #define IOMUX_ENABLE_MASK       BIT(IOMUX_ENABLE_SHIFT)
  36 #define OTAPDLYENA_SHIFT        20
  37 #define OTAPDLYENA_MASK         BIT(OTAPDLYENA_SHIFT)
  38 #define OTAPDLYSEL_SHIFT        12
  39 #define OTAPDLYSEL_MASK         GENMASK(15, 12)
  40 #define STRBSEL_SHIFT           24
  41 #define STRBSEL_4BIT_MASK       GENMASK(27, 24)
  42 #define STRBSEL_8BIT_MASK       GENMASK(31, 24)
  43 #define SEL50_SHIFT             8
  44 #define SEL50_MASK              BIT(SEL50_SHIFT)
  45 #define SEL100_SHIFT            9
  46 #define SEL100_MASK             BIT(SEL100_SHIFT)
  47 #define FREQSEL_SHIFT           8
  48 #define FREQSEL_MASK            GENMASK(10, 8)
  49 #define DLL_TRIM_ICP_SHIFT      4
  50 #define DLL_TRIM_ICP_MASK       GENMASK(7, 4)
  51 #define DR_TY_SHIFT             20
  52 #define DR_TY_MASK              GENMASK(22, 20)
  53 #define ENDLL_SHIFT             1
  54 #define ENDLL_MASK              BIT(ENDLL_SHIFT)
  55 #define DLLRDY_SHIFT            0
  56 #define DLLRDY_MASK             BIT(DLLRDY_SHIFT)
  57 #define PDB_SHIFT               0
  58 #define PDB_MASK                BIT(PDB_SHIFT)
  59 #define CALDONE_SHIFT           1
  60 #define CALDONE_MASK            BIT(CALDONE_SHIFT)
  61 #define RETRIM_SHIFT            17
  62 #define RETRIM_MASK             BIT(RETRIM_SHIFT)
  63
  64 #define DRIVER_STRENGTH_50_OHM  0x0
  65 #define DRIVER_STRENGTH_33_OHM  0x1
  66 #define DRIVER_STRENGTH_66_OHM  0x2
  67 #define DRIVER_STRENGTH_100_OHM 0x3
  68 #define DRIVER_STRENGTH_40_OHM  0x4
  69
  70 #define CLOCK_TOO_SLOW_HZ       400000
  71
  72 /* Command Queue Host Controller Interface Base address */
  73 #define SDHCI_AM654_CQE_BASE_ADDR 0x200
  74
  75 static struct regmap_config sdhci_am654_regmap_config = {
  76         .reg_bits = 32,
  77         .val_bits = 32,
  78         .reg_stride = 4,
  79         .fast_io = true,
  80 };
  81
  82 struct sdhci_am654_data {
  83         struct regmap *base;
  84         bool legacy_otapdly;
  85         int otap_del_sel[11];
  86         int trm_icp;
  87         int drv_strength;
  88         bool dll_on;
  89         int strb_sel;
  90         u32 flags;
  91 };
  92
  93 struct sdhci_am654_driver_data {
  94         const struct sdhci_pltfm_data *pdata;
  95         u32 flags;
  96 #define IOMUX_PRESENT   (1 << 0)
  97 #define FREQSEL_2_BIT   (1 << 1)
  98 #define STRBSEL_4_BIT   (1 << 2)
  99 #define DLL_PRESENT     (1 << 3)
 100 };
 101
 102 struct timing_data {
 103         const char *binding;
 104         u32 capability;
 105 };
 106
 107 static const struct timing_data td[] = {
 108         [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0},
 109         [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED},
 110         [MMC_TIMING_SD_HS]  = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED},
 111         [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12},
 112         [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25},
 113         [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50},
 114         [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
 115                                    MMC_CAP_UHS_SDR104},
 116         [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50},
 117         [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR},
 118         [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200},
 119         [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400},
 120 };
 121
 122 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
 123 {
 124         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 125         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 126         int sel50, sel100, freqsel;
 127         u32 mask, val;
 128         int ret;
 129
 130         if (sdhci_am654->flags & FREQSEL_2_BIT) {
 131                 switch (clock) {
 132                 case 200000000:
 133                         sel50 = 0;
 134                         sel100 = 0;
 135                         break;
 136                 case 100000000:
 137                         sel50 = 0;
 138                         sel100 = 1;
 139                         break;
 140                 default:
 141                         sel50 = 1;
 142                         sel100 = 0;
 143                 }
 144
 145                 /* Configure PHY DLL frequency */
 146                 mask = SEL50_MASK | SEL100_MASK;
 147                 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
 148                 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
 149
 150         } else {
 151                 switch (clock) {
 152                 case 200000000:
 153                         freqsel = 0x0;
 154                         break;
 155                 default:
 156                         freqsel = 0x4;
 157                 }
 158
 159                 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
 160                                    freqsel << FREQSEL_SHIFT);
 161         }
 162         /* Configure DLL TRIM */
 163         mask = DLL_TRIM_ICP_MASK;
 164         val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
 165
 166         /* Configure DLL driver strength */
 167         mask |= DR_TY_MASK;
 168         val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
 169         regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
 170
 171         /* Enable DLL */
 172         regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
 173                            0x1 << ENDLL_SHIFT);
 174         /*
 175          * Poll for DLL ready. Use a one second timeout.
 176          * Works in all experiments done so far
 177          */
 178         ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
 179                                        val & DLLRDY_MASK, 1000, 1000000);
 180         if (ret) {
 181                 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
 182                 return;
 183         }
 184
 185         sdhci_am654->dll_on = true;
 186 }
 187
 188 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
 189 {
 190         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 191         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 192         unsigned char timing = host->mmc->ios.timing;
 193         u32 otap_del_sel;
 194         u32 otap_del_ena;
 195         u32 mask, val;
 196
 197         if (sdhci_am654->dll_on) {
 198                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
 199
 200                 sdhci_am654->dll_on = false;
 201         }
 202
 203         sdhci_set_clock(host, clock);
 204
 205         if (clock > CLOCK_TOO_SLOW_HZ) {
 206                 /* Setup DLL Output TAP delay */
 207                 if (sdhci_am654->legacy_otapdly)
 208                         otap_del_sel = sdhci_am654->otap_del_sel[0];
 209                 else
 210                         otap_del_sel = sdhci_am654->otap_del_sel[timing];
 211
 212                 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
 213
 214                 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 215                 val = (otap_del_ena << OTAPDLYENA_SHIFT) |
 216                       (otap_del_sel << OTAPDLYSEL_SHIFT);
 217
 218                 /* Write to STRBSEL for HS400 speed mode */
 219                 if (timing == MMC_TIMING_MMC_HS400) {
 220                         if (sdhci_am654->flags & STRBSEL_4_BIT)
 221                                 mask |= STRBSEL_4BIT_MASK;
 222                         else
 223                                 mask |= STRBSEL_8BIT_MASK;
 224
 225                         val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
 226                 }
 227
 228                 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
 229
 230                 if (timing > MMC_TIMING_UHS_SDR25)
 231                         sdhci_am654_setup_dll(host, clock);
 232         }
 233 }
 234
 235 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
 236                                        unsigned int clock)
 237 {
 238         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 239         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 240         unsigned char timing = host->mmc->ios.timing;
 241         u32 otap_del_sel;
 242         u32 mask, val;
 243
 244         /* Setup DLL Output TAP delay */
 245         if (sdhci_am654->legacy_otapdly)
 246                 otap_del_sel = sdhci_am654->otap_del_sel[0];
 247         else
 248                 otap_del_sel = sdhci_am654->otap_del_sel[timing];
 249
 250         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 251         val = (0x1 << OTAPDLYENA_SHIFT) |
 252               (otap_del_sel << OTAPDLYSEL_SHIFT);
 253         regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
 254
 255         sdhci_set_clock(host, clock);
 256 }
 257
 258 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
 259 {
 260         unsigned char timing = host->mmc->ios.timing;
 261
 262         if (reg == SDHCI_HOST_CONTROL) {
 263                 switch (timing) {
 264                 /*
 265                  * According to the data manual, HISPD bit
 266                  * should not be set in these speed modes.
 267                  */
 268                 case MMC_TIMING_SD_HS:
 269                 case MMC_TIMING_MMC_HS:
 270                 case MMC_TIMING_UHS_SDR12:
 271                 case MMC_TIMING_UHS_SDR25:
 272                         val &= ~SDHCI_CTRL_HISPD;
 273                 }
 274         }
 275
 276         writeb(val, host->ioaddr + reg);
 277 }
 278
 279 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
 280 {
 281         struct sdhci_host *host = mmc_priv(mmc);
 282         int err = sdhci_execute_tuning(mmc, opcode);
 283
 284         if (err)
 285                 return err;
 286         /*
 287          * Tuning data remains in the buffer after tuning.
 288          * Do a command and data reset to get rid of it
 289          */
 290         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 291
 292         return 0;
 293 }
 294
 295 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
 296 {
 297         int cmd_error = 0;
 298         int data_error = 0;
 299
 300         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
 301                 return intmask;
 302
 303         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
 304
 305         return 0;
 306 }
 307
 308 static struct sdhci_ops sdhci_am654_ops = {
 309         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 310         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 311         .set_uhs_signaling = sdhci_set_uhs_signaling,
 312         .set_bus_width = sdhci_set_bus_width,
 313         .set_power = sdhci_set_power_and_bus_voltage,
 314         .set_clock = sdhci_am654_set_clock,
 315         .write_b = sdhci_am654_write_b,
 316         .irq = sdhci_am654_cqhci_irq,
 317         .reset = sdhci_reset,
 318 };
 319
 320 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
 321         .ops = &sdhci_am654_ops,
 322         .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 323         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 324 };
 325
 326 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
 327         .pdata = &sdhci_am654_pdata,
 328         .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
 329 };
 330
 331 static struct sdhci_ops sdhci_j721e_8bit_ops = {
 332         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 333         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 334         .set_uhs_signaling = sdhci_set_uhs_signaling,
 335         .set_bus_width = sdhci_set_bus_width,
 336         .set_power = sdhci_set_power_and_bus_voltage,
 337         .set_clock = sdhci_am654_set_clock,
 338         .write_b = sdhci_am654_write_b,
 339         .irq = sdhci_am654_cqhci_irq,
 340         .reset = sdhci_reset,
 341 };
 342
 343 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
 344         .ops = &sdhci_j721e_8bit_ops,
 345         .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 346         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 347 };
 348
 349 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
 350         .pdata = &sdhci_j721e_8bit_pdata,
 351         .flags = DLL_PRESENT,
 352 };
 353
 354 static struct sdhci_ops sdhci_j721e_4bit_ops = {
 355         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 356         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 357         .set_uhs_signaling = sdhci_set_uhs_signaling,
 358         .set_bus_width = sdhci_set_bus_width,
 359         .set_power = sdhci_set_power_and_bus_voltage,
 360         .set_clock = sdhci_j721e_4bit_set_clock,
 361         .write_b = sdhci_am654_write_b,
 362         .irq = sdhci_am654_cqhci_irq,
 363         .reset = sdhci_reset,
 364 };
 365
 366 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
 367         .ops = &sdhci_j721e_4bit_ops,
 368         .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 369         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 370 };
 371
 372 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
 373         .pdata = &sdhci_j721e_4bit_pdata,
 374         .flags = IOMUX_PRESENT,
 375 };
 376
 377 static void sdhci_am654_dumpregs(struct mmc_host *mmc)
 378 {
 379         sdhci_dumpregs(mmc_priv(mmc));
 380 }
 381
 382 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
 383         .enable         = sdhci_cqe_enable,
 384         .disable        = sdhci_cqe_disable,
 385         .dumpregs       = sdhci_am654_dumpregs,
 386 };
 387
 388 static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
 389 {
 390         struct cqhci_host *cq_host;
 391         int ret;
 392
 393         cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host),
 394                                GFP_KERNEL);
 395         if (!cq_host)
 396                 return -ENOMEM;
 397
 398         cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
 399         cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
 400         cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
 401         cq_host->ops = &sdhci_am654_cqhci_ops;
 402
 403         host->mmc->caps2 |= MMC_CAP2_CQE;
 404
 405         ret = cqhci_init(cq_host, host->mmc, 1);
 406
 407         return ret;
 408 }
 409
 410 static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
 411                                       struct sdhci_am654_data *sdhci_am654)
 412 {
 413         struct device *dev = mmc_dev(host->mmc);
 414         int i;
 415         int ret;
 416
 417         ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].binding,
 418                                  &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
 419         if (ret) {
 420                 /*
 421                  * ti,otap-del-sel-legacy is mandatory, look for old binding
 422                  * if not found.
 423                  */
 424                 ret = device_property_read_u32(dev, "ti,otap-del-sel",
 425                                                &sdhci_am654->otap_del_sel[0]);
 426                 if (ret) {
 427                         dev_err(dev, "Couldn't find otap-del-sel\n");
 428
 429                         return ret;
 430                 }
 431
 432                 dev_info(dev, "Using legacy binding ti,otap-del-sel\n");
 433                 sdhci_am654->legacy_otapdly = true;
 434
 435                 return 0;
 436         }
 437
 438         for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) {
 439
 440                 ret = device_property_read_u32(dev, td[i].binding,
 441                                                &sdhci_am654->otap_del_sel[i]);
 442                 if (ret) {
 443                         dev_dbg(dev, "Couldn't find %s\n",
 444                                 td[i].binding);
 445                         /*
 446                          * Remove the corresponding capability
 447                          * if an otap-del-sel value is not found
 448                          */
 449                         if (i <= MMC_TIMING_MMC_DDR52)
 450                                 host->mmc->caps &= ~td[i].capability;
 451                         else
 452                                 host->mmc->caps2 &= ~td[i].capability;
 453                 }
 454         }
 455
 456         return 0;
 457 }
 458
 459 static int sdhci_am654_init(struct sdhci_host *host)
 460 {
 461         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 462         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 463         u32 ctl_cfg_2 = 0;
 464         u32 mask;
 465         u32 val;
 466         int ret;
 467
 468         /* Reset OTAP to default value */
 469         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 470         regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
 471
 472         if (sdhci_am654->flags & DLL_PRESENT) {
 473                 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
 474                 if (~val & CALDONE_MASK) {
 475                         /* Calibrate IO lines */
 476                         regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
 477                                            PDB_MASK, PDB_MASK);
 478                         ret = regmap_read_poll_timeout(sdhci_am654->base,
 479                                                        PHY_STAT1, val,
 480                                                        val & CALDONE_MASK,
 481                                                        1, 20);
 482                         if (ret)
 483                                 return ret;
 484                 }
 485         }
 486
 487         /* Enable pins by setting IO mux to 0 */
 488         if (sdhci_am654->flags & IOMUX_PRESENT)
 489                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
 490                                    IOMUX_ENABLE_MASK, 0);
 491
 492         /* Set slot type based on SD or eMMC */
 493         if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
 494                 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
 495
 496         regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
 497                            ctl_cfg_2);
 498
 499         ret = sdhci_setup_host(host);
 500         if (ret)
 501                 return ret;
 502
 503         ret = sdhci_am654_cqe_add_host(host);
 504         if (ret)
 505                 goto err_cleanup_host;
 506
 507         ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
 508         if (ret)
 509                 goto err_cleanup_host;
 510
 511         ret = __sdhci_add_host(host);
 512         if (ret)
 513                 goto err_cleanup_host;
 514
 515         return 0;
 516
 517 err_cleanup_host:
 518         sdhci_cleanup_host(host);
 519         return ret;
 520 }
 521
 522 static int sdhci_am654_get_of_property(struct platform_device *pdev,
 523                                         struct sdhci_am654_data *sdhci_am654)
 524 {
 525         struct device *dev = &pdev->dev;
 526         int drv_strength;
 527         int ret;
 528
 529         if (sdhci_am654->flags & DLL_PRESENT) {
 530                 ret = device_property_read_u32(dev, "ti,trm-icp",
 531                                                &sdhci_am654->trm_icp);
 532                 if (ret)
 533                         return ret;
 534
 535                 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
 536                                                &drv_strength);
 537                 if (ret)
 538                         return ret;
 539
 540                 switch (drv_strength) {
 541                 case 50:
 542                         sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
 543                         break;
 544                 case 33:
 545                         sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
 546                         break;
 547                 case 66:
 548                         sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
 549                         break;
 550                 case 100:
 551                         sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
 552                         break;
 553                 case 40:
 554                         sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
 555                         break;
 556                 default:
 557                         dev_err(dev, "Invalid driver strength\n");
 558                         return -EINVAL;
 559                 }
 560         }
 561
 562         device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
 563
 564         sdhci_get_of_property(pdev);
 565
 566         return 0;
 567 }
 568
 569 static const struct of_device_id sdhci_am654_of_match[] = {
 570         {
 571                 .compatible = "ti,am654-sdhci-5.1",
 572                 .data = &sdhci_am654_drvdata,
 573         },
 574         {
 575                 .compatible = "ti,j721e-sdhci-8bit",
 576                 .data = &sdhci_j721e_8bit_drvdata,
 577         },
 578         {
 579                 .compatible = "ti,j721e-sdhci-4bit",
 580                 .data = &sdhci_j721e_4bit_drvdata,
 581         },
 582         { /* sentinel */ }
 583 };
 584
 585 static int sdhci_am654_probe(struct platform_device *pdev)
 586 {
 587         const struct sdhci_am654_driver_data *drvdata;
 588         struct sdhci_pltfm_host *pltfm_host;
 589         struct sdhci_am654_data *sdhci_am654;
 590         const struct of_device_id *match;
 591         struct sdhci_host *host;
 592         struct clk *clk_xin;
 593         struct device *dev = &pdev->dev;
 594         void __iomem *base;
 595         int ret;
 596
 597         match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
 598         drvdata = match->data;
 599         host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
 600         if (IS_ERR(host))
 601                 return PTR_ERR(host);
 602
 603         pltfm_host = sdhci_priv(host);
 604         sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 605         sdhci_am654->flags = drvdata->flags;
 606
 607         clk_xin = devm_clk_get(dev, "clk_xin");
 608         if (IS_ERR(clk_xin)) {
 609                 dev_err(dev, "clk_xin clock not found.\n");
 610                 ret = PTR_ERR(clk_xin);
 611                 goto err_pltfm_free;
 612         }
 613
 614         pltfm_host->clk = clk_xin;
 615
 616         /* Clocks are enabled using pm_runtime */
 617         pm_runtime_enable(dev);
 618         ret = pm_runtime_get_sync(dev);
 619         if (ret < 0) {
 620                 pm_runtime_put_noidle(dev);
 621                 goto pm_runtime_disable;
 622         }
 623
 624         base = devm_platform_ioremap_resource(pdev, 1);
 625         if (IS_ERR(base)) {
 626                 ret = PTR_ERR(base);
 627                 goto pm_runtime_put;
 628         }
 629
 630         sdhci_am654->base = devm_regmap_init_mmio(dev, base,
 631                                                   &sdhci_am654_regmap_config);
 632         if (IS_ERR(sdhci_am654->base)) {
 633                 dev_err(dev, "Failed to initialize regmap\n");
 634                 ret = PTR_ERR(sdhci_am654->base);
 635                 goto pm_runtime_put;
 636         }
 637
 638         ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
 639         if (ret)
 640                 goto pm_runtime_put;
 641
 642         ret = mmc_of_parse(host->mmc);
 643         if (ret) {
 644                 dev_err(dev, "parsing dt failed (%d)\n", ret);
 645                 goto pm_runtime_put;
 646         }
 647
 648         host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
 649
 650         ret = sdhci_am654_init(host);
 651         if (ret)
 652                 goto pm_runtime_put;
 653
 654         return 0;
 655
 656 pm_runtime_put:
 657         pm_runtime_put_sync(dev);
 658 pm_runtime_disable:
 659         pm_runtime_disable(dev);
 660 err_pltfm_free:
 661         sdhci_pltfm_free(pdev);
 662         return ret;
 663 }
 664
 665 static int sdhci_am654_remove(struct platform_device *pdev)
 666 {
 667         struct sdhci_host *host = platform_get_drvdata(pdev);
 668         int ret;
 669
 670         sdhci_remove_host(host, true);
 671         ret = pm_runtime_put_sync(&pdev->dev);
 672         if (ret < 0)
 673                 return ret;
 674
 675         pm_runtime_disable(&pdev->dev);
 676         sdhci_pltfm_free(pdev);
 677
 678         return 0;
 679 }
 680
 681 static struct platform_driver sdhci_am654_driver = {
 682         .driver = {
 683                 .name = "sdhci-am654",
 684                 .of_match_table = sdhci_am654_of_match,
 685         },
 686         .probe = sdhci_am654_probe,
 687         .remove = sdhci_am654_remove,
 688 };
 689
 690 module_platform_driver(sdhci_am654_driver);
 691
 692 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
 693 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
 694 MODULE_LICENSE("GPL");