2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
35 #define DRIVER_NAME "sdhci"
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
45 #define MAX_TUNING_LOOP 40
47 static unsigned int debug_quirks = 0;
48 static unsigned int debug_quirks2;
50 static void sdhci_finish_data(struct sdhci_host *);
52 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_tuning_timer(unsigned long data);
57 #ifdef CONFIG_PM_RUNTIME
58 static int sdhci_runtime_pm_get(struct sdhci_host *host);
59 static int sdhci_runtime_pm_put(struct sdhci_host *host);
61 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71 static void sdhci_dumpregs(struct sdhci_host *host)
73 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
74 mmc_hostname(host->mmc));
76 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
77 sdhci_readl(host, SDHCI_DMA_ADDRESS),
78 sdhci_readw(host, SDHCI_HOST_VERSION));
79 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
80 sdhci_readw(host, SDHCI_BLOCK_SIZE),
81 sdhci_readw(host, SDHCI_BLOCK_COUNT));
82 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
83 sdhci_readl(host, SDHCI_ARGUMENT),
84 sdhci_readw(host, SDHCI_TRANSFER_MODE));
85 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
86 sdhci_readl(host, SDHCI_PRESENT_STATE),
87 sdhci_readb(host, SDHCI_HOST_CONTROL));
88 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
89 sdhci_readb(host, SDHCI_POWER_CONTROL),
90 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
91 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
92 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
93 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
94 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
95 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
96 sdhci_readl(host, SDHCI_INT_STATUS));
97 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
98 sdhci_readl(host, SDHCI_INT_ENABLE),
99 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
100 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
101 sdhci_readw(host, SDHCI_ACMD12_ERR),
102 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
103 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
104 sdhci_readl(host, SDHCI_CAPABILITIES),
105 sdhci_readl(host, SDHCI_CAPABILITIES_1));
106 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
107 sdhci_readw(host, SDHCI_COMMAND),
108 sdhci_readl(host, SDHCI_MAX_CURRENT));
109 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
110 sdhci_readw(host, SDHCI_HOST_CONTROL2));
112 if (host->flags & SDHCI_USE_ADMA)
113 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
114 readl(host->ioaddr + SDHCI_ADMA_ERROR),
115 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
117 pr_debug(DRIVER_NAME ": ===========================================\n");
120 /*****************************************************************************\
122 * Low level functions *
124 \*****************************************************************************/
126 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
130 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
133 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
134 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
137 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
139 sdhci_clear_set_irqs(host, 0, irqs);
142 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
144 sdhci_clear_set_irqs(host, irqs, 0);
147 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
151 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
152 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
155 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
157 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
160 sdhci_unmask_irqs(host, irqs);
162 sdhci_mask_irqs(host, irqs);
165 static void sdhci_enable_card_detection(struct sdhci_host *host)
167 sdhci_set_card_detection(host, true);
170 static void sdhci_disable_card_detection(struct sdhci_host *host)
172 sdhci_set_card_detection(host, false);
175 static void sdhci_reset(struct sdhci_host *host, u8 mask)
177 unsigned long timeout;
178 u32 uninitialized_var(ier);
180 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
181 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
186 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
187 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
189 if (host->ops->platform_reset_enter)
190 host->ops->platform_reset_enter(host, mask);
192 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
194 if (mask & SDHCI_RESET_ALL)
197 /* Wait max 100 ms */
200 /* hw clears the bit when it's done */
201 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
203 pr_err("%s: Reset 0x%x never completed.\n",
204 mmc_hostname(host->mmc), (int)mask);
205 sdhci_dumpregs(host);
212 if (host->ops->platform_reset_exit)
213 host->ops->platform_reset_exit(host, mask);
215 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
216 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
218 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
219 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
220 host->ops->enable_dma(host);
224 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
226 static void sdhci_init(struct sdhci_host *host, int soft)
229 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
231 sdhci_reset(host, SDHCI_RESET_ALL);
233 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
234 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
235 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
236 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
237 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
240 /* force clock reconfiguration */
242 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 static void sdhci_reinit(struct sdhci_host *host)
250 * Retuning stuffs are affected by different cards inserted and only
251 * applicable to UHS-I cards. So reset these fields to their initial
252 * value when card is removed.
254 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
255 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
257 del_timer_sync(&host->tuning_timer);
258 host->flags &= ~SDHCI_NEEDS_RETUNING;
259 host->mmc->max_blk_count =
260 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
262 sdhci_enable_card_detection(host);
265 static void sdhci_activate_led(struct sdhci_host *host)
269 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
270 ctrl |= SDHCI_CTRL_LED;
271 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
274 static void sdhci_deactivate_led(struct sdhci_host *host)
278 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
279 ctrl &= ~SDHCI_CTRL_LED;
280 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
283 #ifdef SDHCI_USE_LEDS_CLASS
284 static void sdhci_led_control(struct led_classdev *led,
285 enum led_brightness brightness)
287 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
290 spin_lock_irqsave(&host->lock, flags);
292 if (host->runtime_suspended)
295 if (brightness == LED_OFF)
296 sdhci_deactivate_led(host);
298 sdhci_activate_led(host);
300 spin_unlock_irqrestore(&host->lock, flags);
304 /*****************************************************************************\
308 \*****************************************************************************/
310 static void sdhci_read_block_pio(struct sdhci_host *host)
313 size_t blksize, len, chunk;
314 u32 uninitialized_var(scratch);
317 DBG("PIO reading\n");
319 blksize = host->data->blksz;
322 local_irq_save(flags);
325 if (!sg_miter_next(&host->sg_miter))
328 len = min(host->sg_miter.length, blksize);
331 host->sg_miter.consumed = len;
333 buf = host->sg_miter.addr;
337 scratch = sdhci_readl(host, SDHCI_BUFFER);
341 *buf = scratch & 0xFF;
350 sg_miter_stop(&host->sg_miter);
352 local_irq_restore(flags);
355 static void sdhci_write_block_pio(struct sdhci_host *host)
358 size_t blksize, len, chunk;
362 DBG("PIO writing\n");
364 blksize = host->data->blksz;
368 local_irq_save(flags);
371 if (!sg_miter_next(&host->sg_miter))
374 len = min(host->sg_miter.length, blksize);
377 host->sg_miter.consumed = len;
379 buf = host->sg_miter.addr;
382 scratch |= (u32)*buf << (chunk * 8);
388 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
389 sdhci_writel(host, scratch, SDHCI_BUFFER);
396 sg_miter_stop(&host->sg_miter);
398 local_irq_restore(flags);
401 static void sdhci_transfer_pio(struct sdhci_host *host)
407 if (host->blocks == 0)
410 if (host->data->flags & MMC_DATA_READ)
411 mask = SDHCI_DATA_AVAILABLE;
413 mask = SDHCI_SPACE_AVAILABLE;
416 * Some controllers (JMicron JMB38x) mess up the buffer bits
417 * for transfers < 4 bytes. As long as it is just one block,
418 * we can ignore the bits.
420 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
421 (host->data->blocks == 1))
424 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
425 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
428 if (host->data->flags & MMC_DATA_READ)
429 sdhci_read_block_pio(host);
431 sdhci_write_block_pio(host);
434 if (host->blocks == 0)
438 DBG("PIO transfer complete.\n");
441 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
443 local_irq_save(*flags);
444 return kmap_atomic(sg_page(sg)) + sg->offset;
447 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
449 kunmap_atomic(buffer);
450 local_irq_restore(*flags);
453 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
455 __le32 *dataddr = (__le32 __force *)(desc + 4);
456 __le16 *cmdlen = (__le16 __force *)desc;
458 /* SDHCI specification says ADMA descriptors should be 4 byte
459 * aligned, so using 16 or 32bit operations should be safe. */
461 cmdlen[0] = cpu_to_le16(cmd);
462 cmdlen[1] = cpu_to_le16(len);
464 dataddr[0] = cpu_to_le32(addr);
467 static int sdhci_adma_table_pre(struct sdhci_host *host,
468 struct mmc_data *data)
475 dma_addr_t align_addr;
478 struct scatterlist *sg;
484 * The spec does not specify endianness of descriptor table.
485 * We currently guess that it is LE.
488 if (data->flags & MMC_DATA_READ)
489 direction = DMA_FROM_DEVICE;
491 direction = DMA_TO_DEVICE;
494 * The ADMA descriptor table is mapped further down as we
495 * need to fill it with data first.
498 host->align_addr = dma_map_single(mmc_dev(host->mmc),
499 host->align_buffer, 128 * 4, direction);
500 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
502 BUG_ON(host->align_addr & 0x3);
504 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
505 data->sg, data->sg_len, direction);
506 if (host->sg_count == 0)
509 desc = host->adma_desc;
510 align = host->align_buffer;
512 align_addr = host->align_addr;
514 for_each_sg(data->sg, sg, host->sg_count, i) {
515 addr = sg_dma_address(sg);
516 len = sg_dma_len(sg);
519 * The SDHCI specification states that ADMA
520 * addresses must be 32-bit aligned. If they
521 * aren't, then we use a bounce buffer for
522 * the (up to three) bytes that screw up the
525 offset = (4 - (addr & 0x3)) & 0x3;
527 if (data->flags & MMC_DATA_WRITE) {
528 buffer = sdhci_kmap_atomic(sg, &flags);
529 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
530 memcpy(align, buffer, offset);
531 sdhci_kunmap_atomic(buffer, &flags);
535 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
537 BUG_ON(offset > 65536);
551 sdhci_set_adma_desc(desc, addr, len, 0x21);
555 * If this triggers then we have a calculation bug
558 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
561 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
563 * Mark the last descriptor as the terminating descriptor
565 if (desc != host->adma_desc) {
567 desc[0] |= 0x2; /* end */
571 * Add a terminating entry.
574 /* nop, end, valid */
575 sdhci_set_adma_desc(desc, 0, 0, 0x3);
579 * Resync align buffer as we might have changed it.
581 if (data->flags & MMC_DATA_WRITE) {
582 dma_sync_single_for_device(mmc_dev(host->mmc),
583 host->align_addr, 128 * 4, direction);
586 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
587 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
588 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
590 BUG_ON(host->adma_addr & 0x3);
595 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
596 data->sg_len, direction);
598 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
604 static void sdhci_adma_table_post(struct sdhci_host *host,
605 struct mmc_data *data)
609 struct scatterlist *sg;
615 if (data->flags & MMC_DATA_READ)
616 direction = DMA_FROM_DEVICE;
618 direction = DMA_TO_DEVICE;
620 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
621 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
623 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
626 if (data->flags & MMC_DATA_READ) {
627 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
628 data->sg_len, direction);
630 align = host->align_buffer;
632 for_each_sg(data->sg, sg, host->sg_count, i) {
633 if (sg_dma_address(sg) & 0x3) {
634 size = 4 - (sg_dma_address(sg) & 0x3);
636 buffer = sdhci_kmap_atomic(sg, &flags);
637 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
638 memcpy(buffer, align, size);
639 sdhci_kunmap_atomic(buffer, &flags);
646 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
647 data->sg_len, direction);
650 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
653 struct mmc_data *data = cmd->data;
654 unsigned target_timeout, current_timeout;
657 * If the host controller provides us with an incorrect timeout
658 * value, just skip the check and use 0xE. The hardware may take
659 * longer to time out, but that's much better than having a too-short
662 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
665 /* Unspecified timeout, assume max */
666 if (!data && !cmd->cmd_timeout_ms)
671 target_timeout = cmd->cmd_timeout_ms * 1000;
673 target_timeout = data->timeout_ns / 1000;
675 target_timeout += data->timeout_clks / host->clock;
679 * Figure out needed cycles.
680 * We do this in steps in order to fit inside a 32 bit int.
681 * The first step is the minimum timeout, which will have a
682 * minimum resolution of 6 bits:
683 * (1) 2^13*1000 > 2^22,
684 * (2) host->timeout_clk < 2^16
689 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
690 while (current_timeout < target_timeout) {
692 current_timeout <<= 1;
698 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
699 mmc_hostname(host->mmc), count, cmd->opcode);
706 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
708 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
709 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
711 if (host->flags & SDHCI_REQ_USE_DMA)
712 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
714 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
717 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
721 struct mmc_data *data = cmd->data;
726 if (data || (cmd->flags & MMC_RSP_BUSY)) {
727 count = sdhci_calc_timeout(host, cmd);
728 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
735 BUG_ON(data->blksz * data->blocks > 524288);
736 BUG_ON(data->blksz > host->mmc->max_blk_size);
737 BUG_ON(data->blocks > 65535);
740 host->data_early = 0;
741 host->data->bytes_xfered = 0;
743 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
744 host->flags |= SDHCI_REQ_USE_DMA;
747 * FIXME: This doesn't account for merging when mapping the
750 if (host->flags & SDHCI_REQ_USE_DMA) {
752 struct scatterlist *sg;
755 if (host->flags & SDHCI_USE_ADMA) {
756 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
759 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
763 if (unlikely(broken)) {
764 for_each_sg(data->sg, sg, data->sg_len, i) {
765 if (sg->length & 0x3) {
766 DBG("Reverting to PIO because of "
767 "transfer size (%d)\n",
769 host->flags &= ~SDHCI_REQ_USE_DMA;
777 * The assumption here being that alignment is the same after
778 * translation to device address space.
780 if (host->flags & SDHCI_REQ_USE_DMA) {
782 struct scatterlist *sg;
785 if (host->flags & SDHCI_USE_ADMA) {
787 * As we use 3 byte chunks to work around
788 * alignment problems, we need to check this
791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
794 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
798 if (unlikely(broken)) {
799 for_each_sg(data->sg, sg, data->sg_len, i) {
800 if (sg->offset & 0x3) {
801 DBG("Reverting to PIO because of "
803 host->flags &= ~SDHCI_REQ_USE_DMA;
810 if (host->flags & SDHCI_REQ_USE_DMA) {
811 if (host->flags & SDHCI_USE_ADMA) {
812 ret = sdhci_adma_table_pre(host, data);
815 * This only happens when someone fed
816 * us an invalid request.
819 host->flags &= ~SDHCI_REQ_USE_DMA;
821 sdhci_writel(host, host->adma_addr,
827 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
828 data->sg, data->sg_len,
829 (data->flags & MMC_DATA_READ) ?
834 * This only happens when someone fed
835 * us an invalid request.
838 host->flags &= ~SDHCI_REQ_USE_DMA;
840 WARN_ON(sg_cnt != 1);
841 sdhci_writel(host, sg_dma_address(data->sg),
848 * Always adjust the DMA selection as some controllers
849 * (e.g. JMicron) can't do PIO properly when the selection
852 if (host->version >= SDHCI_SPEC_200) {
853 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
854 ctrl &= ~SDHCI_CTRL_DMA_MASK;
855 if ((host->flags & SDHCI_REQ_USE_DMA) &&
856 (host->flags & SDHCI_USE_ADMA))
857 ctrl |= SDHCI_CTRL_ADMA32;
859 ctrl |= SDHCI_CTRL_SDMA;
860 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
863 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
866 flags = SG_MITER_ATOMIC;
867 if (host->data->flags & MMC_DATA_READ)
868 flags |= SG_MITER_TO_SG;
870 flags |= SG_MITER_FROM_SG;
871 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
872 host->blocks = data->blocks;
875 sdhci_set_transfer_irqs(host);
877 /* Set the DMA boundary value and block size */
878 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
879 data->blksz), SDHCI_BLOCK_SIZE);
880 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
883 static void sdhci_set_transfer_mode(struct sdhci_host *host,
884 struct mmc_command *cmd)
887 struct mmc_data *data = cmd->data;
892 WARN_ON(!host->data);
894 mode = SDHCI_TRNS_BLK_CNT_EN;
895 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
896 mode |= SDHCI_TRNS_MULTI;
898 * If we are sending CMD23, CMD12 never gets sent
899 * on successful completion (so no Auto-CMD12).
901 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
902 mode |= SDHCI_TRNS_AUTO_CMD12;
903 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
904 mode |= SDHCI_TRNS_AUTO_CMD23;
905 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
909 if (data->flags & MMC_DATA_READ)
910 mode |= SDHCI_TRNS_READ;
911 if (host->flags & SDHCI_REQ_USE_DMA)
912 mode |= SDHCI_TRNS_DMA;
914 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
917 static void sdhci_finish_data(struct sdhci_host *host)
919 struct mmc_data *data;
926 if (host->flags & SDHCI_REQ_USE_DMA) {
927 if (host->flags & SDHCI_USE_ADMA)
928 sdhci_adma_table_post(host, data);
930 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
931 data->sg_len, (data->flags & MMC_DATA_READ) ?
932 DMA_FROM_DEVICE : DMA_TO_DEVICE);
937 * The specification states that the block count register must
938 * be updated, but it does not specify at what point in the
939 * data flow. That makes the register entirely useless to read
940 * back so we have to assume that nothing made it to the card
941 * in the event of an error.
944 data->bytes_xfered = 0;
946 data->bytes_xfered = data->blksz * data->blocks;
949 * Need to send CMD12 if -
950 * a) open-ended multiblock transfer (no CMD23)
951 * b) error in multiblock transfer
958 * The controller needs a reset of internal state machines
959 * upon error conditions.
962 sdhci_reset(host, SDHCI_RESET_CMD);
963 sdhci_reset(host, SDHCI_RESET_DATA);
966 sdhci_send_command(host, data->stop);
968 tasklet_schedule(&host->finish_tasklet);
971 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
975 unsigned long timeout;
982 mask = SDHCI_CMD_INHIBIT;
983 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
984 mask |= SDHCI_DATA_INHIBIT;
986 /* We shouldn't wait for data inihibit for stop commands, even
987 though they might use busy signaling */
988 if (host->mrq->data && (cmd == host->mrq->data->stop))
989 mask &= ~SDHCI_DATA_INHIBIT;
991 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
993 pr_err("%s: Controller never released "
994 "inhibit bit(s).\n", mmc_hostname(host->mmc));
995 sdhci_dumpregs(host);
997 tasklet_schedule(&host->finish_tasklet);
1004 mod_timer(&host->timer, jiffies + 10 * HZ);
1008 sdhci_prepare_data(host, cmd);
1010 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1012 sdhci_set_transfer_mode(host, cmd);
1014 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1015 pr_err("%s: Unsupported response type!\n",
1016 mmc_hostname(host->mmc));
1017 cmd->error = -EINVAL;
1018 tasklet_schedule(&host->finish_tasklet);
1022 if (!(cmd->flags & MMC_RSP_PRESENT))
1023 flags = SDHCI_CMD_RESP_NONE;
1024 else if (cmd->flags & MMC_RSP_136)
1025 flags = SDHCI_CMD_RESP_LONG;
1026 else if (cmd->flags & MMC_RSP_BUSY)
1027 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1029 flags = SDHCI_CMD_RESP_SHORT;
1031 if (cmd->flags & MMC_RSP_CRC)
1032 flags |= SDHCI_CMD_CRC;
1033 if (cmd->flags & MMC_RSP_OPCODE)
1034 flags |= SDHCI_CMD_INDEX;
1036 /* CMD19 is special in that the Data Present Select should be set */
1037 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1038 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1039 flags |= SDHCI_CMD_DATA;
1041 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1044 static void sdhci_finish_command(struct sdhci_host *host)
1048 BUG_ON(host->cmd == NULL);
1050 if (host->cmd->flags & MMC_RSP_PRESENT) {
1051 if (host->cmd->flags & MMC_RSP_136) {
1052 /* CRC is stripped so we need to do some shifting. */
1053 for (i = 0;i < 4;i++) {
1054 host->cmd->resp[i] = sdhci_readl(host,
1055 SDHCI_RESPONSE + (3-i)*4) << 8;
1057 host->cmd->resp[i] |=
1059 SDHCI_RESPONSE + (3-i)*4-1);
1062 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1066 host->cmd->error = 0;
1068 /* Finished CMD23, now send actual command. */
1069 if (host->cmd == host->mrq->sbc) {
1071 sdhci_send_command(host, host->mrq->cmd);
1074 /* Processed actual command. */
1075 if (host->data && host->data_early)
1076 sdhci_finish_data(host);
1078 if (!host->cmd->data)
1079 tasklet_schedule(&host->finish_tasklet);
1085 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1087 int div = 0; /* Initialized for compiler warning */
1088 int real_div = div, clk_mul = 1;
1090 unsigned long timeout;
1092 if (clock && clock == host->clock)
1095 host->mmc->actual_clock = 0;
1097 if (host->ops->set_clock) {
1098 host->ops->set_clock(host, clock);
1099 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1103 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1108 if (host->version >= SDHCI_SPEC_300) {
1110 * Check if the Host Controller supports Programmable Clock
1113 if (host->clk_mul) {
1117 * We need to figure out whether the Host Driver needs
1118 * to select Programmable Clock Mode, or the value can
1119 * be set automatically by the Host Controller based on
1120 * the Preset Value registers.
1122 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1123 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1124 for (div = 1; div <= 1024; div++) {
1125 if (((host->max_clk * host->clk_mul) /
1130 * Set Programmable Clock Mode in the Clock
1133 clk = SDHCI_PROG_CLOCK_MODE;
1135 clk_mul = host->clk_mul;
1139 /* Version 3.00 divisors must be a multiple of 2. */
1140 if (host->max_clk <= clock)
1143 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1145 if ((host->max_clk / div) <= clock)
1153 /* Version 2.00 divisors must be a power of 2. */
1154 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1155 if ((host->max_clk / div) <= clock)
1163 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1165 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1166 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1167 << SDHCI_DIVIDER_HI_SHIFT;
1168 clk |= SDHCI_CLOCK_INT_EN;
1169 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1171 /* Wait max 20 ms */
1173 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1174 & SDHCI_CLOCK_INT_STABLE)) {
1176 pr_err("%s: Internal clock never "
1177 "stabilised.\n", mmc_hostname(host->mmc));
1178 sdhci_dumpregs(host);
1185 clk |= SDHCI_CLOCK_CARD_EN;
1186 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1189 host->clock = clock;
1192 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1196 if (power != (unsigned short)-1) {
1197 switch (1 << power) {
1198 case MMC_VDD_165_195:
1199 pwr = SDHCI_POWER_180;
1203 pwr = SDHCI_POWER_300;
1207 pwr = SDHCI_POWER_330;
1214 if (host->pwr == pwr)
1220 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1225 * Spec says that we should clear the power reg before setting
1226 * a new value. Some controllers don't seem to like this though.
1228 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1229 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1232 * At least the Marvell CaFe chip gets confused if we set the voltage
1233 * and set turn on power at the same time, so set the voltage first.
1235 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1236 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1238 pwr |= SDHCI_POWER_ON;
1240 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1243 * Some controllers need an extra 10ms delay of 10ms before they
1244 * can apply clock after applying power
1246 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1252 /*****************************************************************************\
1256 \*****************************************************************************/
1258 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1260 struct sdhci_host *host;
1262 unsigned long flags;
1265 host = mmc_priv(mmc);
1267 sdhci_runtime_pm_get(host);
1269 spin_lock_irqsave(&host->lock, flags);
1271 WARN_ON(host->mrq != NULL);
1273 #ifndef SDHCI_USE_LEDS_CLASS
1274 sdhci_activate_led(host);
1278 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1279 * requests if Auto-CMD12 is enabled.
1281 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1283 mrq->data->stop = NULL;
1290 /* If polling, assume that the card is always present. */
1291 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1294 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1297 /* If we're using a cd-gpio, testing the presence bit might fail. */
1299 int ret = mmc_gpio_get_cd(host->mmc);
1304 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1305 host->mrq->cmd->error = -ENOMEDIUM;
1306 tasklet_schedule(&host->finish_tasklet);
1310 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1312 * Check if the re-tuning timer has already expired and there
1313 * is no on-going data transfer. If so, we need to execute
1314 * tuning procedure before sending command.
1316 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1317 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1318 /* eMMC uses cmd21 while sd and sdio use cmd19 */
1319 tuning_opcode = mmc->card->type == MMC_TYPE_MMC ?
1320 MMC_SEND_TUNING_BLOCK_HS200 :
1321 MMC_SEND_TUNING_BLOCK;
1322 spin_unlock_irqrestore(&host->lock, flags);
1323 sdhci_execute_tuning(mmc, tuning_opcode);
1324 spin_lock_irqsave(&host->lock, flags);
1326 /* Restore original mmc_request structure */
1330 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1331 sdhci_send_command(host, mrq->sbc);
1333 sdhci_send_command(host, mrq->cmd);
1337 spin_unlock_irqrestore(&host->lock, flags);
1340 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1342 unsigned long flags;
1346 spin_lock_irqsave(&host->lock, flags);
1348 if (host->flags & SDHCI_DEVICE_DEAD) {
1349 spin_unlock_irqrestore(&host->lock, flags);
1350 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1351 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1356 * Reset the chip on each power off.
1357 * Should clear out any weird states.
1359 if (ios->power_mode == MMC_POWER_OFF) {
1360 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1364 sdhci_set_clock(host, ios->clock);
1366 if (ios->power_mode == MMC_POWER_OFF)
1367 vdd_bit = sdhci_set_power(host, -1);
1369 vdd_bit = sdhci_set_power(host, ios->vdd);
1371 if (host->vmmc && vdd_bit != -1) {
1372 spin_unlock_irqrestore(&host->lock, flags);
1373 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1374 spin_lock_irqsave(&host->lock, flags);
1377 if (host->ops->platform_send_init_74_clocks)
1378 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1381 * If your platform has 8-bit width support but is not a v3 controller,
1382 * or if it requires special setup code, you should implement that in
1383 * platform_8bit_width().
1385 if (host->ops->platform_8bit_width)
1386 host->ops->platform_8bit_width(host, ios->bus_width);
1388 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1389 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1390 ctrl &= ~SDHCI_CTRL_4BITBUS;
1391 if (host->version >= SDHCI_SPEC_300)
1392 ctrl |= SDHCI_CTRL_8BITBUS;
1394 if (host->version >= SDHCI_SPEC_300)
1395 ctrl &= ~SDHCI_CTRL_8BITBUS;
1396 if (ios->bus_width == MMC_BUS_WIDTH_4)
1397 ctrl |= SDHCI_CTRL_4BITBUS;
1399 ctrl &= ~SDHCI_CTRL_4BITBUS;
1401 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1404 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1406 if ((ios->timing == MMC_TIMING_SD_HS ||
1407 ios->timing == MMC_TIMING_MMC_HS)
1408 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1409 ctrl |= SDHCI_CTRL_HISPD;
1411 ctrl &= ~SDHCI_CTRL_HISPD;
1413 if (host->version >= SDHCI_SPEC_300) {
1417 /* In case of UHS-I modes, set High Speed Enable */
1418 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1419 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1420 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1421 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1422 (ios->timing == MMC_TIMING_UHS_SDR25))
1423 ctrl |= SDHCI_CTRL_HISPD;
1425 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1426 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1427 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1429 * We only need to set Driver Strength if the
1430 * preset value enable is not set.
1432 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1433 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1434 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1435 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1436 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1438 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1441 * According to SDHC Spec v3.00, if the Preset Value
1442 * Enable in the Host Control 2 register is set, we
1443 * need to reset SD Clock Enable before changing High
1444 * Speed Enable to avoid generating clock gliches.
1447 /* Reset SD Clock Enable */
1448 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1449 clk &= ~SDHCI_CLOCK_CARD_EN;
1450 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1452 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1454 /* Re-enable SD Clock */
1455 clock = host->clock;
1457 sdhci_set_clock(host, clock);
1461 /* Reset SD Clock Enable */
1462 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1463 clk &= ~SDHCI_CLOCK_CARD_EN;
1464 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1466 if (host->ops->set_uhs_signaling)
1467 host->ops->set_uhs_signaling(host, ios->timing);
1469 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1470 /* Select Bus Speed Mode for host */
1471 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1472 if (ios->timing == MMC_TIMING_MMC_HS200)
1473 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1474 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1475 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1476 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1477 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1478 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1479 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1480 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1481 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1482 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1483 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1484 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1487 /* Re-enable SD Clock */
1488 clock = host->clock;
1490 sdhci_set_clock(host, clock);
1492 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1495 * Some (ENE) controllers go apeshit on some ios operation,
1496 * signalling timeout and CRC errors even on CMD0. Resetting
1497 * it on each ios seems to solve the problem.
1499 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1500 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1503 spin_unlock_irqrestore(&host->lock, flags);
1506 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1508 struct sdhci_host *host = mmc_priv(mmc);
1510 sdhci_runtime_pm_get(host);
1511 sdhci_do_set_ios(host, ios);
1512 sdhci_runtime_pm_put(host);
1515 static int sdhci_check_ro(struct sdhci_host *host)
1517 unsigned long flags;
1520 spin_lock_irqsave(&host->lock, flags);
1522 if (host->flags & SDHCI_DEVICE_DEAD)
1524 else if (host->ops->get_ro)
1525 is_readonly = host->ops->get_ro(host);
1527 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1528 & SDHCI_WRITE_PROTECT);
1530 spin_unlock_irqrestore(&host->lock, flags);
1532 /* This quirk needs to be replaced by a callback-function later */
1533 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1534 !is_readonly : is_readonly;
1537 #define SAMPLE_COUNT 5
1539 static int sdhci_do_get_ro(struct sdhci_host *host)
1543 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1544 return sdhci_check_ro(host);
1547 for (i = 0; i < SAMPLE_COUNT; i++) {
1548 if (sdhci_check_ro(host)) {
1549 if (++ro_count > SAMPLE_COUNT / 2)
1557 static void sdhci_hw_reset(struct mmc_host *mmc)
1559 struct sdhci_host *host = mmc_priv(mmc);
1561 if (host->ops && host->ops->hw_reset)
1562 host->ops->hw_reset(host);
1565 static int sdhci_get_ro(struct mmc_host *mmc)
1567 struct sdhci_host *host = mmc_priv(mmc);
1570 sdhci_runtime_pm_get(host);
1571 ret = sdhci_do_get_ro(host);
1572 sdhci_runtime_pm_put(host);
1576 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1578 if (host->flags & SDHCI_DEVICE_DEAD)
1582 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1584 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1586 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1587 if (host->runtime_suspended)
1591 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1593 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1598 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1600 struct sdhci_host *host = mmc_priv(mmc);
1601 unsigned long flags;
1603 spin_lock_irqsave(&host->lock, flags);
1604 sdhci_enable_sdio_irq_nolock(host, enable);
1605 spin_unlock_irqrestore(&host->lock, flags);
1608 static int sdhci_do_3_3v_signal_voltage_switch(struct sdhci_host *host,
1613 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1614 ctrl &= ~SDHCI_CTRL_VDD_180;
1615 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1618 ret = regulator_set_voltage(host->vqmmc, 3300000, 3300000);
1620 pr_warning("%s: Switching to 3.3V signalling voltage "
1621 " failed\n", mmc_hostname(host->mmc));
1626 usleep_range(5000, 5500);
1628 /* 3.3V regulator output should be stable within 5 ms */
1629 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1630 if (!(ctrl & SDHCI_CTRL_VDD_180))
1633 pr_warning("%s: 3.3V regulator output did not became stable\n",
1634 mmc_hostname(host->mmc));
1639 static int sdhci_do_1_8v_signal_voltage_switch(struct sdhci_host *host,
1648 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1649 clk &= ~SDHCI_CLOCK_CARD_EN;
1650 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1652 /* Check whether DAT[3:0] is 0000 */
1653 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1654 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1655 SDHCI_DATA_LVL_SHIFT)) {
1657 * Enable 1.8V Signal Enable in the Host Control2
1661 ret = regulator_set_voltage(host->vqmmc,
1667 ctrl |= SDHCI_CTRL_VDD_180;
1668 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1671 usleep_range(5000, 5500);
1673 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1674 if (ctrl & SDHCI_CTRL_VDD_180) {
1675 /* Provide SDCLK again and wait for 1ms */
1676 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1677 clk |= SDHCI_CLOCK_CARD_EN;
1678 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1679 usleep_range(1000, 1500);
1682 * If DAT[3:0] level is 1111b, then the card
1683 * was successfully switched to 1.8V signaling.
1685 present_state = sdhci_readl(host,
1686 SDHCI_PRESENT_STATE);
1687 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1688 SDHCI_DATA_LVL_MASK)
1695 * If we are here, that means the switch to 1.8V signaling
1696 * failed. We power cycle the card, and retry initialization
1697 * sequence by setting S18R to 0.
1699 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1700 pwr &= ~SDHCI_POWER_ON;
1701 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1703 regulator_disable(host->vmmc);
1705 /* Wait for 1ms as per the spec */
1706 usleep_range(1000, 1500);
1707 pwr |= SDHCI_POWER_ON;
1708 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1710 regulator_enable(host->vmmc);
1712 pr_warning("%s: Switching to 1.8V signalling voltage failed, "
1713 "retrying with S18R set to 0\n", mmc_hostname(host->mmc));
1718 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1719 struct mmc_ios *ios)
1724 * Signal Voltage Switching is only applicable for Host Controllers
1727 if (host->version < SDHCI_SPEC_300)
1731 * We first check whether the request is to set signalling voltage
1732 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1734 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1735 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1736 return sdhci_do_3_3v_signal_voltage_switch(host, ctrl);
1737 else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1738 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180))
1739 return sdhci_do_1_8v_signal_voltage_switch(host, ctrl);
1741 /* No signal voltage switch required */
1745 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1746 struct mmc_ios *ios)
1748 struct sdhci_host *host = mmc_priv(mmc);
1751 if (host->version < SDHCI_SPEC_300)
1753 sdhci_runtime_pm_get(host);
1754 err = sdhci_do_start_signal_voltage_switch(host, ios);
1755 sdhci_runtime_pm_put(host);
1759 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1761 struct sdhci_host *host;
1764 int tuning_loop_counter = MAX_TUNING_LOOP;
1765 unsigned long timeout;
1767 bool requires_tuning_nonuhs = false;
1769 host = mmc_priv(mmc);
1771 sdhci_runtime_pm_get(host);
1772 disable_irq(host->irq);
1773 spin_lock(&host->lock);
1775 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1778 * The Host Controller needs tuning only in case of SDR104 mode
1779 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1780 * Capabilities register.
1781 * If the Host Controller supports the HS200 mode then the
1782 * tuning function has to be executed.
1784 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1785 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1786 host->flags & SDHCI_HS200_NEEDS_TUNING))
1787 requires_tuning_nonuhs = true;
1789 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1790 requires_tuning_nonuhs)
1791 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1793 spin_unlock(&host->lock);
1794 enable_irq(host->irq);
1795 sdhci_runtime_pm_put(host);
1799 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1802 * As per the Host Controller spec v3.00, tuning command
1803 * generates Buffer Read Ready interrupt, so enable that.
1805 * Note: The spec clearly says that when tuning sequence
1806 * is being performed, the controller does not generate
1807 * interrupts other than Buffer Read Ready interrupt. But
1808 * to make sure we don't hit a controller bug, we _only_
1809 * enable Buffer Read Ready interrupt here.
1811 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1812 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1815 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1816 * of loops reaches 40 times or a timeout of 150ms occurs.
1820 struct mmc_command cmd = {0};
1821 struct mmc_request mrq = {NULL};
1823 if (!tuning_loop_counter && !timeout)
1826 cmd.opcode = opcode;
1828 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1837 * In response to CMD19, the card sends 64 bytes of tuning
1838 * block to the Host Controller. So we set the block size
1841 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1842 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1843 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1845 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1846 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1849 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1854 * The tuning block is sent by the card to the host controller.
1855 * So we set the TRNS_READ bit in the Transfer Mode register.
1856 * This also takes care of setting DMA Enable and Multi Block
1857 * Select in the same register to 0.
1859 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1861 sdhci_send_command(host, &cmd);
1866 spin_unlock(&host->lock);
1867 enable_irq(host->irq);
1869 /* Wait for Buffer Read Ready interrupt */
1870 wait_event_interruptible_timeout(host->buf_ready_int,
1871 (host->tuning_done == 1),
1872 msecs_to_jiffies(50));
1873 disable_irq(host->irq);
1874 spin_lock(&host->lock);
1876 if (!host->tuning_done) {
1877 pr_info(DRIVER_NAME ": Timeout waiting for "
1878 "Buffer Read Ready interrupt during tuning "
1879 "procedure, falling back to fixed sampling "
1881 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1882 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1883 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1884 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1890 host->tuning_done = 0;
1892 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1893 tuning_loop_counter--;
1896 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1899 * The Host Driver has exhausted the maximum number of loops allowed,
1900 * so use fixed sampling frequency.
1902 if (!tuning_loop_counter || !timeout) {
1903 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1904 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1906 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1907 pr_info(DRIVER_NAME ": Tuning procedure"
1908 " failed, falling back to fixed sampling"
1916 * If this is the very first time we are here, we start the retuning
1917 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1918 * flag won't be set, we check this condition before actually starting
1921 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1922 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1923 host->flags |= SDHCI_USING_RETUNING_TIMER;
1924 mod_timer(&host->tuning_timer, jiffies +
1925 host->tuning_count * HZ);
1926 /* Tuning mode 1 limits the maximum data length to 4MB */
1927 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1929 host->flags &= ~SDHCI_NEEDS_RETUNING;
1930 /* Reload the new initial value for timer */
1931 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1932 mod_timer(&host->tuning_timer, jiffies +
1933 host->tuning_count * HZ);
1937 * In case tuning fails, host controllers which support re-tuning can
1938 * try tuning again at a later time, when the re-tuning timer expires.
1939 * So for these controllers, we return 0. Since there might be other
1940 * controllers who do not have this capability, we return error for
1941 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
1942 * a retuning timer to do the retuning for the card.
1944 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
1947 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1948 spin_unlock(&host->lock);
1949 enable_irq(host->irq);
1950 sdhci_runtime_pm_put(host);
1955 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1958 unsigned long flags;
1960 /* Host Controller v3.00 defines preset value registers */
1961 if (host->version < SDHCI_SPEC_300)
1964 spin_lock_irqsave(&host->lock, flags);
1966 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1969 * We only enable or disable Preset Value if they are not already
1970 * enabled or disabled respectively. Otherwise, we bail out.
1972 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1973 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1974 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1975 host->flags |= SDHCI_PV_ENABLED;
1976 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1977 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1978 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1979 host->flags &= ~SDHCI_PV_ENABLED;
1982 spin_unlock_irqrestore(&host->lock, flags);
1985 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1987 struct sdhci_host *host = mmc_priv(mmc);
1989 sdhci_runtime_pm_get(host);
1990 sdhci_do_enable_preset_value(host, enable);
1991 sdhci_runtime_pm_put(host);
1994 static const struct mmc_host_ops sdhci_ops = {
1995 .request = sdhci_request,
1996 .set_ios = sdhci_set_ios,
1997 .get_ro = sdhci_get_ro,
1998 .hw_reset = sdhci_hw_reset,
1999 .enable_sdio_irq = sdhci_enable_sdio_irq,
2000 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2001 .execute_tuning = sdhci_execute_tuning,
2002 .enable_preset_value = sdhci_enable_preset_value,
2005 /*****************************************************************************\
2009 \*****************************************************************************/
2011 static void sdhci_tasklet_card(unsigned long param)
2013 struct sdhci_host *host;
2014 unsigned long flags;
2016 host = (struct sdhci_host*)param;
2018 spin_lock_irqsave(&host->lock, flags);
2020 /* Check host->mrq first in case we are runtime suspended */
2022 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
2023 pr_err("%s: Card removed during transfer!\n",
2024 mmc_hostname(host->mmc));
2025 pr_err("%s: Resetting controller.\n",
2026 mmc_hostname(host->mmc));
2028 sdhci_reset(host, SDHCI_RESET_CMD);
2029 sdhci_reset(host, SDHCI_RESET_DATA);
2031 host->mrq->cmd->error = -ENOMEDIUM;
2032 tasklet_schedule(&host->finish_tasklet);
2035 spin_unlock_irqrestore(&host->lock, flags);
2037 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2040 static void sdhci_tasklet_finish(unsigned long param)
2042 struct sdhci_host *host;
2043 unsigned long flags;
2044 struct mmc_request *mrq;
2046 host = (struct sdhci_host*)param;
2048 spin_lock_irqsave(&host->lock, flags);
2051 * If this tasklet gets rescheduled while running, it will
2052 * be run again afterwards but without any active request.
2055 spin_unlock_irqrestore(&host->lock, flags);
2059 del_timer(&host->timer);
2064 * The controller needs a reset of internal state machines
2065 * upon error conditions.
2067 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2068 ((mrq->cmd && mrq->cmd->error) ||
2069 (mrq->data && (mrq->data->error ||
2070 (mrq->data->stop && mrq->data->stop->error))) ||
2071 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2073 /* Some controllers need this kick or reset won't work here */
2074 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
2077 /* This is to force an update */
2078 clock = host->clock;
2080 sdhci_set_clock(host, clock);
2083 /* Spec says we should do both at the same time, but Ricoh
2084 controllers do not like that. */
2085 sdhci_reset(host, SDHCI_RESET_CMD);
2086 sdhci_reset(host, SDHCI_RESET_DATA);
2093 #ifndef SDHCI_USE_LEDS_CLASS
2094 sdhci_deactivate_led(host);
2098 spin_unlock_irqrestore(&host->lock, flags);
2100 mmc_request_done(host->mmc, mrq);
2101 sdhci_runtime_pm_put(host);
2104 static void sdhci_timeout_timer(unsigned long data)
2106 struct sdhci_host *host;
2107 unsigned long flags;
2109 host = (struct sdhci_host*)data;
2111 spin_lock_irqsave(&host->lock, flags);
2114 pr_err("%s: Timeout waiting for hardware "
2115 "interrupt.\n", mmc_hostname(host->mmc));
2116 sdhci_dumpregs(host);
2119 host->data->error = -ETIMEDOUT;
2120 sdhci_finish_data(host);
2123 host->cmd->error = -ETIMEDOUT;
2125 host->mrq->cmd->error = -ETIMEDOUT;
2127 tasklet_schedule(&host->finish_tasklet);
2132 spin_unlock_irqrestore(&host->lock, flags);
2135 static void sdhci_tuning_timer(unsigned long data)
2137 struct sdhci_host *host;
2138 unsigned long flags;
2140 host = (struct sdhci_host *)data;
2142 spin_lock_irqsave(&host->lock, flags);
2144 host->flags |= SDHCI_NEEDS_RETUNING;
2146 spin_unlock_irqrestore(&host->lock, flags);
2149 /*****************************************************************************\
2151 * Interrupt handling *
2153 \*****************************************************************************/
2155 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2157 BUG_ON(intmask == 0);
2160 pr_err("%s: Got command interrupt 0x%08x even "
2161 "though no command operation was in progress.\n",
2162 mmc_hostname(host->mmc), (unsigned)intmask);
2163 sdhci_dumpregs(host);
2167 if (intmask & SDHCI_INT_TIMEOUT)
2168 host->cmd->error = -ETIMEDOUT;
2169 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2171 host->cmd->error = -EILSEQ;
2173 if (host->cmd->error) {
2174 tasklet_schedule(&host->finish_tasklet);
2179 * The host can send and interrupt when the busy state has
2180 * ended, allowing us to wait without wasting CPU cycles.
2181 * Unfortunately this is overloaded on the "data complete"
2182 * interrupt, so we need to take some care when handling
2185 * Note: The 1.0 specification is a bit ambiguous about this
2186 * feature so there might be some problems with older
2189 if (host->cmd->flags & MMC_RSP_BUSY) {
2190 if (host->cmd->data)
2191 DBG("Cannot wait for busy signal when also "
2192 "doing a data transfer");
2193 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2196 /* The controller does not support the end-of-busy IRQ,
2197 * fall through and take the SDHCI_INT_RESPONSE */
2200 if (intmask & SDHCI_INT_RESPONSE)
2201 sdhci_finish_command(host);
2204 #ifdef CONFIG_MMC_DEBUG
2205 static void sdhci_show_adma_error(struct sdhci_host *host)
2207 const char *name = mmc_hostname(host->mmc);
2208 u8 *desc = host->adma_desc;
2213 sdhci_dumpregs(host);
2216 dma = (__le32 *)(desc + 4);
2217 len = (__le16 *)(desc + 2);
2220 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2221 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2230 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2233 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2236 BUG_ON(intmask == 0);
2238 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2239 if (intmask & SDHCI_INT_DATA_AVAIL) {
2240 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2241 if (command == MMC_SEND_TUNING_BLOCK ||
2242 command == MMC_SEND_TUNING_BLOCK_HS200) {
2243 host->tuning_done = 1;
2244 wake_up(&host->buf_ready_int);
2251 * The "data complete" interrupt is also used to
2252 * indicate that a busy state has ended. See comment
2253 * above in sdhci_cmd_irq().
2255 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2256 if (intmask & SDHCI_INT_DATA_END) {
2257 sdhci_finish_command(host);
2262 pr_err("%s: Got data interrupt 0x%08x even "
2263 "though no data operation was in progress.\n",
2264 mmc_hostname(host->mmc), (unsigned)intmask);
2265 sdhci_dumpregs(host);
2270 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2271 host->data->error = -ETIMEDOUT;
2272 else if (intmask & SDHCI_INT_DATA_END_BIT)
2273 host->data->error = -EILSEQ;
2274 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2275 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2277 host->data->error = -EILSEQ;
2278 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2279 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2280 sdhci_show_adma_error(host);
2281 host->data->error = -EIO;
2284 if (host->data->error)
2285 sdhci_finish_data(host);
2287 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2288 sdhci_transfer_pio(host);
2291 * We currently don't do anything fancy with DMA
2292 * boundaries, but as we can't disable the feature
2293 * we need to at least restart the transfer.
2295 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2296 * should return a valid address to continue from, but as
2297 * some controllers are faulty, don't trust them.
2299 if (intmask & SDHCI_INT_DMA_END) {
2300 u32 dmastart, dmanow;
2301 dmastart = sg_dma_address(host->data->sg);
2302 dmanow = dmastart + host->data->bytes_xfered;
2304 * Force update to the next DMA block boundary.
2307 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2308 SDHCI_DEFAULT_BOUNDARY_SIZE;
2309 host->data->bytes_xfered = dmanow - dmastart;
2310 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2312 mmc_hostname(host->mmc), dmastart,
2313 host->data->bytes_xfered, dmanow);
2314 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2317 if (intmask & SDHCI_INT_DATA_END) {
2320 * Data managed to finish before the
2321 * command completed. Make sure we do
2322 * things in the proper order.
2324 host->data_early = 1;
2326 sdhci_finish_data(host);
2332 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2335 struct sdhci_host *host = dev_id;
2336 u32 intmask, unexpected = 0;
2337 int cardint = 0, max_loops = 16;
2339 spin_lock(&host->lock);
2341 if (host->runtime_suspended) {
2342 spin_unlock(&host->lock);
2343 pr_warning("%s: got irq while runtime suspended\n",
2344 mmc_hostname(host->mmc));
2348 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2350 if (!intmask || intmask == 0xffffffff) {
2356 DBG("*** %s got interrupt: 0x%08x\n",
2357 mmc_hostname(host->mmc), intmask);
2359 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2360 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2364 * There is a observation on i.mx esdhc. INSERT bit will be
2365 * immediately set again when it gets cleared, if a card is
2366 * inserted. We have to mask the irq to prevent interrupt
2367 * storm which will freeze the system. And the REMOVE gets
2368 * the same situation.
2370 * More testing are needed here to ensure it works for other
2373 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2374 SDHCI_INT_CARD_REMOVE);
2375 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2376 SDHCI_INT_CARD_INSERT);
2378 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2379 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2380 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2381 tasklet_schedule(&host->card_tasklet);
2384 if (intmask & SDHCI_INT_CMD_MASK) {
2385 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2387 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2390 if (intmask & SDHCI_INT_DATA_MASK) {
2391 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2393 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2396 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2398 intmask &= ~SDHCI_INT_ERROR;
2400 if (intmask & SDHCI_INT_BUS_POWER) {
2401 pr_err("%s: Card is consuming too much power!\n",
2402 mmc_hostname(host->mmc));
2403 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2406 intmask &= ~SDHCI_INT_BUS_POWER;
2408 if (intmask & SDHCI_INT_CARD_INT)
2411 intmask &= ~SDHCI_INT_CARD_INT;
2414 unexpected |= intmask;
2415 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2418 result = IRQ_HANDLED;
2420 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2421 if (intmask && --max_loops)
2424 spin_unlock(&host->lock);
2427 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2428 mmc_hostname(host->mmc), unexpected);
2429 sdhci_dumpregs(host);
2432 * We have to delay this as it calls back into the driver.
2435 mmc_signal_sdio_irq(host->mmc);
2440 /*****************************************************************************\
2444 \*****************************************************************************/
2448 int sdhci_suspend_host(struct sdhci_host *host)
2452 if (host->ops->platform_suspend)
2453 host->ops->platform_suspend(host);
2455 sdhci_disable_card_detection(host);
2457 /* Disable tuning since we are suspending */
2458 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2459 del_timer_sync(&host->tuning_timer);
2460 host->flags &= ~SDHCI_NEEDS_RETUNING;
2463 ret = mmc_suspend_host(host->mmc);
2465 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2466 host->flags |= SDHCI_NEEDS_RETUNING;
2467 mod_timer(&host->tuning_timer, jiffies +
2468 host->tuning_count * HZ);
2471 sdhci_enable_card_detection(host);
2476 free_irq(host->irq, host);
2481 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2483 int sdhci_resume_host(struct sdhci_host *host)
2487 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2488 if (host->ops->enable_dma)
2489 host->ops->enable_dma(host);
2492 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2493 mmc_hostname(host->mmc), host);
2497 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2498 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2499 /* Card keeps power but host controller does not */
2500 sdhci_init(host, 0);
2503 sdhci_do_set_ios(host, &host->mmc->ios);
2505 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2509 ret = mmc_resume_host(host->mmc);
2510 sdhci_enable_card_detection(host);
2512 if (host->ops->platform_resume)
2513 host->ops->platform_resume(host);
2515 /* Set the re-tuning expiration flag */
2516 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2517 host->flags |= SDHCI_NEEDS_RETUNING;
2522 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2524 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2527 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2528 val |= SDHCI_WAKE_ON_INT;
2529 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2532 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2534 #endif /* CONFIG_PM */
2536 #ifdef CONFIG_PM_RUNTIME
2538 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2540 return pm_runtime_get_sync(host->mmc->parent);
2543 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2545 pm_runtime_mark_last_busy(host->mmc->parent);
2546 return pm_runtime_put_autosuspend(host->mmc->parent);
2549 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2551 unsigned long flags;
2554 /* Disable tuning since we are suspending */
2555 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2556 del_timer_sync(&host->tuning_timer);
2557 host->flags &= ~SDHCI_NEEDS_RETUNING;
2560 spin_lock_irqsave(&host->lock, flags);
2561 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2562 spin_unlock_irqrestore(&host->lock, flags);
2564 synchronize_irq(host->irq);
2566 spin_lock_irqsave(&host->lock, flags);
2567 host->runtime_suspended = true;
2568 spin_unlock_irqrestore(&host->lock, flags);
2572 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2574 int sdhci_runtime_resume_host(struct sdhci_host *host)
2576 unsigned long flags;
2577 int ret = 0, host_flags = host->flags;
2579 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2580 if (host->ops->enable_dma)
2581 host->ops->enable_dma(host);
2584 sdhci_init(host, 0);
2586 /* Force clock and power re-program */
2589 sdhci_do_set_ios(host, &host->mmc->ios);
2591 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2592 if (host_flags & SDHCI_PV_ENABLED)
2593 sdhci_do_enable_preset_value(host, true);
2595 /* Set the re-tuning expiration flag */
2596 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2597 host->flags |= SDHCI_NEEDS_RETUNING;
2599 spin_lock_irqsave(&host->lock, flags);
2601 host->runtime_suspended = false;
2603 /* Enable SDIO IRQ */
2604 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2605 sdhci_enable_sdio_irq_nolock(host, true);
2607 /* Enable Card Detection */
2608 sdhci_enable_card_detection(host);
2610 spin_unlock_irqrestore(&host->lock, flags);
2614 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2618 /*****************************************************************************\
2620 * Device allocation/registration *
2622 \*****************************************************************************/
2624 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2627 struct mmc_host *mmc;
2628 struct sdhci_host *host;
2630 WARN_ON(dev == NULL);
2632 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2634 return ERR_PTR(-ENOMEM);
2636 host = mmc_priv(mmc);
2642 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2644 int sdhci_add_host(struct sdhci_host *host)
2646 struct mmc_host *mmc;
2647 u32 caps[2] = {0, 0};
2648 u32 max_current_caps;
2649 unsigned int ocr_avail;
2652 WARN_ON(host == NULL);
2659 host->quirks = debug_quirks;
2661 host->quirks2 = debug_quirks2;
2663 sdhci_reset(host, SDHCI_RESET_ALL);
2665 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2666 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2667 >> SDHCI_SPEC_VER_SHIFT;
2668 if (host->version > SDHCI_SPEC_300) {
2669 pr_err("%s: Unknown controller version (%d). "
2670 "You may experience problems.\n", mmc_hostname(mmc),
2674 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2675 sdhci_readl(host, SDHCI_CAPABILITIES);
2677 if (host->version >= SDHCI_SPEC_300)
2678 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2680 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2682 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2683 host->flags |= SDHCI_USE_SDMA;
2684 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2685 DBG("Controller doesn't have SDMA capability\n");
2687 host->flags |= SDHCI_USE_SDMA;
2689 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2690 (host->flags & SDHCI_USE_SDMA)) {
2691 DBG("Disabling DMA as it is marked broken\n");
2692 host->flags &= ~SDHCI_USE_SDMA;
2695 if ((host->version >= SDHCI_SPEC_200) &&
2696 (caps[0] & SDHCI_CAN_DO_ADMA2))
2697 host->flags |= SDHCI_USE_ADMA;
2699 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2700 (host->flags & SDHCI_USE_ADMA)) {
2701 DBG("Disabling ADMA as it is marked broken\n");
2702 host->flags &= ~SDHCI_USE_ADMA;
2705 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2706 if (host->ops->enable_dma) {
2707 if (host->ops->enable_dma(host)) {
2708 pr_warning("%s: No suitable DMA "
2709 "available. Falling back to PIO.\n",
2712 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2717 if (host->flags & SDHCI_USE_ADMA) {
2719 * We need to allocate descriptors for all sg entries
2720 * (128) and potentially one alignment transfer for
2721 * each of those entries.
2723 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2724 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2725 if (!host->adma_desc || !host->align_buffer) {
2726 kfree(host->adma_desc);
2727 kfree(host->align_buffer);
2728 pr_warning("%s: Unable to allocate ADMA "
2729 "buffers. Falling back to standard DMA.\n",
2731 host->flags &= ~SDHCI_USE_ADMA;
2736 * If we use DMA, then it's up to the caller to set the DMA
2737 * mask, but PIO does not need the hw shim so we set a new
2738 * mask here in that case.
2740 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2741 host->dma_mask = DMA_BIT_MASK(64);
2742 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2745 if (host->version >= SDHCI_SPEC_300)
2746 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2747 >> SDHCI_CLOCK_BASE_SHIFT;
2749 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2750 >> SDHCI_CLOCK_BASE_SHIFT;
2752 host->max_clk *= 1000000;
2753 if (host->max_clk == 0 || host->quirks &
2754 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2755 if (!host->ops->get_max_clock) {
2756 pr_err("%s: Hardware doesn't specify base clock "
2757 "frequency.\n", mmc_hostname(mmc));
2760 host->max_clk = host->ops->get_max_clock(host);
2764 * In case of Host Controller v3.00, find out whether clock
2765 * multiplier is supported.
2767 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2768 SDHCI_CLOCK_MUL_SHIFT;
2771 * In case the value in Clock Multiplier is 0, then programmable
2772 * clock mode is not supported, otherwise the actual clock
2773 * multiplier is one more than the value of Clock Multiplier
2774 * in the Capabilities Register.
2780 * Set host parameters.
2782 mmc->ops = &sdhci_ops;
2783 mmc->f_max = host->max_clk;
2784 if (host->ops->get_min_clock)
2785 mmc->f_min = host->ops->get_min_clock(host);
2786 else if (host->version >= SDHCI_SPEC_300) {
2787 if (host->clk_mul) {
2788 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2789 mmc->f_max = host->max_clk * host->clk_mul;
2791 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2793 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2796 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2797 if (host->timeout_clk == 0) {
2798 if (host->ops->get_timeout_clock) {
2799 host->timeout_clk = host->ops->get_timeout_clock(host);
2800 } else if (!(host->quirks &
2801 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2802 pr_err("%s: Hardware doesn't specify timeout clock "
2803 "frequency.\n", mmc_hostname(mmc));
2807 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2808 host->timeout_clk *= 1000;
2810 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2811 host->timeout_clk = mmc->f_max / 1000;
2813 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2815 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2817 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2818 host->flags |= SDHCI_AUTO_CMD12;
2820 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2821 if ((host->version >= SDHCI_SPEC_300) &&
2822 ((host->flags & SDHCI_USE_ADMA) ||
2823 !(host->flags & SDHCI_USE_SDMA))) {
2824 host->flags |= SDHCI_AUTO_CMD23;
2825 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2827 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2831 * A controller may support 8-bit width, but the board itself
2832 * might not have the pins brought out. Boards that support
2833 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2834 * their platform code before calling sdhci_add_host(), and we
2835 * won't assume 8-bit width for hosts without that CAP.
2837 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2838 mmc->caps |= MMC_CAP_4_BIT_DATA;
2840 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2841 mmc->caps &= ~MMC_CAP_CMD23;
2843 if (caps[0] & SDHCI_CAN_DO_HISPD)
2844 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2846 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2847 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2848 mmc->caps |= MMC_CAP_NEEDS_POLL;
2850 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2851 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
2852 if (IS_ERR(host->vqmmc)) {
2853 pr_info("%s: no vqmmc regulator found\n", mmc_hostname(mmc));
2856 else if (regulator_is_supported_voltage(host->vqmmc, 1800000, 1800000))
2857 regulator_enable(host->vqmmc);
2859 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2860 SDHCI_SUPPORT_DDR50);
2862 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2863 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2864 SDHCI_SUPPORT_DDR50))
2865 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2867 /* SDR104 supports also implies SDR50 support */
2868 if (caps[1] & SDHCI_SUPPORT_SDR104)
2869 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2870 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2871 mmc->caps |= MMC_CAP_UHS_SDR50;
2873 if (caps[1] & SDHCI_SUPPORT_DDR50)
2874 mmc->caps |= MMC_CAP_UHS_DDR50;
2876 /* Does the host need tuning for SDR50? */
2877 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2878 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2880 /* Does the host need tuning for HS200? */
2881 if (mmc->caps2 & MMC_CAP2_HS200)
2882 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2884 /* Driver Type(s) (A, C, D) supported by the host */
2885 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2886 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2887 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2888 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2889 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2890 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2892 /* Initial value for re-tuning timer count */
2893 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2894 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2897 * In case Re-tuning Timer is not disabled, the actual value of
2898 * re-tuning timer will be 2 ^ (n - 1).
2900 if (host->tuning_count)
2901 host->tuning_count = 1 << (host->tuning_count - 1);
2903 /* Re-tuning mode supported by the Host Controller */
2904 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2905 SDHCI_RETUNING_MODE_SHIFT;
2909 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2910 if (IS_ERR(host->vmmc)) {
2911 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2914 regulator_enable(host->vmmc);
2916 #ifdef CONFIG_REGULATOR
2918 ret = regulator_is_supported_voltage(host->vmmc, 3300000,
2920 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
2921 caps[0] &= ~SDHCI_CAN_VDD_330;
2922 ret = regulator_is_supported_voltage(host->vmmc, 3000000,
2924 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
2925 caps[0] &= ~SDHCI_CAN_VDD_300;
2926 ret = regulator_is_supported_voltage(host->vmmc, 1800000,
2928 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
2929 caps[0] &= ~SDHCI_CAN_VDD_180;
2931 #endif /* CONFIG_REGULATOR */
2934 * According to SD Host Controller spec v3.00, if the Host System
2935 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2936 * the value is meaningful only if Voltage Support in the Capabilities
2937 * register is set. The actual current value is 4 times the register
2940 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2941 if (!max_current_caps && host->vmmc) {
2942 u32 curr = regulator_get_current_limit(host->vmmc);
2945 /* convert to SDHCI_MAX_CURRENT format */
2946 curr = curr/1000; /* convert to mA */
2947 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
2949 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
2951 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
2952 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
2953 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
2957 if (caps[0] & SDHCI_CAN_VDD_330) {
2958 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2960 mmc->max_current_330 = ((max_current_caps &
2961 SDHCI_MAX_CURRENT_330_MASK) >>
2962 SDHCI_MAX_CURRENT_330_SHIFT) *
2963 SDHCI_MAX_CURRENT_MULTIPLIER;
2965 if (caps[0] & SDHCI_CAN_VDD_300) {
2966 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2968 mmc->max_current_300 = ((max_current_caps &
2969 SDHCI_MAX_CURRENT_300_MASK) >>
2970 SDHCI_MAX_CURRENT_300_SHIFT) *
2971 SDHCI_MAX_CURRENT_MULTIPLIER;
2973 if (caps[0] & SDHCI_CAN_VDD_180) {
2974 ocr_avail |= MMC_VDD_165_195;
2976 mmc->max_current_180 = ((max_current_caps &
2977 SDHCI_MAX_CURRENT_180_MASK) >>
2978 SDHCI_MAX_CURRENT_180_SHIFT) *
2979 SDHCI_MAX_CURRENT_MULTIPLIER;
2982 mmc->ocr_avail = ocr_avail;
2983 mmc->ocr_avail_sdio = ocr_avail;
2984 if (host->ocr_avail_sdio)
2985 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2986 mmc->ocr_avail_sd = ocr_avail;
2987 if (host->ocr_avail_sd)
2988 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2989 else /* normal SD controllers don't support 1.8V */
2990 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2991 mmc->ocr_avail_mmc = ocr_avail;
2992 if (host->ocr_avail_mmc)
2993 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2995 if (mmc->ocr_avail == 0) {
2996 pr_err("%s: Hardware doesn't report any "
2997 "support voltages.\n", mmc_hostname(mmc));
3001 spin_lock_init(&host->lock);
3004 * Maximum number of segments. Depends on if the hardware
3005 * can do scatter/gather or not.
3007 if (host->flags & SDHCI_USE_ADMA)
3008 mmc->max_segs = 128;
3009 else if (host->flags & SDHCI_USE_SDMA)
3012 mmc->max_segs = 128;
3015 * Maximum number of sectors in one transfer. Limited by DMA boundary
3018 mmc->max_req_size = 524288;
3021 * Maximum segment size. Could be one segment with the maximum number
3022 * of bytes. When doing hardware scatter/gather, each entry cannot
3023 * be larger than 64 KiB though.
3025 if (host->flags & SDHCI_USE_ADMA) {
3026 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3027 mmc->max_seg_size = 65535;
3029 mmc->max_seg_size = 65536;
3031 mmc->max_seg_size = mmc->max_req_size;
3035 * Maximum block size. This varies from controller to controller and
3036 * is specified in the capabilities register.
3038 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3039 mmc->max_blk_size = 2;
3041 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3042 SDHCI_MAX_BLOCK_SHIFT;
3043 if (mmc->max_blk_size >= 3) {
3044 pr_warning("%s: Invalid maximum block size, "
3045 "assuming 512 bytes\n", mmc_hostname(mmc));
3046 mmc->max_blk_size = 0;
3050 mmc->max_blk_size = 512 << mmc->max_blk_size;
3053 * Maximum block count.
3055 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3060 tasklet_init(&host->card_tasklet,
3061 sdhci_tasklet_card, (unsigned long)host);
3062 tasklet_init(&host->finish_tasklet,
3063 sdhci_tasklet_finish, (unsigned long)host);
3065 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3067 if (host->version >= SDHCI_SPEC_300) {
3068 init_waitqueue_head(&host->buf_ready_int);
3070 /* Initialize re-tuning timer */
3071 init_timer(&host->tuning_timer);
3072 host->tuning_timer.data = (unsigned long)host;
3073 host->tuning_timer.function = sdhci_tuning_timer;
3076 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3077 mmc_hostname(mmc), host);
3079 pr_err("%s: Failed to request IRQ %d: %d\n",
3080 mmc_hostname(mmc), host->irq, ret);
3084 sdhci_init(host, 0);
3086 #ifdef CONFIG_MMC_DEBUG
3087 sdhci_dumpregs(host);
3090 #ifdef SDHCI_USE_LEDS_CLASS
3091 snprintf(host->led_name, sizeof(host->led_name),
3092 "%s::", mmc_hostname(mmc));
3093 host->led.name = host->led_name;
3094 host->led.brightness = LED_OFF;
3095 host->led.default_trigger = mmc_hostname(mmc);
3096 host->led.brightness_set = sdhci_led_control;
3098 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3100 pr_err("%s: Failed to register LED device: %d\n",
3101 mmc_hostname(mmc), ret);
3110 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3111 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3112 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3113 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3115 sdhci_enable_card_detection(host);
3119 #ifdef SDHCI_USE_LEDS_CLASS
3121 sdhci_reset(host, SDHCI_RESET_ALL);
3122 free_irq(host->irq, host);
3125 tasklet_kill(&host->card_tasklet);
3126 tasklet_kill(&host->finish_tasklet);
3131 EXPORT_SYMBOL_GPL(sdhci_add_host);
3133 void sdhci_remove_host(struct sdhci_host *host, int dead)
3135 unsigned long flags;
3138 spin_lock_irqsave(&host->lock, flags);
3140 host->flags |= SDHCI_DEVICE_DEAD;
3143 pr_err("%s: Controller removed during "
3144 " transfer!\n", mmc_hostname(host->mmc));
3146 host->mrq->cmd->error = -ENOMEDIUM;
3147 tasklet_schedule(&host->finish_tasklet);
3150 spin_unlock_irqrestore(&host->lock, flags);
3153 sdhci_disable_card_detection(host);
3155 mmc_remove_host(host->mmc);
3157 #ifdef SDHCI_USE_LEDS_CLASS
3158 led_classdev_unregister(&host->led);
3162 sdhci_reset(host, SDHCI_RESET_ALL);
3164 free_irq(host->irq, host);
3166 del_timer_sync(&host->timer);
3168 tasklet_kill(&host->card_tasklet);
3169 tasklet_kill(&host->finish_tasklet);
3172 regulator_disable(host->vmmc);
3173 regulator_put(host->vmmc);
3177 regulator_disable(host->vqmmc);
3178 regulator_put(host->vqmmc);
3181 kfree(host->adma_desc);
3182 kfree(host->align_buffer);
3184 host->adma_desc = NULL;
3185 host->align_buffer = NULL;
3188 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3190 void sdhci_free_host(struct sdhci_host *host)
3192 mmc_free_host(host->mmc);
3195 EXPORT_SYMBOL_GPL(sdhci_free_host);
3197 /*****************************************************************************\
3199 * Driver init/exit *
3201 \*****************************************************************************/
3203 static int __init sdhci_drv_init(void)
3206 ": Secure Digital Host Controller Interface driver\n");
3207 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3212 static void __exit sdhci_drv_exit(void)
3216 module_init(sdhci_drv_init);
3217 module_exit(sdhci_drv_exit);
3219 module_param(debug_quirks, uint, 0444);
3220 module_param(debug_quirks2, uint, 0444);
3222 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3223 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3224 MODULE_LICENSE("GPL");
3226 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3227 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");