drivers/mmc/host/sdhci-xenon.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Marvell Xenon SDHC as a platform device
   4  *
   5  * Copyright (C) 2016 Marvell, All Rights Reserved.
   6  *
   7  * Author:      Hu Ziji <huziji@marvell.com>
   8  * Date:        2016-8-24
   9  *
  10  * Inspired by Jisheng Zhang <jszhang@marvell.com>
  11  * Special thanks to Video BG4 project team.
  12  */
  13
  14 #include <linux/acpi.h>
  15 #include <linux/delay.h>
  16 #include <linux/ktime.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/pm.h>
  20 #include <linux/pm_runtime.h>
  21
  22 #include "sdhci-pltfm.h"
  23 #include "sdhci-xenon.h"
  24
  25 static int xenon_enable_internal_clk(struct sdhci_host *host)
  26 {
  27         u32 reg;
  28         ktime_t timeout;
  29
  30         reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
  31         reg |= SDHCI_CLOCK_INT_EN;
  32         sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
  33         /* Wait max 20 ms */
  34         timeout = ktime_add_ms(ktime_get(), 20);
  35         while (1) {
  36                 bool timedout = ktime_after(ktime_get(), timeout);
  37
  38                 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  39                 if (reg & SDHCI_CLOCK_INT_STABLE)
  40                         break;
  41                 if (timedout) {
  42                         dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n");
  43                         return -ETIMEDOUT;
  44                 }
  45                 usleep_range(900, 1100);
  46         }
  47
  48         return 0;
  49 }
  50
  51 /* Set SDCLK-off-while-idle */
  52 static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
  53                                      unsigned char sdhc_id, bool enable)
  54 {
  55         u32 reg;
  56         u32 mask;
  57
  58         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  59         /* Get the bit shift basing on the SDHC index */
  60         mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
  61         if (enable)
  62                 reg |= mask;
  63         else
  64                 reg &= ~mask;
  65
  66         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  67 }
  68
  69 /* Enable/Disable the Auto Clock Gating function */
  70 static void xenon_set_acg(struct sdhci_host *host, bool enable)
  71 {
  72         u32 reg;
  73
  74         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  75         if (enable)
  76                 reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
  77         else
  78                 reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
  79         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  80 }
  81
  82 /* Enable this SDHC */
  83 static void xenon_enable_sdhc(struct sdhci_host *host,
  84                               unsigned char sdhc_id)
  85 {
  86         u32 reg;
  87
  88         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  89         reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
  90         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  91
  92         host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
  93         /*
  94          * Force to clear BUS_TEST to
  95          * skip bus_test_pre and bus_test_post
  96          */
  97         host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
  98 }
  99
 100 /* Disable this SDHC */
 101 static void xenon_disable_sdhc(struct sdhci_host *host,
 102                                unsigned char sdhc_id)
 103 {
 104         u32 reg;
 105
 106         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
 107         reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
 108         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
 109 }
 110
 111 /* Enable Parallel Transfer Mode */
 112 static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
 113                                             unsigned char sdhc_id)
 114 {
 115         u32 reg;
 116
 117         reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
 118         reg |= BIT(sdhc_id);
 119         sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
 120 }
 121
 122 /* Mask command conflict error */
 123 static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
 124 {
 125         u32  reg;
 126
 127         reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
 128         reg |= XENON_MASK_CMD_CONFLICT_ERR;
 129         sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
 130 }
 131
 132 static void xenon_retune_setup(struct sdhci_host *host)
 133 {
 134         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 135         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 136         u32 reg;
 137
 138         /* Disable the Re-Tuning Request functionality */
 139         reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
 140         reg &= ~XENON_RETUNING_COMPATIBLE;
 141         sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
 142
 143         /* Disable the Re-tuning Interrupt */
 144         reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
 145         reg &= ~SDHCI_INT_RETUNE;
 146         sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
 147         reg = sdhci_readl(host, SDHCI_INT_ENABLE);
 148         reg &= ~SDHCI_INT_RETUNE;
 149         sdhci_writel(host, reg, SDHCI_INT_ENABLE);
 150
 151         /* Force to use Tuning Mode 1 */
 152         host->tuning_mode = SDHCI_TUNING_MODE_1;
 153         /* Set re-tuning period */
 154         host->tuning_count = 1 << (priv->tuning_count - 1);
 155 }
 156
 157 /*
 158  * Operations inside struct sdhci_ops
 159  */
 160 /* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
 161 static void xenon_reset_exit(struct sdhci_host *host,
 162                              unsigned char sdhc_id, u8 mask)
 163 {
 164         /* Only SOFTWARE RESET ALL will clear the register setting */
 165         if (!(mask & SDHCI_RESET_ALL))
 166                 return;
 167
 168         /* Disable tuning request and auto-retuning again */
 169         xenon_retune_setup(host);
 170
 171         xenon_set_acg(host, true);
 172
 173         xenon_set_sdclk_off_idle(host, sdhc_id, false);
 174
 175         xenon_mask_cmd_conflict_err(host);
 176 }
 177
 178 static void xenon_reset(struct sdhci_host *host, u8 mask)
 179 {
 180         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 181         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 182
 183         sdhci_reset(host, mask);
 184         xenon_reset_exit(host, priv->sdhc_id, mask);
 185 }
 186
 187 /*
 188  * Xenon defines different values for HS200 and HS400
 189  * in Host_Control_2
 190  */
 191 static void xenon_set_uhs_signaling(struct sdhci_host *host,
 192                                     unsigned int timing)
 193 {
 194         u16 ctrl_2;
 195
 196         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 197         /* Select Bus Speed Mode for host */
 198         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 199         if (timing == MMC_TIMING_MMC_HS200)
 200                 ctrl_2 |= XENON_CTRL_HS200;
 201         else if (timing == MMC_TIMING_UHS_SDR104)
 202                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 203         else if (timing == MMC_TIMING_UHS_SDR12)
 204                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 205         else if (timing == MMC_TIMING_UHS_SDR25)
 206                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 207         else if (timing == MMC_TIMING_UHS_SDR50)
 208                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 209         else if ((timing == MMC_TIMING_UHS_DDR50) ||
 210                  (timing == MMC_TIMING_MMC_DDR52))
 211                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 212         else if (timing == MMC_TIMING_MMC_HS400)
 213                 ctrl_2 |= XENON_CTRL_HS400;
 214         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 215 }
 216
 217 static void xenon_set_power(struct sdhci_host *host, unsigned char mode,
 218                 unsigned short vdd)
 219 {
 220         struct mmc_host *mmc = host->mmc;
 221         u8 pwr = host->pwr;
 222
 223         sdhci_set_power_noreg(host, mode, vdd);
 224
 225         if (host->pwr == pwr)
 226                 return;
 227
 228         if (host->pwr == 0)
 229                 vdd = 0;
 230
 231         if (!IS_ERR(mmc->supply.vmmc))
 232                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 233 }
 234
 235 static void xenon_voltage_switch(struct sdhci_host *host)
 236 {
 237         /* Wait for 5ms after set 1.8V signal enable bit */
 238         usleep_range(5000, 5500);
 239
 240         /*
 241          * For some reason the controller's Host Control2 register reports
 242          * the bit representing 1.8V signaling as 0 when read after it was
 243          * written as 1. Subsequent read reports 1.
 244          *
 245          * Since this may cause some issues, do an empty read of the Host
 246          * Control2 register here to circumvent this.
 247          */
 248         sdhci_readw(host, SDHCI_HOST_CONTROL2);
 249 }
 250
 251 static unsigned int xenon_get_max_clock(struct sdhci_host *host)
 252 {
 253         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 254
 255         if (pltfm_host->clk)
 256                 return sdhci_pltfm_clk_get_max_clock(host);
 257         else
 258                 return pltfm_host->clock;
 259 }
 260
 261 static const struct sdhci_ops sdhci_xenon_ops = {
 262         .voltage_switch         = xenon_voltage_switch,
 263         .set_clock              = sdhci_set_clock,
 264         .set_power              = xenon_set_power,
 265         .set_bus_width          = sdhci_set_bus_width,
 266         .reset                  = xenon_reset,
 267         .set_uhs_signaling      = xenon_set_uhs_signaling,
 268         .get_max_clock          = xenon_get_max_clock,
 269 };
 270
 271 static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
 272         .ops = &sdhci_xenon_ops,
 273         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
 274                   SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
 275                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 276 };
 277
 278 /*
 279  * Xenon Specific Operations in mmc_host_ops
 280  */
 281 static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 282 {
 283         struct sdhci_host *host = mmc_priv(mmc);
 284         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 285         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 286         u32 reg;
 287
 288         /*
 289          * HS400/HS200/eMMC HS doesn't have Preset Value register.
 290          * However, sdhci_set_ios will read HS400/HS200 Preset register.
 291          * Disable Preset Value register for HS400/HS200.
 292          * eMMC HS with preset_enabled set will trigger a bug in
 293          * get_preset_value().
 294          */
 295         if ((ios->timing == MMC_TIMING_MMC_HS400) ||
 296             (ios->timing == MMC_TIMING_MMC_HS200) ||
 297             (ios->timing == MMC_TIMING_MMC_HS)) {
 298                 host->preset_enabled = false;
 299                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 300                 host->flags &= ~SDHCI_PV_ENABLED;
 301
 302                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 303                 reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 304                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 305         } else {
 306                 host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 307         }
 308
 309         sdhci_set_ios(mmc, ios);
 310         xenon_phy_adj(host, ios);
 311
 312         if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
 313                 xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
 314 }
 315
 316 static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
 317                                              struct mmc_ios *ios)
 318 {
 319         struct sdhci_host *host = mmc_priv(mmc);
 320
 321         /*
 322          * Before SD/SDIO set signal voltage, SD bus clock should be
 323          * disabled. However, sdhci_set_clock will also disable the Internal
 324          * clock in mmc_set_signal_voltage().
 325          * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
 326          * Thus here manually enable internal clock.
 327          *
 328          * After switch completes, it is unnecessary to disable internal clock,
 329          * since keeping internal clock active obeys SD spec.
 330          */
 331         xenon_enable_internal_clk(host);
 332
 333         xenon_soc_pad_ctrl(host, ios->signal_voltage);
 334
 335         /*
 336          * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable.
 337          * Thus SDHCI_CTRL_VDD_180 bit might not work then.
 338          * Skip the standard voltage switch to avoid any issue.
 339          */
 340         if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV)
 341                 return 0;
 342
 343         return sdhci_start_signal_voltage_switch(mmc, ios);
 344 }
 345
 346 /*
 347  * Update card type.
 348  * priv->init_card_type will be used in PHY timing adjustment.
 349  */
 350 static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
 351 {
 352         struct sdhci_host *host = mmc_priv(mmc);
 353         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 354         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 355
 356         /* Update card type*/
 357         priv->init_card_type = card->type;
 358 }
 359
 360 static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
 361 {
 362         struct sdhci_host *host = mmc_priv(mmc);
 363
 364         if (host->timing == MMC_TIMING_UHS_DDR50 ||
 365                 host->timing == MMC_TIMING_MMC_DDR52)
 366                 return 0;
 367
 368         /*
 369          * Currently force Xenon driver back to support mode 1 only,
 370          * even though Xenon might claim to support mode 2 or mode 3.
 371          * It requires more time to test mode 2/mode 3 on more platforms.
 372          */
 373         if (host->tuning_mode != SDHCI_TUNING_MODE_1)
 374                 xenon_retune_setup(host);
 375
 376         return sdhci_execute_tuning(mmc, opcode);
 377 }
 378
 379 static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
 380 {
 381         struct sdhci_host *host = mmc_priv(mmc);
 382         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 383         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 384         u32 reg;
 385         u8 sdhc_id = priv->sdhc_id;
 386
 387         sdhci_enable_sdio_irq(mmc, enable);
 388
 389         if (enable) {
 390                 /*
 391                  * Set SDIO Card Inserted indication
 392                  * to enable detecting SDIO async irq.
 393                  */
 394                 reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
 395                 reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
 396                 sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
 397         } else {
 398                 /* Clear SDIO Card Inserted indication */
 399                 reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
 400                 reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
 401                 sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
 402         }
 403 }
 404
 405 static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
 406 {
 407         host->mmc_host_ops.set_ios = xenon_set_ios;
 408         host->mmc_host_ops.start_signal_voltage_switch =
 409                         xenon_start_signal_voltage_switch;
 410         host->mmc_host_ops.init_card = xenon_init_card;
 411         host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
 412         host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
 413 }
 414
 415 /*
 416  * Parse Xenon specific DT properties:
 417  * sdhc-id: the index of current SDHC.
 418  *          Refer to XENON_SYS_CFG_INFO register
 419  * tun-count: the interval between re-tuning
 420  */
 421 static int xenon_probe_params(struct platform_device *pdev)
 422 {
 423         struct device *dev = &pdev->dev;
 424         struct sdhci_host *host = platform_get_drvdata(pdev);
 425         struct mmc_host *mmc = host->mmc;
 426         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 427         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 428         u32 sdhc_id, nr_sdhc;
 429         u32 tuning_count;
 430
 431         /* Disable HS200 on Armada AP806 */
 432         if (priv->hw_version == XENON_AP806)
 433                 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
 434
 435         sdhc_id = 0x0;
 436         if (!device_property_read_u32(dev, "marvell,xenon-sdhc-id", &sdhc_id)) {
 437                 nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
 438                 nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
 439                 if (unlikely(sdhc_id > nr_sdhc)) {
 440                         dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
 441                                 sdhc_id, nr_sdhc);
 442                         return -EINVAL;
 443                 }
 444         }
 445         priv->sdhc_id = sdhc_id;
 446
 447         tuning_count = XENON_DEF_TUNING_COUNT;
 448         if (!device_property_read_u32(dev, "marvell,xenon-tun-count",
 449                                       &tuning_count)) {
 450                 if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
 451                         dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
 452                                 XENON_DEF_TUNING_COUNT);
 453                         tuning_count = XENON_DEF_TUNING_COUNT;
 454                 }
 455         }
 456         priv->tuning_count = tuning_count;
 457
 458         return xenon_phy_parse_params(dev, host);
 459 }
 460
 461 static int xenon_sdhc_prepare(struct sdhci_host *host)
 462 {
 463         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 464         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 465         u8 sdhc_id = priv->sdhc_id;
 466
 467         /* Enable SDHC */
 468         xenon_enable_sdhc(host, sdhc_id);
 469
 470         /* Enable ACG */
 471         xenon_set_acg(host, true);
 472
 473         /* Enable Parallel Transfer Mode */
 474         xenon_enable_sdhc_parallel_tran(host, sdhc_id);
 475
 476         /* Disable SDCLK-Off-While-Idle before card init */
 477         xenon_set_sdclk_off_idle(host, sdhc_id, false);
 478
 479         xenon_mask_cmd_conflict_err(host);
 480
 481         return 0;
 482 }
 483
 484 static void xenon_sdhc_unprepare(struct sdhci_host *host)
 485 {
 486         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 487         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 488         u8 sdhc_id = priv->sdhc_id;
 489
 490         /* disable SDHC */
 491         xenon_disable_sdhc(host, sdhc_id);
 492 }
 493
 494 static int xenon_probe(struct platform_device *pdev)
 495 {
 496         struct sdhci_pltfm_host *pltfm_host;
 497         struct device *dev = &pdev->dev;
 498         struct sdhci_host *host;
 499         struct xenon_priv *priv;
 500         int err;
 501
 502         host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
 503                                 sizeof(struct xenon_priv));
 504         if (IS_ERR(host))
 505                 return PTR_ERR(host);
 506
 507         pltfm_host = sdhci_priv(host);
 508         priv = sdhci_pltfm_priv(pltfm_host);
 509
 510         priv->hw_version = (unsigned long)device_get_match_data(&pdev->dev);
 511
 512         /*
 513          * Link Xenon specific mmc_host_ops function,
 514          * to replace standard ones in sdhci_ops.
 515          */
 516         xenon_replace_mmc_host_ops(host);
 517
 518         if (dev->of_node) {
 519                 pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
 520                 if (IS_ERR(pltfm_host->clk)) {
 521                         err = PTR_ERR(pltfm_host->clk);
 522                         dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
 523                         goto free_pltfm;
 524                 }
 525                 err = clk_prepare_enable(pltfm_host->clk);
 526                 if (err)
 527                         goto free_pltfm;
 528
 529                 priv->axi_clk = devm_clk_get(&pdev->dev, "axi");
 530                 if (IS_ERR(priv->axi_clk)) {
 531                         err = PTR_ERR(priv->axi_clk);
 532                         if (err == -EPROBE_DEFER)
 533                                 goto err_clk;
 534                 } else {
 535                         err = clk_prepare_enable(priv->axi_clk);
 536                         if (err)
 537                                 goto err_clk;
 538                 }
 539         }
 540
 541         err = mmc_of_parse(host->mmc);
 542         if (err)
 543                 goto err_clk_axi;
 544
 545         sdhci_get_property(pdev);
 546
 547         xenon_set_acg(host, false);
 548
 549         /* Xenon specific parameters parse */
 550         err = xenon_probe_params(pdev);
 551         if (err)
 552                 goto err_clk_axi;
 553
 554         err = xenon_sdhc_prepare(host);
 555         if (err)
 556                 goto err_clk_axi;
 557
 558         pm_runtime_get_noresume(&pdev->dev);
 559         pm_runtime_set_active(&pdev->dev);
 560         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 561         pm_runtime_use_autosuspend(&pdev->dev);
 562         pm_runtime_enable(&pdev->dev);
 563         pm_suspend_ignore_children(&pdev->dev, 1);
 564
 565         err = sdhci_add_host(host);
 566         if (err)
 567                 goto remove_sdhc;
 568
 569         pm_runtime_put_autosuspend(&pdev->dev);
 570
 571         return 0;
 572
 573 remove_sdhc:
 574         pm_runtime_disable(&pdev->dev);
 575         pm_runtime_put_noidle(&pdev->dev);
 576         xenon_sdhc_unprepare(host);
 577 err_clk_axi:
 578         clk_disable_unprepare(priv->axi_clk);
 579 err_clk:
 580         clk_disable_unprepare(pltfm_host->clk);
 581 free_pltfm:
 582         sdhci_pltfm_free(pdev);
 583         return err;
 584 }
 585
 586 static int xenon_remove(struct platform_device *pdev)
 587 {
 588         struct sdhci_host *host = platform_get_drvdata(pdev);
 589         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 590         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 591
 592         pm_runtime_get_sync(&pdev->dev);
 593         pm_runtime_disable(&pdev->dev);
 594         pm_runtime_put_noidle(&pdev->dev);
 595
 596         sdhci_remove_host(host, 0);
 597
 598         xenon_sdhc_unprepare(host);
 599         clk_disable_unprepare(priv->axi_clk);
 600         clk_disable_unprepare(pltfm_host->clk);
 601
 602         sdhci_pltfm_free(pdev);
 603
 604         return 0;
 605 }
 606
 607 #ifdef CONFIG_PM_SLEEP
 608 static int xenon_suspend(struct device *dev)
 609 {
 610         struct sdhci_host *host = dev_get_drvdata(dev);
 611         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 612         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 613         int ret;
 614
 615         ret = pm_runtime_force_suspend(dev);
 616
 617         priv->restore_needed = true;
 618         return ret;
 619 }
 620 #endif
 621
 622 #ifdef CONFIG_PM
 623 static int xenon_runtime_suspend(struct device *dev)
 624 {
 625         struct sdhci_host *host = dev_get_drvdata(dev);
 626         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 627         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 628         int ret;
 629
 630         ret = sdhci_runtime_suspend_host(host);
 631         if (ret)
 632                 return ret;
 633
 634         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 635                 mmc_retune_needed(host->mmc);
 636
 637         clk_disable_unprepare(pltfm_host->clk);
 638         /*
 639          * Need to update the priv->clock here, or when runtime resume
 640          * back, phy don't aware the clock change and won't adjust phy
 641          * which will cause cmd err
 642          */
 643         priv->clock = 0;
 644         return 0;
 645 }
 646
 647 static int xenon_runtime_resume(struct device *dev)
 648 {
 649         struct sdhci_host *host = dev_get_drvdata(dev);
 650         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 651         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 652         int ret;
 653
 654         ret = clk_prepare_enable(pltfm_host->clk);
 655         if (ret) {
 656                 dev_err(dev, "can't enable mainck\n");
 657                 return ret;
 658         }
 659
 660         if (priv->restore_needed) {
 661                 ret = xenon_sdhc_prepare(host);
 662                 if (ret)
 663                         goto out;
 664                 priv->restore_needed = false;
 665         }
 666
 667         ret = sdhci_runtime_resume_host(host, 0);
 668         if (ret)
 669                 goto out;
 670         return 0;
 671 out:
 672         clk_disable_unprepare(pltfm_host->clk);
 673         return ret;
 674 }
 675 #endif /* CONFIG_PM */
 676
 677 static const struct dev_pm_ops sdhci_xenon_dev_pm_ops = {
 678         SET_SYSTEM_SLEEP_PM_OPS(xenon_suspend,
 679                                 pm_runtime_force_resume)
 680         SET_RUNTIME_PM_OPS(xenon_runtime_suspend,
 681                            xenon_runtime_resume,
 682                            NULL)
 683 };
 684
 685 static const struct of_device_id sdhci_xenon_dt_ids[] = {
 686         { .compatible = "marvell,armada-ap806-sdhci", .data = (void *)XENON_AP806},
 687         { .compatible = "marvell,armada-cp110-sdhci", .data =  (void *)XENON_CP110},
 688         { .compatible = "marvell,armada-3700-sdhci", .data =  (void *)XENON_A3700},
 689         {}
 690 };
 691 MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
 692
 693 #ifdef CONFIG_ACPI
 694 static const struct acpi_device_id sdhci_xenon_acpi_ids[] = {
 695         { .id = "MRVL0002", XENON_AP806},
 696         { .id = "MRVL0003", XENON_AP807},
 697         { .id = "MRVL0004", XENON_CP110},
 698         {}
 699 };
 700 MODULE_DEVICE_TABLE(acpi, sdhci_xenon_acpi_ids);
 701 #endif
 702
 703 static struct platform_driver sdhci_xenon_driver = {
 704         .driver = {
 705                 .name   = "xenon-sdhci",
 706                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 707                 .of_match_table = sdhci_xenon_dt_ids,
 708                 .acpi_match_table = ACPI_PTR(sdhci_xenon_acpi_ids),
 709                 .pm = &sdhci_xenon_dev_pm_ops,
 710         },
 711         .probe  = xenon_probe,
 712         .remove = xenon_remove,
 713 };
 714
 715 module_platform_driver(sdhci_xenon_driver);
 716
 717 MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
 718 MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
 719 MODULE_LICENSE("GPL v2");