drivers/mmc/host/sdhci-sprd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Secure Digital Host Controller
   4 //
   5 // Copyright (C) 2018 Spreadtrum, Inc.
   6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
   7
   8 #include <linux/delay.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/highmem.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_gpio.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/slab.h>
  21
  22 #include "sdhci-pltfm.h"
  23 #include "mmc_hsq.h"
  24
  25 /* SDHCI_ARGUMENT2 register high 16bit */
  26 #define SDHCI_SPRD_ARG2_STUFF           GENMASK(31, 16)
  27
  28 #define SDHCI_SPRD_REG_32_DLL_CFG       0x200
  29 #define  SDHCI_SPRD_DLL_ALL_CPST_EN     (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
  30 #define  SDHCI_SPRD_DLL_EN              BIT(21)
  31 #define  SDHCI_SPRD_DLL_SEARCH_MODE     BIT(16)
  32 #define  SDHCI_SPRD_DLL_INIT_COUNT      0xc00
  33 #define  SDHCI_SPRD_DLL_PHASE_INTERNAL  0x3
  34
  35 #define SDHCI_SPRD_REG_32_DLL_DLY       0x204
  36
  37 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET        0x208
  38 #define  SDHCIBSPRD_IT_WR_DLY_INV               BIT(5)
  39 #define  SDHCI_SPRD_BIT_CMD_DLY_INV             BIT(13)
  40 #define  SDHCI_SPRD_BIT_POSRD_DLY_INV           BIT(21)
  41 #define  SDHCI_SPRD_BIT_NEGRD_DLY_INV           BIT(29)
  42
  43 #define SDHCI_SPRD_REG_32_DLL_STS0      0x210
  44 #define SDHCI_SPRD_DLL_LOCKED           BIT(18)
  45
  46 #define SDHCI_SPRD_REG_32_BUSY_POSI             0x250
  47 #define  SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN        BIT(25)
  48 #define  SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN        BIT(24)
  49
  50 #define SDHCI_SPRD_REG_DEBOUNCE         0x28C
  51 #define  SDHCI_SPRD_BIT_DLL_BAK         BIT(0)
  52 #define  SDHCI_SPRD_BIT_DLL_VAL         BIT(1)
  53
  54 #define  SDHCI_SPRD_INT_SIGNAL_MASK     0x1B7F410B
  55
  56 /* SDHCI_HOST_CONTROL2 */
  57 #define  SDHCI_SPRD_CTRL_HS200          0x0005
  58 #define  SDHCI_SPRD_CTRL_HS400          0x0006
  59 #define  SDHCI_SPRD_CTRL_HS400ES        0x0007
  60
  61 /*
  62  * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
  63  * reserved, and only used on Spreadtrum's design, the hardware cannot work
  64  * if this bit is cleared.
  65  * 1 : normal work
  66  * 0 : hardware reset
  67  */
  68 #define  SDHCI_HW_RESET_CARD            BIT(3)
  69
  70 #define SDHCI_SPRD_MAX_CUR              0xFFFFFF
  71 #define SDHCI_SPRD_CLK_MAX_DIV          1023
  72
  73 #define SDHCI_SPRD_CLK_DEF_RATE         26000000
  74 #define SDHCI_SPRD_PHY_DLL_CLK          52000000
  75
  76 struct sdhci_sprd_host {
  77         u32 version;
  78         struct clk *clk_sdio;
  79         struct clk *clk_enable;
  80         struct clk *clk_2x_enable;
  81         struct pinctrl *pinctrl;
  82         struct pinctrl_state *pins_uhs;
  83         struct pinctrl_state *pins_default;
  84         u32 base_rate;
  85         int flags; /* backup of host attribute */
  86         u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
  87 };
  88
  89 struct sdhci_sprd_phy_cfg {
  90         const char *property;
  91         u8 timing;
  92 };
  93
  94 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
  95         { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
  96         { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
  97         { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
  98         { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
  99         { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
 100         { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
 101         { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
 102         { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
 103         { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
 104 };
 105
 106 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
 107
 108 static void sdhci_sprd_init_config(struct sdhci_host *host)
 109 {
 110         u16 val;
 111
 112         /* set dll backup mode */
 113         val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
 114         val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
 115         sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
 116 }
 117
 118 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
 119 {
 120         if (unlikely(reg == SDHCI_MAX_CURRENT))
 121                 return SDHCI_SPRD_MAX_CUR;
 122
 123         return readl_relaxed(host->ioaddr + reg);
 124 }
 125
 126 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
 127 {
 128         /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
 129         if (unlikely(reg == SDHCI_MAX_CURRENT))
 130                 return;
 131
 132         if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
 133                 val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
 134
 135         writel_relaxed(val, host->ioaddr + reg);
 136 }
 137
 138 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
 139 {
 140         /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
 141         if (unlikely(reg == SDHCI_BLOCK_COUNT))
 142                 return;
 143
 144         writew_relaxed(val, host->ioaddr + reg);
 145 }
 146
 147 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
 148 {
 149         /*
 150          * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
 151          * standard specification, sdhci_reset() write this register directly
 152          * without checking other reserved bits, that will clear BIT(3) which
 153          * is defined as hardware reset on Spreadtrum's platform and clearing
 154          * it by mistake will lead the card not work. So here we need to work
 155          * around it.
 156          */
 157         if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
 158                 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
 159                         val |= SDHCI_HW_RESET_CARD;
 160         }
 161
 162         writeb_relaxed(val, host->ioaddr + reg);
 163 }
 164
 165 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
 166 {
 167         u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 168
 169         ctrl &= ~SDHCI_CLOCK_CARD_EN;
 170         sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
 171 }
 172
 173 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
 174 {
 175         u16 ctrl;
 176
 177         ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 178         ctrl |= SDHCI_CLOCK_CARD_EN;
 179         sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
 180 }
 181
 182 static inline void
 183 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
 184 {
 185         u32 dll_dly_offset;
 186
 187         dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
 188         if (en)
 189                 dll_dly_offset |= mask;
 190         else
 191                 dll_dly_offset &= ~mask;
 192         sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
 193 }
 194
 195 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
 196 {
 197         u32 div;
 198
 199         /* select 2x clock source */
 200         if (base_clk <= clk * 2)
 201                 return 0;
 202
 203         div = (u32) (base_clk / (clk * 2));
 204
 205         if ((base_clk / div) > (clk * 2))
 206                 div++;
 207
 208         if (div > SDHCI_SPRD_CLK_MAX_DIV)
 209                 div = SDHCI_SPRD_CLK_MAX_DIV;
 210
 211         if (div % 2)
 212                 div = (div + 1) / 2;
 213         else
 214                 div = div / 2;
 215
 216         return div;
 217 }
 218
 219 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
 220                                         unsigned int clk)
 221 {
 222         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 223         u32 div, val, mask;
 224
 225         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 226
 227         div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
 228         div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
 229         sdhci_enable_clk(host, div);
 230
 231         /* enable auto gate sdhc_enable_auto_gate */
 232         val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
 233         mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
 234                SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
 235         if (mask != (val & mask)) {
 236                 val |= mask;
 237                 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
 238         }
 239 }
 240
 241 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
 242 {
 243         u32 tmp;
 244
 245         tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
 246         tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
 247         sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
 248         /* wait 1ms */
 249         usleep_range(1000, 1250);
 250
 251         tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
 252         tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
 253                 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
 254         sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
 255         /* wait 1ms */
 256         usleep_range(1000, 1250);
 257
 258         tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
 259         tmp |= SDHCI_SPRD_DLL_EN;
 260         sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
 261         /* wait 1ms */
 262         usleep_range(1000, 1250);
 263
 264         if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED),
 265                 2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) {
 266                 pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc));
 267                 pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n",
 268                          mmc_hostname(host->mmc),
 269                          sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0),
 270                          sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG));
 271         }
 272 }
 273
 274 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
 275 {
 276         bool en = false, clk_changed = false;
 277
 278         if (clock == 0) {
 279                 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 280         } else if (clock != host->clock) {
 281                 sdhci_sprd_sd_clk_off(host);
 282                 _sdhci_sprd_set_clock(host, clock);
 283
 284                 if (clock <= 400000)
 285                         en = true;
 286                 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
 287                                           SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
 288                 clk_changed = true;
 289         } else {
 290                 _sdhci_sprd_set_clock(host, clock);
 291         }
 292
 293         /*
 294          * According to the Spreadtrum SD host specification, when we changed
 295          * the clock to be more than 52M, we should enable the PHY DLL which
 296          * is used to track the clock frequency to make the clock work more
 297          * stable. Otherwise deviation may occur of the higher clock.
 298          */
 299         if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
 300                 sdhci_sprd_enable_phy_dll(host);
 301 }
 302
 303 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
 304 {
 305         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 306
 307         return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
 308 }
 309
 310 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
 311 {
 312         return 400000;
 313 }
 314
 315 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
 316                                          unsigned int timing)
 317 {
 318         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 319         struct mmc_host *mmc = host->mmc;
 320         u32 *p = sprd_host->phy_delay;
 321         u16 ctrl_2;
 322
 323         if (timing == host->timing)
 324                 return;
 325
 326         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 327         /* Select Bus Speed Mode for host */
 328         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 329         switch (timing) {
 330         case MMC_TIMING_UHS_SDR12:
 331                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 332                 break;
 333         case MMC_TIMING_MMC_HS:
 334         case MMC_TIMING_SD_HS:
 335         case MMC_TIMING_UHS_SDR25:
 336                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 337                 break;
 338         case MMC_TIMING_UHS_SDR50:
 339                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 340                 break;
 341         case MMC_TIMING_UHS_SDR104:
 342                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 343                 break;
 344         case MMC_TIMING_UHS_DDR50:
 345         case MMC_TIMING_MMC_DDR52:
 346                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 347                 break;
 348         case MMC_TIMING_MMC_HS200:
 349                 ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
 350                 break;
 351         case MMC_TIMING_MMC_HS400:
 352                 ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
 353                 break;
 354         default:
 355                 break;
 356         }
 357
 358         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 359
 360         if (!mmc->ios.enhanced_strobe)
 361                 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
 362 }
 363
 364 static void sdhci_sprd_hw_reset(struct sdhci_host *host)
 365 {
 366         int val;
 367
 368         /*
 369          * Note: don't use sdhci_writeb() API here since it is redirected to
 370          * sdhci_sprd_writeb() in which we have a workaround for
 371          * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
 372          * not be cleared.
 373          */
 374         val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
 375         val &= ~SDHCI_HW_RESET_CARD;
 376         writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
 377         /* wait for 10 us */
 378         usleep_range(10, 20);
 379
 380         val |= SDHCI_HW_RESET_CARD;
 381         writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
 382         usleep_range(300, 500);
 383 }
 384
 385 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
 386 {
 387         /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
 388         return 1 << 31;
 389 }
 390
 391 static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
 392 {
 393         return 0;
 394 }
 395
 396 static void sdhci_sprd_request_done(struct sdhci_host *host,
 397                                     struct mmc_request *mrq)
 398 {
 399         /* Validate if the request was from software queue firstly. */
 400         if (mmc_hsq_finalize_request(host->mmc, mrq))
 401                 return;
 402
 403         mmc_request_done(host->mmc, mrq);
 404 }
 405
 406 static struct sdhci_ops sdhci_sprd_ops = {
 407         .read_l = sdhci_sprd_readl,
 408         .write_l = sdhci_sprd_writel,
 409         .write_w = sdhci_sprd_writew,
 410         .write_b = sdhci_sprd_writeb,
 411         .set_clock = sdhci_sprd_set_clock,
 412         .get_max_clock = sdhci_sprd_get_max_clock,
 413         .get_min_clock = sdhci_sprd_get_min_clock,
 414         .set_bus_width = sdhci_set_bus_width,
 415         .reset = sdhci_reset,
 416         .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
 417         .hw_reset = sdhci_sprd_hw_reset,
 418         .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
 419         .get_ro = sdhci_sprd_get_ro,
 420         .request_done = sdhci_sprd_request_done,
 421 };
 422
 423 static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc,
 424                                         struct mmc_request *mrq)
 425 {
 426         struct sdhci_host *host = mmc_priv(mmc);
 427         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 428
 429         host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
 430
 431         /*
 432          * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
 433          * block count register which doesn't support stuff bits of
 434          * CMD23 argument on Spreadtrum's sd host controller.
 435          */
 436         if (host->version >= SDHCI_SPEC_410 &&
 437             mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
 438             (host->flags & SDHCI_AUTO_CMD23))
 439                 host->flags &= ~SDHCI_AUTO_CMD23;
 440 }
 441
 442 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
 443 {
 444         sdhci_sprd_check_auto_cmd23(mmc, mrq);
 445
 446         sdhci_request(mmc, mrq);
 447 }
 448
 449 static int sdhci_sprd_request_atomic(struct mmc_host *mmc,
 450                                      struct mmc_request *mrq)
 451 {
 452         sdhci_sprd_check_auto_cmd23(mmc, mrq);
 453
 454         return sdhci_request_atomic(mmc, mrq);
 455 }
 456
 457 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
 458 {
 459         struct sdhci_host *host = mmc_priv(mmc);
 460         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 461         int ret;
 462
 463         if (!IS_ERR(mmc->supply.vqmmc)) {
 464                 ret = mmc_regulator_set_vqmmc(mmc, ios);
 465                 if (ret < 0) {
 466                         pr_err("%s: Switching signalling voltage failed\n",
 467                                mmc_hostname(mmc));
 468                         return ret;
 469                 }
 470         }
 471
 472         if (IS_ERR(sprd_host->pinctrl))
 473                 return 0;
 474
 475         switch (ios->signal_voltage) {
 476         case MMC_SIGNAL_VOLTAGE_180:
 477                 ret = pinctrl_select_state(sprd_host->pinctrl,
 478                                            sprd_host->pins_uhs);
 479                 if (ret) {
 480                         pr_err("%s: failed to select uhs pin state\n",
 481                                mmc_hostname(mmc));
 482                         return ret;
 483                 }
 484                 break;
 485
 486         default:
 487                 fallthrough;
 488         case MMC_SIGNAL_VOLTAGE_330:
 489                 ret = pinctrl_select_state(sprd_host->pinctrl,
 490                                            sprd_host->pins_default);
 491                 if (ret) {
 492                         pr_err("%s: failed to select default pin state\n",
 493                                mmc_hostname(mmc));
 494                         return ret;
 495                 }
 496                 break;
 497         }
 498
 499         /* Wait for 300 ~ 500 us for pin state stable */
 500         usleep_range(300, 500);
 501         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 502
 503         return 0;
 504 }
 505
 506 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
 507                                              struct mmc_ios *ios)
 508 {
 509         struct sdhci_host *host = mmc_priv(mmc);
 510         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 511         u32 *p = sprd_host->phy_delay;
 512         u16 ctrl_2;
 513
 514         if (!ios->enhanced_strobe)
 515                 return;
 516
 517         sdhci_sprd_sd_clk_off(host);
 518
 519         /* Set HS400 enhanced strobe mode */
 520         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 521         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 522         ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
 523         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 524
 525         sdhci_sprd_sd_clk_on(host);
 526
 527         /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
 528         sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
 529                      SDHCI_SPRD_REG_32_DLL_DLY);
 530 }
 531
 532 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
 533                                        struct device_node *np)
 534 {
 535         u32 *p = sprd_host->phy_delay;
 536         int ret, i, index;
 537         u32 val[4];
 538
 539         for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
 540                 ret = of_property_read_u32_array(np,
 541                                 sdhci_sprd_phy_cfgs[i].property, val, 4);
 542                 if (ret)
 543                         continue;
 544
 545                 index = sdhci_sprd_phy_cfgs[i].timing;
 546                 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
 547         }
 548 }
 549
 550 static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
 551         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 552                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 553                   SDHCI_QUIRK_MISSING_CAPS,
 554         .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
 555                    SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
 556                    SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 557         .ops = &sdhci_sprd_ops,
 558 };
 559
 560 static int sdhci_sprd_probe(struct platform_device *pdev)
 561 {
 562         struct sdhci_host *host;
 563         struct sdhci_sprd_host *sprd_host;
 564         struct mmc_hsq *hsq;
 565         struct clk *clk;
 566         int ret = 0;
 567
 568         host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
 569         if (IS_ERR(host))
 570                 return PTR_ERR(host);
 571
 572         host->dma_mask = DMA_BIT_MASK(64);
 573         pdev->dev.dma_mask = &host->dma_mask;
 574         host->mmc_host_ops.request = sdhci_sprd_request;
 575         host->mmc_host_ops.hs400_enhanced_strobe =
 576                 sdhci_sprd_hs400_enhanced_strobe;
 577         /*
 578          * We can not use the standard ops to change and detect the voltage
 579          * signal for Spreadtrum SD host controller, since our voltage regulator
 580          * for I/O is fixed in hardware, that means we do not need control
 581          * the standard SD host controller to change the I/O voltage.
 582          */
 583         host->mmc_host_ops.start_signal_voltage_switch =
 584                 sdhci_sprd_voltage_switch;
 585
 586         host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
 587                 MMC_CAP_WAIT_WHILE_BUSY;
 588
 589         ret = mmc_of_parse(host->mmc);
 590         if (ret)
 591                 goto pltfm_free;
 592
 593         if (!mmc_card_is_removable(host->mmc))
 594                 host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic;
 595         else
 596                 host->always_defer_done = true;
 597
 598         sprd_host = TO_SPRD_HOST(host);
 599         sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
 600
 601         sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
 602         if (!IS_ERR(sprd_host->pinctrl)) {
 603                 sprd_host->pins_uhs =
 604                         pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
 605                 if (IS_ERR(sprd_host->pins_uhs)) {
 606                         ret = PTR_ERR(sprd_host->pins_uhs);
 607                         goto pltfm_free;
 608                 }
 609
 610                 sprd_host->pins_default =
 611                         pinctrl_lookup_state(sprd_host->pinctrl, "default");
 612                 if (IS_ERR(sprd_host->pins_default)) {
 613                         ret = PTR_ERR(sprd_host->pins_default);
 614                         goto pltfm_free;
 615                 }
 616         }
 617
 618         clk = devm_clk_get(&pdev->dev, "sdio");
 619         if (IS_ERR(clk)) {
 620                 ret = PTR_ERR(clk);
 621                 goto pltfm_free;
 622         }
 623         sprd_host->clk_sdio = clk;
 624         sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
 625         if (!sprd_host->base_rate)
 626                 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
 627
 628         clk = devm_clk_get(&pdev->dev, "enable");
 629         if (IS_ERR(clk)) {
 630                 ret = PTR_ERR(clk);
 631                 goto pltfm_free;
 632         }
 633         sprd_host->clk_enable = clk;
 634
 635         clk = devm_clk_get(&pdev->dev, "2x_enable");
 636         if (!IS_ERR(clk))
 637                 sprd_host->clk_2x_enable = clk;
 638
 639         ret = clk_prepare_enable(sprd_host->clk_sdio);
 640         if (ret)
 641                 goto pltfm_free;
 642
 643         ret = clk_prepare_enable(sprd_host->clk_enable);
 644         if (ret)
 645                 goto clk_disable;
 646
 647         ret = clk_prepare_enable(sprd_host->clk_2x_enable);
 648         if (ret)
 649                 goto clk_disable2;
 650
 651         sdhci_sprd_init_config(host);
 652         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 653         sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
 654                                SDHCI_VENDOR_VER_SHIFT);
 655
 656         pm_runtime_get_noresume(&pdev->dev);
 657         pm_runtime_set_active(&pdev->dev);
 658         pm_runtime_enable(&pdev->dev);
 659         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 660         pm_runtime_use_autosuspend(&pdev->dev);
 661         pm_suspend_ignore_children(&pdev->dev, 1);
 662
 663         sdhci_enable_v4_mode(host);
 664
 665         /*
 666          * Supply the existing CAPS, but clear the UHS-I modes. This
 667          * will allow these modes to be specified only by device
 668          * tree properties through mmc_of_parse().
 669          */
 670         host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 671         host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 672         host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
 673                          SDHCI_SUPPORT_DDR50);
 674
 675         ret = sdhci_setup_host(host);
 676         if (ret)
 677                 goto pm_runtime_disable;
 678
 679         sprd_host->flags = host->flags;
 680
 681         hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
 682         if (!hsq) {
 683                 ret = -ENOMEM;
 684                 goto err_cleanup_host;
 685         }
 686
 687         ret = mmc_hsq_init(hsq, host->mmc);
 688         if (ret)
 689                 goto err_cleanup_host;
 690
 691         ret = __sdhci_add_host(host);
 692         if (ret)
 693                 goto err_cleanup_host;
 694
 695         pm_runtime_mark_last_busy(&pdev->dev);
 696         pm_runtime_put_autosuspend(&pdev->dev);
 697
 698         return 0;
 699
 700 err_cleanup_host:
 701         sdhci_cleanup_host(host);
 702
 703 pm_runtime_disable:
 704         pm_runtime_put_noidle(&pdev->dev);
 705         pm_runtime_disable(&pdev->dev);
 706         pm_runtime_set_suspended(&pdev->dev);
 707
 708         clk_disable_unprepare(sprd_host->clk_2x_enable);
 709
 710 clk_disable2:
 711         clk_disable_unprepare(sprd_host->clk_enable);
 712
 713 clk_disable:
 714         clk_disable_unprepare(sprd_host->clk_sdio);
 715
 716 pltfm_free:
 717         sdhci_pltfm_free(pdev);
 718         return ret;
 719 }
 720
 721 static int sdhci_sprd_remove(struct platform_device *pdev)
 722 {
 723         struct sdhci_host *host = platform_get_drvdata(pdev);
 724         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 725
 726         sdhci_remove_host(host, 0);
 727
 728         clk_disable_unprepare(sprd_host->clk_sdio);
 729         clk_disable_unprepare(sprd_host->clk_enable);
 730         clk_disable_unprepare(sprd_host->clk_2x_enable);
 731
 732         sdhci_pltfm_free(pdev);
 733
 734         return 0;
 735 }
 736
 737 static const struct of_device_id sdhci_sprd_of_match[] = {
 738         { .compatible = "sprd,sdhci-r11", },
 739         { }
 740 };
 741 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
 742
 743 #ifdef CONFIG_PM
 744 static int sdhci_sprd_runtime_suspend(struct device *dev)
 745 {
 746         struct sdhci_host *host = dev_get_drvdata(dev);
 747         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 748
 749         mmc_hsq_suspend(host->mmc);
 750         sdhci_runtime_suspend_host(host);
 751
 752         clk_disable_unprepare(sprd_host->clk_sdio);
 753         clk_disable_unprepare(sprd_host->clk_enable);
 754         clk_disable_unprepare(sprd_host->clk_2x_enable);
 755
 756         return 0;
 757 }
 758
 759 static int sdhci_sprd_runtime_resume(struct device *dev)
 760 {
 761         struct sdhci_host *host = dev_get_drvdata(dev);
 762         struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
 763         int ret;
 764
 765         ret = clk_prepare_enable(sprd_host->clk_2x_enable);
 766         if (ret)
 767                 return ret;
 768
 769         ret = clk_prepare_enable(sprd_host->clk_enable);
 770         if (ret)
 771                 goto clk_2x_disable;
 772
 773         ret = clk_prepare_enable(sprd_host->clk_sdio);
 774         if (ret)
 775                 goto clk_disable;
 776
 777         sdhci_runtime_resume_host(host, 1);
 778         mmc_hsq_resume(host->mmc);
 779
 780         return 0;
 781
 782 clk_disable:
 783         clk_disable_unprepare(sprd_host->clk_enable);
 784
 785 clk_2x_disable:
 786         clk_disable_unprepare(sprd_host->clk_2x_enable);
 787
 788         return ret;
 789 }
 790 #endif
 791
 792 static const struct dev_pm_ops sdhci_sprd_pm_ops = {
 793         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 794                                 pm_runtime_force_resume)
 795         SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
 796                            sdhci_sprd_runtime_resume, NULL)
 797 };
 798
 799 static struct platform_driver sdhci_sprd_driver = {
 800         .probe = sdhci_sprd_probe,
 801         .remove = sdhci_sprd_remove,
 802         .driver = {
 803                 .name = "sdhci_sprd_r11",
 804                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 805                 .of_match_table = sdhci_sprd_of_match,
 806                 .pm = &sdhci_sprd_pm_ops,
 807         },
 808 };
 809 module_platform_driver(sdhci_sprd_driver);
 810
 811 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
 812 MODULE_LICENSE("GPL v2");
 813 MODULE_ALIAS("platform:sdhci-sprd-r11");