drivers/mmc/host/sdhci-pxav3.c

   1 /*
   2  * Copyright (C) 2010 Marvell International Ltd.
   3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
   4  *              Kevin Wang <dwang4@marvell.com>
   5  *              Mingwei Wang <mwwang@marvell.com>
   6  *              Philip Rakity <prakity@marvell.com>
   7  *              Mark Brown <markb@marvell.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/mmc/card.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/platform_data/pxa_sdhci.h>
  27 #include <linux/slab.h>
  28 #include <linux/delay.h>
  29 #include <linux/module.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/pm.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/mbus.h>
  35
  36 #include "sdhci.h"
  37 #include "sdhci-pltfm.h"
  38
  39 #define PXAV3_RPM_DELAY_MS     50
  40
  41 #define SD_CLOCK_BURST_SIZE_SETUP               0x10A
  42 #define SDCLK_SEL       0x100
  43 #define SDCLK_DELAY_SHIFT       9
  44 #define SDCLK_DELAY_MASK        0x1f
  45
  46 #define SD_CFG_FIFO_PARAM       0x100
  47 #define SDCFG_GEN_PAD_CLK_ON    (1<<6)
  48 #define SDCFG_GEN_PAD_CLK_CNT_MASK      0xFF
  49 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT     24
  50
  51 #define SD_SPI_MODE          0x108
  52 #define SD_CE_ATA_1          0x10C
  53
  54 #define SD_CE_ATA_2          0x10E
  55 #define SDCE_MISC_INT           (1<<2)
  56 #define SDCE_MISC_INT_EN        (1<<1)
  57
  58 struct sdhci_pxa {
  59         struct clk *clk_core;
  60         struct clk *clk_io;
  61         u8      power_mode;
  62         void __iomem *sdio3_conf_reg;
  63 };
  64
  65 /*
  66  * These registers are relative to the second register region, for the
  67  * MBus bridge.
  68  */
  69 #define SDHCI_WINDOW_CTRL(i)    (0x80 + ((i) << 3))
  70 #define SDHCI_WINDOW_BASE(i)    (0x84 + ((i) << 3))
  71 #define SDHCI_MAX_WIN_NUM       8
  72
  73 /*
  74  * Fields below belong to SDIO3 Configuration Register (third register
  75  * region for the Armada 38x flavor)
  76  */
  77
  78 #define SDIO3_CONF_CLK_INV      BIT(0)
  79 #define SDIO3_CONF_SD_FB_CLK    BIT(2)
  80
  81 static int mv_conf_mbus_windows(struct platform_device *pdev,
  82                                 const struct mbus_dram_target_info *dram)
  83 {
  84         int i;
  85         void __iomem *regs;
  86         struct resource *res;
  87
  88         if (!dram) {
  89                 dev_err(&pdev->dev, "no mbus dram info\n");
  90                 return -EINVAL;
  91         }
  92
  93         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  94         if (!res) {
  95                 dev_err(&pdev->dev, "cannot get mbus registers\n");
  96                 return -EINVAL;
  97         }
  98
  99         regs = ioremap(res->start, resource_size(res));
 100         if (!regs) {
 101                 dev_err(&pdev->dev, "cannot map mbus registers\n");
 102                 return -ENOMEM;
 103         }
 104
 105         for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
 106                 writel(0, regs + SDHCI_WINDOW_CTRL(i));
 107                 writel(0, regs + SDHCI_WINDOW_BASE(i));
 108         }
 109
 110         for (i = 0; i < dram->num_cs; i++) {
 111                 const struct mbus_dram_window *cs = dram->cs + i;
 112
 113                 /* Write size, attributes and target id to control register */
 114                 writel(((cs->size - 1) & 0xffff0000) |
 115                         (cs->mbus_attr << 8) |
 116                         (dram->mbus_dram_target_id << 4) | 1,
 117                         regs + SDHCI_WINDOW_CTRL(i));
 118                 /* Write base address to base register */
 119                 writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
 120         }
 121
 122         iounmap(regs);
 123
 124         return 0;
 125 }
 126
 127 static int armada_38x_quirks(struct platform_device *pdev,
 128                              struct sdhci_host *host)
 129 {
 130         struct device_node *np = pdev->dev.of_node;
 131         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 132         struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
 133         struct resource *res;
 134
 135         host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
 136         host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
 137
 138         host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 139         host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 140
 141         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 142                                            "conf-sdio3");
 143         if (res) {
 144                 pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
 145                 if (IS_ERR(pxa->sdio3_conf_reg))
 146                         return PTR_ERR(pxa->sdio3_conf_reg);
 147         } else {
 148                 /*
 149                  * According to erratum 'FE-2946959' both SDR50 and DDR50
 150                  * modes require specific clock adjustments in SDIO3
 151                  * Configuration register, if the adjustment is not done,
 152                  * remove them from the capabilities.
 153                  */
 154                 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
 155
 156                 dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
 157         }
 158
 159         /*
 160          * According to erratum 'ERR-7878951' Armada 38x SDHCI
 161          * controller has different capabilities than the ones shown
 162          * in its registers
 163          */
 164         if (of_property_read_bool(np, "no-1-8-v")) {
 165                 host->caps &= ~SDHCI_CAN_VDD_180;
 166                 host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
 167         } else {
 168                 host->caps &= ~SDHCI_CAN_VDD_330;
 169         }
 170         host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
 171
 172         return 0;
 173 }
 174
 175 static void pxav3_reset(struct sdhci_host *host, u8 mask)
 176 {
 177         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
 178         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 179
 180         sdhci_reset(host, mask);
 181
 182         if (mask == SDHCI_RESET_ALL) {
 183                 /*
 184                  * tune timing of read data/command when crc error happen
 185                  * no performance impact
 186                  */
 187                 if (pdata && 0 != pdata->clk_delay_cycles) {
 188                         u16 tmp;
 189
 190                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 191                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
 192                                 << SDCLK_DELAY_SHIFT;
 193                         tmp |= SDCLK_SEL;
 194                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 195                 }
 196         }
 197 }
 198
 199 #define MAX_WAIT_COUNT 5
 200 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 201 {
 202         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 203         struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
 204         u16 tmp;
 205         int count;
 206
 207         if (pxa->power_mode == MMC_POWER_UP
 208                         && power_mode == MMC_POWER_ON) {
 209
 210                 dev_dbg(mmc_dev(host->mmc),
 211                                 "%s: slot->power_mode = %d,"
 212                                 "ios->power_mode = %d\n",
 213                                 __func__,
 214                                 pxa->power_mode,
 215                                 power_mode);
 216
 217                 /* set we want notice of when 74 clocks are sent */
 218                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 219                 tmp |= SDCE_MISC_INT_EN;
 220                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 221
 222                 /* start sending the 74 clocks */
 223                 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
 224                 tmp |= SDCFG_GEN_PAD_CLK_ON;
 225                 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
 226
 227                 /* slowest speed is about 100KHz or 10usec per clock */
 228                 udelay(740);
 229                 count = 0;
 230
 231                 while (count++ < MAX_WAIT_COUNT) {
 232                         if ((readw(host->ioaddr + SD_CE_ATA_2)
 233                                                 & SDCE_MISC_INT) == 0)
 234                                 break;
 235                         udelay(10);
 236                 }
 237
 238                 if (count == MAX_WAIT_COUNT)
 239                         dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
 240
 241                 /* clear the interrupt bit if posted */
 242                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 243                 tmp |= SDCE_MISC_INT;
 244                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 245         }
 246         pxa->power_mode = power_mode;
 247 }
 248
 249 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 250 {
 251         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 252         struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
 253         u16 ctrl_2;
 254
 255         /*
 256          * Set V18_EN -- UHS modes do not work without this.
 257          * does not change signaling voltage
 258          */
 259         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 260
 261         /* Select Bus Speed Mode for host */
 262         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 263         switch (uhs) {
 264         case MMC_TIMING_UHS_SDR12:
 265                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 266                 break;
 267         case MMC_TIMING_UHS_SDR25:
 268                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 269                 break;
 270         case MMC_TIMING_UHS_SDR50:
 271                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
 272                 break;
 273         case MMC_TIMING_UHS_SDR104:
 274                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
 275                 break;
 276         case MMC_TIMING_MMC_DDR52:
 277         case MMC_TIMING_UHS_DDR50:
 278                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
 279                 break;
 280         }
 281
 282         /*
 283          * Update SDIO3 Configuration register according to erratum
 284          * FE-2946959
 285          */
 286         if (pxa->sdio3_conf_reg) {
 287                 u8 reg_val  = readb(pxa->sdio3_conf_reg);
 288
 289                 if (uhs == MMC_TIMING_UHS_SDR50 ||
 290                     uhs == MMC_TIMING_UHS_DDR50) {
 291                         reg_val &= ~SDIO3_CONF_CLK_INV;
 292                         reg_val |= SDIO3_CONF_SD_FB_CLK;
 293                 } else if (uhs == MMC_TIMING_MMC_HS) {
 294                         reg_val &= ~SDIO3_CONF_CLK_INV;
 295                         reg_val &= ~SDIO3_CONF_SD_FB_CLK;
 296                 } else {
 297                         reg_val |= SDIO3_CONF_CLK_INV;
 298                         reg_val &= ~SDIO3_CONF_SD_FB_CLK;
 299                 }
 300                 writeb(reg_val, pxa->sdio3_conf_reg);
 301         }
 302
 303         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 304         dev_dbg(mmc_dev(host->mmc),
 305                 "%s uhs = %d, ctrl_2 = %04X\n",
 306                 __func__, uhs, ctrl_2);
 307 }
 308
 309 static void pxav3_set_power(struct sdhci_host *host, unsigned char mode,
 310                             unsigned short vdd)
 311 {
 312         struct mmc_host *mmc = host->mmc;
 313         u8 pwr = host->pwr;
 314
 315         sdhci_set_power_noreg(host, mode, vdd);
 316
 317         if (host->pwr == pwr)
 318                 return;
 319
 320         if (host->pwr == 0)
 321                 vdd = 0;
 322
 323         if (!IS_ERR(mmc->supply.vmmc))
 324                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 325 }
 326
 327 static const struct sdhci_ops pxav3_sdhci_ops = {
 328         .set_clock = sdhci_set_clock,
 329         .set_power = pxav3_set_power,
 330         .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
 331         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 332         .set_bus_width = sdhci_set_bus_width,
 333         .reset = pxav3_reset,
 334         .set_uhs_signaling = pxav3_set_uhs_signaling,
 335 };
 336
 337 static const struct sdhci_pltfm_data sdhci_pxav3_pdata = {
 338         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
 339                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 340                 | SDHCI_QUIRK_32BIT_ADMA_SIZE
 341                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 342         .ops = &pxav3_sdhci_ops,
 343 };
 344
 345 #ifdef CONFIG_OF
 346 static const struct of_device_id sdhci_pxav3_of_match[] = {
 347         {
 348                 .compatible = "mrvl,pxav3-mmc",
 349         },
 350         {
 351                 .compatible = "marvell,armada-380-sdhci",
 352         },
 353         {},
 354 };
 355 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
 356
 357 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 358 {
 359         struct sdhci_pxa_platdata *pdata;
 360         struct device_node *np = dev->of_node;
 361         u32 clk_delay_cycles;
 362
 363         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 364         if (!pdata)
 365                 return NULL;
 366
 367         if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
 368                                   &clk_delay_cycles))
 369                 pdata->clk_delay_cycles = clk_delay_cycles;
 370
 371         return pdata;
 372 }
 373 #else
 374 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 375 {
 376         return NULL;
 377 }
 378 #endif
 379
 380 static int sdhci_pxav3_probe(struct platform_device *pdev)
 381 {
 382         struct sdhci_pltfm_host *pltfm_host;
 383         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 384         struct device *dev = &pdev->dev;
 385         struct device_node *np = pdev->dev.of_node;
 386         struct sdhci_host *host = NULL;
 387         struct sdhci_pxa *pxa = NULL;
 388         const struct of_device_id *match;
 389         int ret;
 390
 391         host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, sizeof(*pxa));
 392         if (IS_ERR(host))
 393                 return PTR_ERR(host);
 394
 395         pltfm_host = sdhci_priv(host);
 396         pxa = sdhci_pltfm_priv(pltfm_host);
 397
 398         pxa->clk_io = devm_clk_get(dev, "io");
 399         if (IS_ERR(pxa->clk_io))
 400                 pxa->clk_io = devm_clk_get(dev, NULL);
 401         if (IS_ERR(pxa->clk_io)) {
 402                 dev_err(dev, "failed to get io clock\n");
 403                 ret = PTR_ERR(pxa->clk_io);
 404                 goto err_clk_get;
 405         }
 406         pltfm_host->clk = pxa->clk_io;
 407         clk_prepare_enable(pxa->clk_io);
 408
 409         pxa->clk_core = devm_clk_get(dev, "core");
 410         if (!IS_ERR(pxa->clk_core))
 411                 clk_prepare_enable(pxa->clk_core);
 412
 413         /* enable 1/8V DDR capable */
 414         host->mmc->caps |= MMC_CAP_1_8V_DDR;
 415
 416         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
 417                 ret = armada_38x_quirks(pdev, host);
 418                 if (ret < 0)
 419                         goto err_mbus_win;
 420                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
 421                 if (ret < 0)
 422                         goto err_mbus_win;
 423         }
 424
 425         match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
 426         if (match) {
 427                 ret = mmc_of_parse(host->mmc);
 428                 if (ret)
 429                         goto err_of_parse;
 430                 sdhci_get_of_property(pdev);
 431                 pdata = pxav3_get_mmc_pdata(dev);
 432                 pdev->dev.platform_data = pdata;
 433         } else if (pdata) {
 434                 /* on-chip device */
 435                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
 436                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
 437
 438                 /* If slot design supports 8 bit data, indicate this to MMC. */
 439                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
 440                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 441
 442                 if (pdata->quirks)
 443                         host->quirks |= pdata->quirks;
 444                 if (pdata->quirks2)
 445                         host->quirks2 |= pdata->quirks2;
 446                 if (pdata->host_caps)
 447                         host->mmc->caps |= pdata->host_caps;
 448                 if (pdata->host_caps2)
 449                         host->mmc->caps2 |= pdata->host_caps2;
 450                 if (pdata->pm_caps)
 451                         host->mmc->pm_caps |= pdata->pm_caps;
 452         }
 453
 454         pm_runtime_get_noresume(&pdev->dev);
 455         pm_runtime_set_active(&pdev->dev);
 456         pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
 457         pm_runtime_use_autosuspend(&pdev->dev);
 458         pm_runtime_enable(&pdev->dev);
 459         pm_suspend_ignore_children(&pdev->dev, 1);
 460
 461         ret = sdhci_add_host(host);
 462         if (ret)
 463                 goto err_add_host;
 464
 465         if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
 466                 device_init_wakeup(&pdev->dev, 1);
 467
 468         pm_runtime_put_autosuspend(&pdev->dev);
 469
 470         return 0;
 471
 472 err_add_host:
 473         pm_runtime_disable(&pdev->dev);
 474         pm_runtime_put_noidle(&pdev->dev);
 475 err_of_parse:
 476 err_mbus_win:
 477         clk_disable_unprepare(pxa->clk_io);
 478         clk_disable_unprepare(pxa->clk_core);
 479 err_clk_get:
 480         sdhci_pltfm_free(pdev);
 481         return ret;
 482 }
 483
 484 static int sdhci_pxav3_remove(struct platform_device *pdev)
 485 {
 486         struct sdhci_host *host = platform_get_drvdata(pdev);
 487         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 488         struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
 489
 490         pm_runtime_get_sync(&pdev->dev);
 491         pm_runtime_disable(&pdev->dev);
 492         pm_runtime_put_noidle(&pdev->dev);
 493
 494         sdhci_remove_host(host, 1);
 495
 496         clk_disable_unprepare(pxa->clk_io);
 497         clk_disable_unprepare(pxa->clk_core);
 498
 499         sdhci_pltfm_free(pdev);
 500
 501         return 0;
 502 }
 503
 504 #ifdef CONFIG_PM_SLEEP
 505 static int sdhci_pxav3_suspend(struct device *dev)
 506 {
 507         int ret;
 508         struct sdhci_host *host = dev_get_drvdata(dev);
 509
 510         pm_runtime_get_sync(dev);
 511         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 512                 mmc_retune_needed(host->mmc);
 513         ret = sdhci_suspend_host(host);
 514         pm_runtime_mark_last_busy(dev);
 515         pm_runtime_put_autosuspend(dev);
 516
 517         return ret;
 518 }
 519
 520 static int sdhci_pxav3_resume(struct device *dev)
 521 {
 522         int ret;
 523         struct sdhci_host *host = dev_get_drvdata(dev);
 524
 525         pm_runtime_get_sync(dev);
 526         ret = sdhci_resume_host(host);
 527         pm_runtime_mark_last_busy(dev);
 528         pm_runtime_put_autosuspend(dev);
 529
 530         return ret;
 531 }
 532 #endif
 533
 534 #ifdef CONFIG_PM
 535 static int sdhci_pxav3_runtime_suspend(struct device *dev)
 536 {
 537         struct sdhci_host *host = dev_get_drvdata(dev);
 538         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 539         struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
 540         int ret;
 541
 542         ret = sdhci_runtime_suspend_host(host);
 543         if (ret)
 544                 return ret;
 545
 546         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 547                 mmc_retune_needed(host->mmc);
 548
 549         clk_disable_unprepare(pxa->clk_io);
 550         if (!IS_ERR(pxa->clk_core))
 551                 clk_disable_unprepare(pxa->clk_core);
 552
 553         return 0;
 554 }
 555
 556 static int sdhci_pxav3_runtime_resume(struct device *dev)
 557 {
 558         struct sdhci_host *host = dev_get_drvdata(dev);
 559         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 560         struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
 561
 562         clk_prepare_enable(pxa->clk_io);
 563         if (!IS_ERR(pxa->clk_core))
 564                 clk_prepare_enable(pxa->clk_core);
 565
 566         return sdhci_runtime_resume_host(host);
 567 }
 568 #endif
 569
 570 static const struct dev_pm_ops sdhci_pxav3_pmops = {
 571         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
 572         SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
 573                 sdhci_pxav3_runtime_resume, NULL)
 574 };
 575
 576 static struct platform_driver sdhci_pxav3_driver = {
 577         .driver         = {
 578                 .name   = "sdhci-pxav3",
 579                 .of_match_table = of_match_ptr(sdhci_pxav3_of_match),
 580                 .pm     = &sdhci_pxav3_pmops,
 581         },
 582         .probe          = sdhci_pxav3_probe,
 583         .remove         = sdhci_pxav3_remove,
 584 };
 585
 586 module_platform_driver(sdhci_pxav3_driver);
 587
 588 MODULE_DESCRIPTION("SDHCI driver for pxav3");
 589 MODULE_AUTHOR("Marvell International Ltd.");
 590 MODULE_LICENSE("GPL v2");
 591