drivers/mmc/host/sdhci-pci-o2micro.c

   1 /*
   2  * Copyright (C) 2013 BayHub Technology Ltd.
   3  *
   4  * Authors: Peter Guo <peter.guo@bayhubtech.com>
   5  *          Adam Lee <adam.lee@canonical.com>
   6  *          Ernest Zhang <ernest.zhang@bayhubtech.com>
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/pci.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/mmc.h>
  22 #include <linux/delay.h>
  23
  24 #include "sdhci.h"
  25 #include "sdhci-pci.h"
  26
  27 /*
  28  * O2Micro device registers
  29  */
  30
  31 #define O2_SD_MISC_REG5         0x64
  32 #define O2_SD_LD0_CTRL          0x68
  33 #define O2_SD_DEV_CTRL          0x88
  34 #define O2_SD_LOCK_WP           0xD3
  35 #define O2_SD_TEST_REG          0xD4
  36 #define O2_SD_FUNC_REG0         0xDC
  37 #define O2_SD_MULTI_VCC3V       0xEE
  38 #define O2_SD_CLKREQ            0xEC
  39 #define O2_SD_CAPS              0xE0
  40 #define O2_SD_ADMA1             0xE2
  41 #define O2_SD_ADMA2             0xE7
  42 #define O2_SD_INF_MOD           0xF1
  43 #define O2_SD_MISC_CTRL4        0xFC
  44 #define O2_SD_TUNING_CTRL       0x300
  45 #define O2_SD_PLL_SETTING       0x304
  46 #define O2_SD_MISC_SETTING      0x308
  47 #define O2_SD_CLK_SETTING       0x328
  48 #define O2_SD_CAP_REG2          0x330
  49 #define O2_SD_CAP_REG0          0x334
  50 #define O2_SD_UHS1_CAP_SETTING  0x33C
  51 #define O2_SD_DELAY_CTRL        0x350
  52 #define O2_SD_UHS2_L1_CTRL      0x35C
  53 #define O2_SD_FUNC_REG3         0x3E0
  54 #define O2_SD_FUNC_REG4         0x3E4
  55 #define O2_SD_LED_ENABLE        BIT(6)
  56 #define O2_SD_FREG0_LEDOFF      BIT(13)
  57 #define O2_SD_FREG4_ENABLE_CLK_SET      BIT(22)
  58
  59 #define O2_SD_VENDOR_SETTING    0x110
  60 #define O2_SD_VENDOR_SETTING2   0x1C8
  61 #define O2_SD_HW_TUNING_DISABLE BIT(4)
  62
  63 #define O2_PLL_WDT_CONTROL1     0x1CC
  64 #define  O2_PLL_FORCE_ACTIVE    BIT(18)
  65 #define  O2_PLL_LOCK_STATUS     BIT(14)
  66 #define  O2_PLL_SOFT_RESET      BIT(12)
  67
  68 #define O2_SD_DETECT_SETTING 0x324
  69
  70 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
  71 {
  72         u16 reg;
  73
  74         /* enable hardware tuning */
  75         reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
  76         reg &= ~O2_SD_HW_TUNING_DISABLE;
  77         sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
  78 }
  79
  80 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
  81 {
  82         int i;
  83
  84         sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200);
  85
  86         for (i = 0; i < 150; i++) {
  87                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  88
  89                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
  90                         if (ctrl & SDHCI_CTRL_TUNED_CLK) {
  91                                 host->tuning_done = true;
  92                                 return;
  93                         }
  94                         pr_warn("%s: HW tuning failed !\n",
  95                                 mmc_hostname(host->mmc));
  96                         break;
  97                 }
  98
  99                 mdelay(1);
 100         }
 101
 102         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
 103                 mmc_hostname(host->mmc));
 104         sdhci_reset_tuning(host);
 105 }
 106
 107 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
 108 {
 109         struct sdhci_host *host = mmc_priv(mmc);
 110         int current_bus_width = 0;
 111
 112         /*
 113          * This handler only implements the eMMC tuning that is specific to
 114          * this controller.  Fall back to the standard method for other TIMING.
 115          */
 116         if (host->timing != MMC_TIMING_MMC_HS200)
 117                 return sdhci_execute_tuning(mmc, opcode);
 118
 119         if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
 120                 return -EINVAL;
 121
 122         /*
 123          * o2 sdhci host didn't support 8bit emmc tuning
 124          */
 125         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
 126                 current_bus_width = mmc->ios.bus_width;
 127                 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
 128         }
 129
 130         sdhci_o2_set_tuning_mode(host);
 131
 132         sdhci_start_tuning(host);
 133
 134         __sdhci_o2_execute_tuning(host, opcode);
 135
 136         sdhci_end_tuning(host);
 137
 138         if (current_bus_width == MMC_BUS_WIDTH_8)
 139                 sdhci_set_bus_width(host, current_bus_width);
 140
 141         host->flags &= ~SDHCI_HS400_TUNING;
 142         return 0;
 143 }
 144
 145 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
 146 {
 147         u32 scratch_32;
 148         pci_read_config_dword(chip->pdev,
 149                               O2_SD_PLL_SETTING, &scratch_32);
 150
 151         scratch_32 &= 0x0000FFFF;
 152         scratch_32 |= value;
 153
 154         pci_write_config_dword(chip->pdev,
 155                                O2_SD_PLL_SETTING, scratch_32);
 156 }
 157
 158 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
 159 {
 160         int ret;
 161         u32 scratch_32;
 162
 163         /* Set led of SD host function enable */
 164         ret = pci_read_config_dword(chip->pdev,
 165                                     O2_SD_FUNC_REG0, &scratch_32);
 166         if (ret)
 167                 return;
 168
 169         scratch_32 &= ~O2_SD_FREG0_LEDOFF;
 170         pci_write_config_dword(chip->pdev,
 171                                O2_SD_FUNC_REG0, scratch_32);
 172
 173         ret = pci_read_config_dword(chip->pdev,
 174                                     O2_SD_TEST_REG, &scratch_32);
 175         if (ret)
 176                 return;
 177
 178         scratch_32 |= O2_SD_LED_ENABLE;
 179         pci_write_config_dword(chip->pdev,
 180                                O2_SD_TEST_REG, scratch_32);
 181
 182 }
 183
 184 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
 185 {
 186         u32 scratch_32;
 187         int ret;
 188         /* Improve write performance for SD3.0 */
 189         ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
 190         if (ret)
 191                 return;
 192         scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
 193         pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
 194
 195         /* Enable Link abnormal reset generating Reset */
 196         ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
 197         if (ret)
 198                 return;
 199         scratch_32 &= ~((1 << 19) | (1 << 11));
 200         scratch_32 |= (1 << 10);
 201         pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
 202
 203         /* set card power over current protection */
 204         ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
 205         if (ret)
 206                 return;
 207         scratch_32 |= (1 << 4);
 208         pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
 209
 210         /* adjust the output delay for SD mode */
 211         pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
 212
 213         /* Set the output voltage setting of Aux 1.2v LDO */
 214         ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
 215         if (ret)
 216                 return;
 217         scratch_32 &= ~(3 << 12);
 218         pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
 219
 220         /* Set Max power supply capability of SD host */
 221         ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
 222         if (ret)
 223                 return;
 224         scratch_32 &= ~(0x01FE);
 225         scratch_32 |= 0x00CC;
 226         pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
 227         /* Set DLL Tuning Window */
 228         ret = pci_read_config_dword(chip->pdev,
 229                                     O2_SD_TUNING_CTRL, &scratch_32);
 230         if (ret)
 231                 return;
 232         scratch_32 &= ~(0x000000FF);
 233         scratch_32 |= 0x00000066;
 234         pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
 235
 236         /* Set UHS2 T_EIDLE */
 237         ret = pci_read_config_dword(chip->pdev,
 238                                     O2_SD_UHS2_L1_CTRL, &scratch_32);
 239         if (ret)
 240                 return;
 241         scratch_32 &= ~(0x000000FC);
 242         scratch_32 |= 0x00000084;
 243         pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
 244
 245         /* Set UHS2 Termination */
 246         ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
 247         if (ret)
 248                 return;
 249         scratch_32 &= ~((1 << 21) | (1 << 30));
 250
 251         pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
 252
 253         /* Set L1 Entrance Timer */
 254         ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
 255         if (ret)
 256                 return;
 257         scratch_32 &= ~(0xf0000000);
 258         scratch_32 |= 0x30000000;
 259         pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
 260
 261         ret = pci_read_config_dword(chip->pdev,
 262                                     O2_SD_MISC_CTRL4, &scratch_32);
 263         if (ret)
 264                 return;
 265         scratch_32 &= ~(0x000f0000);
 266         scratch_32 |= 0x00080000;
 267         pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
 268 }
 269
 270 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
 271                                     struct sdhci_host *host)
 272 {
 273         int ret;
 274
 275         ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
 276         if (!ret) {
 277                 pr_info("%s: unsupport msi, use INTx irq\n",
 278                         mmc_hostname(host->mmc));
 279                 return;
 280         }
 281
 282         ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
 283                                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
 284         if (ret < 0) {
 285                 pr_err("%s: enable PCI MSI failed, err=%d\n",
 286                        mmc_hostname(host->mmc), ret);
 287                 return;
 288         }
 289
 290         host->irq = pci_irq_vector(chip->pdev, 0);
 291 }
 292
 293 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
 294 {
 295         ktime_t timeout;
 296         u32 scratch32;
 297
 298         /* Wait max 50 ms */
 299         timeout = ktime_add_ms(ktime_get(), 50);
 300         while (1) {
 301                 bool timedout = ktime_after(ktime_get(), timeout);
 302
 303                 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
 304                 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
 305                     == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
 306                         break;
 307
 308                 if (timedout) {
 309                         pr_err("%s: Card Detect debounce never finished.\n",
 310                                mmc_hostname(host->mmc));
 311                         sdhci_dumpregs(host);
 312                         return;
 313                 }
 314                 udelay(10);
 315         }
 316 }
 317
 318 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
 319 {
 320         ktime_t timeout;
 321         u16 scratch;
 322         u32 scratch32;
 323
 324         /* PLL software reset */
 325         scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
 326         scratch32 |= O2_PLL_SOFT_RESET;
 327         sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
 328         udelay(1);
 329         scratch32 &= ~(O2_PLL_SOFT_RESET);
 330         sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
 331
 332         /* PLL force active */
 333         scratch32 |= O2_PLL_FORCE_ACTIVE;
 334         sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
 335
 336         /* Wait max 20 ms */
 337         timeout = ktime_add_ms(ktime_get(), 20);
 338         while (1) {
 339                 bool timedout = ktime_after(ktime_get(), timeout);
 340
 341                 scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1);
 342                 if (scratch & O2_PLL_LOCK_STATUS)
 343                         break;
 344                 if (timedout) {
 345                         pr_err("%s: Internal clock never stabilised.\n",
 346                                mmc_hostname(host->mmc));
 347                         sdhci_dumpregs(host);
 348                         goto out;
 349                 }
 350                 udelay(10);
 351         }
 352
 353         /* Wait for card detect finish */
 354         udelay(1);
 355         sdhci_o2_wait_card_detect_stable(host);
 356
 357 out:
 358         /* Cancel PLL force active */
 359         scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
 360         scratch32 &= ~O2_PLL_FORCE_ACTIVE;
 361         sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
 362 }
 363
 364 static int sdhci_o2_get_cd(struct mmc_host *mmc)
 365 {
 366         struct sdhci_host *host = mmc_priv(mmc);
 367
 368         sdhci_o2_enable_internal_clock(host);
 369
 370         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
 371 }
 372
 373 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
 374 {
 375         /* Enable internal clock */
 376         clk |= SDHCI_CLOCK_INT_EN;
 377         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 378
 379         if (sdhci_o2_get_cd(host->mmc)) {
 380                 clk |= SDHCI_CLOCK_CARD_EN;
 381                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 382         }
 383 }
 384
 385 void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
 386 {
 387         u16 clk;
 388
 389         host->mmc->actual_clock = 0;
 390
 391         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 392
 393         if (clock == 0)
 394                 return;
 395
 396         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
 397         sdhci_o2_enable_clk(host, clk);
 398 }
 399
 400 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
 401 {
 402         struct sdhci_pci_chip *chip;
 403         struct sdhci_host *host;
 404         u32 reg;
 405         int ret;
 406
 407         chip = slot->chip;
 408         host = slot->host;
 409         switch (chip->pdev->device) {
 410         case PCI_DEVICE_ID_O2_SDS0:
 411         case PCI_DEVICE_ID_O2_SEABIRD0:
 412         case PCI_DEVICE_ID_O2_SEABIRD1:
 413         case PCI_DEVICE_ID_O2_SDS1:
 414         case PCI_DEVICE_ID_O2_FUJIN2:
 415                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
 416                 if (reg & 0x1)
 417                         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 418
 419                 sdhci_pci_o2_enable_msi(chip, host);
 420
 421                 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
 422                         ret = pci_read_config_dword(chip->pdev,
 423                                                     O2_SD_MISC_SETTING, &reg);
 424                         if (ret)
 425                                 return -EIO;
 426                         if (reg & (1 << 4)) {
 427                                 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
 428                                         mmc_hostname(host->mmc));
 429                                 host->flags &= ~SDHCI_SIGNALING_330;
 430                                 host->flags |= SDHCI_SIGNALING_180;
 431                                 host->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
 432                                 host->mmc->caps2 |= MMC_CAP2_NO_SD;
 433                                 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 434                                 pci_write_config_dword(chip->pdev,
 435                                                        O2_SD_DETECT_SETTING, 3);
 436                         }
 437
 438                         slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
 439                 }
 440
 441                 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
 442
 443                 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
 444                         break;
 445                 /* set dll watch dog timer */
 446                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
 447                 reg |= (1 << 12);
 448                 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
 449
 450                 break;
 451         default:
 452                 break;
 453         }
 454
 455         return 0;
 456 }
 457
 458 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 459 {
 460         int ret;
 461         u8 scratch;
 462         u32 scratch_32;
 463
 464         switch (chip->pdev->device) {
 465         case PCI_DEVICE_ID_O2_8220:
 466         case PCI_DEVICE_ID_O2_8221:
 467         case PCI_DEVICE_ID_O2_8320:
 468         case PCI_DEVICE_ID_O2_8321:
 469                 /* This extra setup is required due to broken ADMA. */
 470                 ret = pci_read_config_byte(chip->pdev,
 471                                 O2_SD_LOCK_WP, &scratch);
 472                 if (ret)
 473                         return ret;
 474                 scratch &= 0x7f;
 475                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 476
 477                 /* Set Multi 3 to VCC3V# */
 478                 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
 479
 480                 /* Disable CLK_REQ# support after media DET */
 481                 ret = pci_read_config_byte(chip->pdev,
 482                                 O2_SD_CLKREQ, &scratch);
 483                 if (ret)
 484                         return ret;
 485                 scratch |= 0x20;
 486                 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
 487
 488                 /* Choose capabilities, enable SDMA.  We have to write 0x01
 489                  * to the capabilities register first to unlock it.
 490                  */
 491                 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
 492                 if (ret)
 493                         return ret;
 494                 scratch |= 0x01;
 495                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
 496                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
 497
 498                 /* Disable ADMA1/2 */
 499                 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
 500                 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
 501
 502                 /* Disable the infinite transfer mode */
 503                 ret = pci_read_config_byte(chip->pdev,
 504                                 O2_SD_INF_MOD, &scratch);
 505                 if (ret)
 506                         return ret;
 507                 scratch |= 0x08;
 508                 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
 509
 510                 /* Lock WP */
 511                 ret = pci_read_config_byte(chip->pdev,
 512                                 O2_SD_LOCK_WP, &scratch);
 513                 if (ret)
 514                         return ret;
 515                 scratch |= 0x80;
 516                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 517                 break;
 518         case PCI_DEVICE_ID_O2_SDS0:
 519         case PCI_DEVICE_ID_O2_SDS1:
 520         case PCI_DEVICE_ID_O2_FUJIN2:
 521                 /* UnLock WP */
 522                 ret = pci_read_config_byte(chip->pdev,
 523                                 O2_SD_LOCK_WP, &scratch);
 524                 if (ret)
 525                         return ret;
 526
 527                 scratch &= 0x7f;
 528                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 529
 530                 /* DevId=8520 subId= 0x11 or 0x12  Type Chip support */
 531                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
 532                         ret = pci_read_config_dword(chip->pdev,
 533                                                     O2_SD_FUNC_REG0,
 534                                                     &scratch_32);
 535                         scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
 536
 537                         /* Check Whether subId is 0x11 or 0x12 */
 538                         if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
 539                                 scratch_32 = 0x25100000;
 540
 541                                 o2_pci_set_baseclk(chip, scratch_32);
 542                                 ret = pci_read_config_dword(chip->pdev,
 543                                                             O2_SD_FUNC_REG4,
 544                                                             &scratch_32);
 545
 546                                 /* Enable Base Clk setting change */
 547                                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
 548                                 pci_write_config_dword(chip->pdev,
 549                                                        O2_SD_FUNC_REG4,
 550                                                        scratch_32);
 551
 552                                 /* Set Tuning Window to 4 */
 553                                 pci_write_config_byte(chip->pdev,
 554                                                       O2_SD_TUNING_CTRL, 0x44);
 555
 556                                 break;
 557                         }
 558                 }
 559
 560                 /* Enable 8520 led function */
 561                 o2_pci_led_enable(chip);
 562
 563                 /* Set timeout CLK */
 564                 ret = pci_read_config_dword(chip->pdev,
 565                                             O2_SD_CLK_SETTING, &scratch_32);
 566                 if (ret)
 567                         return ret;
 568
 569                 scratch_32 &= ~(0xFF00);
 570                 scratch_32 |= 0x07E0C800;
 571                 pci_write_config_dword(chip->pdev,
 572                                        O2_SD_CLK_SETTING, scratch_32);
 573
 574                 ret = pci_read_config_dword(chip->pdev,
 575                                             O2_SD_CLKREQ, &scratch_32);
 576                 if (ret)
 577                         return ret;
 578                 scratch_32 |= 0x3;
 579                 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
 580
 581                 ret = pci_read_config_dword(chip->pdev,
 582                                             O2_SD_PLL_SETTING, &scratch_32);
 583                 if (ret)
 584                         return ret;
 585
 586                 scratch_32 &= ~(0x1F3F070E);
 587                 scratch_32 |= 0x18270106;
 588                 pci_write_config_dword(chip->pdev,
 589                                        O2_SD_PLL_SETTING, scratch_32);
 590
 591                 /* Disable UHS1 funciton */
 592                 ret = pci_read_config_dword(chip->pdev,
 593                                             O2_SD_CAP_REG2, &scratch_32);
 594                 if (ret)
 595                         return ret;
 596                 scratch_32 &= ~(0xE0);
 597                 pci_write_config_dword(chip->pdev,
 598                                        O2_SD_CAP_REG2, scratch_32);
 599
 600                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
 601                         sdhci_pci_o2_fujin2_pci_init(chip);
 602
 603                 /* Lock WP */
 604                 ret = pci_read_config_byte(chip->pdev,
 605                                            O2_SD_LOCK_WP, &scratch);
 606                 if (ret)
 607                         return ret;
 608                 scratch |= 0x80;
 609                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 610                 break;
 611         case PCI_DEVICE_ID_O2_SEABIRD0:
 612         case PCI_DEVICE_ID_O2_SEABIRD1:
 613                 /* UnLock WP */
 614                 ret = pci_read_config_byte(chip->pdev,
 615                                 O2_SD_LOCK_WP, &scratch);
 616                 if (ret)
 617                         return ret;
 618
 619                 scratch &= 0x7f;
 620                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 621
 622                 ret = pci_read_config_dword(chip->pdev,
 623                                             O2_SD_PLL_SETTING, &scratch_32);
 624
 625                 if ((scratch_32 & 0xff000000) == 0x01000000) {
 626                         scratch_32 &= 0x0000FFFF;
 627                         scratch_32 |= 0x1F340000;
 628
 629                         pci_write_config_dword(chip->pdev,
 630                                                O2_SD_PLL_SETTING, scratch_32);
 631                 } else {
 632                         scratch_32 &= 0x0000FFFF;
 633                         scratch_32 |= 0x25100000;
 634
 635                         pci_write_config_dword(chip->pdev,
 636                                                O2_SD_PLL_SETTING, scratch_32);
 637
 638                         ret = pci_read_config_dword(chip->pdev,
 639                                                     O2_SD_FUNC_REG4,
 640                                                     &scratch_32);
 641                         scratch_32 |= (1 << 22);
 642                         pci_write_config_dword(chip->pdev,
 643                                                O2_SD_FUNC_REG4, scratch_32);
 644                 }
 645
 646                 /* Set Tuning Windows to 5 */
 647                 pci_write_config_byte(chip->pdev,
 648                                 O2_SD_TUNING_CTRL, 0x55);
 649                 /* Lock WP */
 650                 ret = pci_read_config_byte(chip->pdev,
 651                                            O2_SD_LOCK_WP, &scratch);
 652                 if (ret)
 653                         return ret;
 654                 scratch |= 0x80;
 655                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 656                 break;
 657         }
 658
 659         return 0;
 660 }
 661
 662 #ifdef CONFIG_PM_SLEEP
 663 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
 664 {
 665         sdhci_pci_o2_probe(chip);
 666         return sdhci_pci_resume_host(chip);
 667 }
 668 #endif
 669
 670 static const struct sdhci_ops sdhci_pci_o2_ops = {
 671         .set_clock = sdhci_pci_o2_set_clock,
 672         .enable_dma = sdhci_pci_enable_dma,
 673         .set_bus_width = sdhci_set_bus_width,
 674         .reset = sdhci_reset,
 675         .set_uhs_signaling = sdhci_set_uhs_signaling,
 676 };
 677
 678 const struct sdhci_pci_fixes sdhci_o2 = {
 679         .probe = sdhci_pci_o2_probe,
 680         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 681         .probe_slot = sdhci_pci_o2_probe_slot,
 682 #ifdef CONFIG_PM_SLEEP
 683         .resume = sdhci_pci_o2_resume,
 684 #endif
 685         .ops = &sdhci_pci_o2_ops,
 686 };