drivers/mmc/host/sdhci-pci-gli.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 Genesys Logic, Inc.
   4  *
   5  * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
   6  *
   7  * Version: v0.9.0 (2019-08-08)
   8  */
   9
  10 #include <linux/bitfield.h>
  11 #include <linux/bits.h>
  12 #include <linux/pci.h>
  13 #include <linux/mmc/mmc.h>
  14 #include <linux/delay.h>
  15 #include "sdhci.h"
  16 #include "sdhci-pci.h"
  17 #include "cqhci.h"
  18
  19 /*  Genesys Logic extra registers */
  20 #define SDHCI_GLI_9750_WT         0x800
  21 #define   SDHCI_GLI_9750_WT_EN      BIT(0)
  22 #define   GLI_9750_WT_EN_ON         0x1
  23 #define   GLI_9750_WT_EN_OFF        0x0
  24
  25 #define SDHCI_GLI_9750_DRIVING      0x860
  26 #define   SDHCI_GLI_9750_DRIVING_1    GENMASK(11, 0)
  27 #define   SDHCI_GLI_9750_DRIVING_2    GENMASK(27, 26)
  28 #define   GLI_9750_DRIVING_1_VALUE    0xFFF
  29 #define   GLI_9750_DRIVING_2_VALUE    0x3
  30 #define   SDHCI_GLI_9750_SEL_1        BIT(29)
  31 #define   SDHCI_GLI_9750_SEL_2        BIT(31)
  32 #define   SDHCI_GLI_9750_ALL_RST      (BIT(24)|BIT(25)|BIT(28)|BIT(30))
  33
  34 #define SDHCI_GLI_9750_PLL            0x864
  35 #define   SDHCI_GLI_9750_PLL_LDIV       GENMASK(9, 0)
  36 #define   SDHCI_GLI_9750_PLL_PDIV       GENMASK(14, 12)
  37 #define   SDHCI_GLI_9750_PLL_DIR        BIT(15)
  38 #define   SDHCI_GLI_9750_PLL_TX2_INV    BIT(23)
  39 #define   SDHCI_GLI_9750_PLL_TX2_DLY    GENMASK(22, 20)
  40 #define   GLI_9750_PLL_TX2_INV_VALUE    0x1
  41 #define   GLI_9750_PLL_TX2_DLY_VALUE    0x0
  42 #define   SDHCI_GLI_9750_PLLSSC_STEP    GENMASK(28, 24)
  43 #define   SDHCI_GLI_9750_PLLSSC_EN      BIT(31)
  44
  45 #define SDHCI_GLI_9750_PLLSSC        0x86C
  46 #define   SDHCI_GLI_9750_PLLSSC_PPM    GENMASK(31, 16)
  47
  48 #define SDHCI_GLI_9750_SW_CTRL      0x874
  49 #define   SDHCI_GLI_9750_SW_CTRL_4    GENMASK(7, 6)
  50 #define   GLI_9750_SW_CTRL_4_VALUE    0x3
  51
  52 #define SDHCI_GLI_9750_MISC            0x878
  53 #define   SDHCI_GLI_9750_MISC_TX1_INV    BIT(2)
  54 #define   SDHCI_GLI_9750_MISC_RX_INV     BIT(3)
  55 #define   SDHCI_GLI_9750_MISC_TX1_DLY    GENMASK(6, 4)
  56 #define   GLI_9750_MISC_TX1_INV_VALUE    0x0
  57 #define   GLI_9750_MISC_RX_INV_ON        0x1
  58 #define   GLI_9750_MISC_RX_INV_OFF       0x0
  59 #define   GLI_9750_MISC_RX_INV_VALUE     GLI_9750_MISC_RX_INV_OFF
  60 #define   GLI_9750_MISC_TX1_DLY_VALUE    0x5
  61
  62 #define SDHCI_GLI_9750_TUNING_CONTROL             0x540
  63 #define   SDHCI_GLI_9750_TUNING_CONTROL_EN          BIT(4)
  64 #define   GLI_9750_TUNING_CONTROL_EN_ON             0x1
  65 #define   GLI_9750_TUNING_CONTROL_EN_OFF            0x0
  66 #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1    BIT(16)
  67 #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2    GENMASK(20, 19)
  68 #define   GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE    0x1
  69 #define   GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE    0x2
  70
  71 #define SDHCI_GLI_9750_TUNING_PARAMETERS           0x544
  72 #define   SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY    GENMASK(2, 0)
  73 #define   GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE    0x1
  74
  75 #define SDHCI_GLI_9763E_CTRL_HS400  0x7
  76
  77 #define SDHCI_GLI_9763E_HS400_ES_REG      0x52C
  78 #define   SDHCI_GLI_9763E_HS400_ES_BIT      BIT(8)
  79
  80 #define PCIE_GLI_9763E_VHS       0x884
  81 #define   GLI_9763E_VHS_REV        GENMASK(19, 16)
  82 #define   GLI_9763E_VHS_REV_R      0x0
  83 #define   GLI_9763E_VHS_REV_M      0x1
  84 #define   GLI_9763E_VHS_REV_W      0x2
  85 #define PCIE_GLI_9763E_MB        0x888
  86 #define   GLI_9763E_MB_CMDQ_OFF    BIT(19)
  87 #define   GLI_9763E_MB_ERP_ON      BIT(7)
  88 #define PCIE_GLI_9763E_SCR       0x8E0
  89 #define   GLI_9763E_SCR_AXI_REQ    BIT(9)
  90
  91 #define PCIE_GLI_9763E_CFG2      0x8A4
  92 #define   GLI_9763E_CFG2_L1DLY     GENMASK(28, 19)
  93 #define   GLI_9763E_CFG2_L1DLY_MAX 0x3FF
  94
  95 #define PCIE_GLI_9763E_MMC_CTRL  0x960
  96 #define   GLI_9763E_HS400_SLOW     BIT(3)
  97
  98 #define PCIE_GLI_9763E_CLKRXDLY  0x934
  99 #define   GLI_9763E_HS400_RXDLY    GENMASK(31, 28)
 100 #define   GLI_9763E_HS400_RXDLY_5  0x5
 101
 102 #define SDHCI_GLI_9763E_CQE_BASE_ADDR    0x200
 103 #define GLI_9763E_CQE_TRNS_MODE    (SDHCI_TRNS_MULTI | \
 104                                     SDHCI_TRNS_BLK_CNT_EN | \
 105                                     SDHCI_TRNS_DMA)
 106
 107 #define PCI_GLI_9755_WT       0x800
 108 #define   PCI_GLI_9755_WT_EN    BIT(0)
 109 #define   GLI_9755_WT_EN_ON     0x1
 110 #define   GLI_9755_WT_EN_OFF    0x0
 111
 112 #define PCI_GLI_9755_PECONF   0x44
 113 #define   PCI_GLI_9755_LFCLK    GENMASK(14, 12)
 114 #define   PCI_GLI_9755_DMACLK   BIT(29)
 115
 116 #define PCI_GLI_9755_PLL            0x64
 117 #define   PCI_GLI_9755_PLL_LDIV       GENMASK(9, 0)
 118 #define   PCI_GLI_9755_PLL_PDIV       GENMASK(14, 12)
 119 #define   PCI_GLI_9755_PLL_DIR        BIT(15)
 120 #define   PCI_GLI_9755_PLLSSC_STEP    GENMASK(28, 24)
 121 #define   PCI_GLI_9755_PLLSSC_EN      BIT(31)
 122
 123 #define PCI_GLI_9755_PLLSSC        0x68
 124 #define   PCI_GLI_9755_PLLSSC_PPM    GENMASK(15, 0)
 125
 126 #define GLI_MAX_TUNING_LOOP 40
 127
 128 /* Genesys Logic chipset */
 129 static inline void gl9750_wt_on(struct sdhci_host *host)
 130 {
 131         u32 wt_value;
 132         u32 wt_enable;
 133
 134         wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
 135         wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
 136
 137         if (wt_enable == GLI_9750_WT_EN_ON)
 138                 return;
 139
 140         wt_value &= ~SDHCI_GLI_9750_WT_EN;
 141         wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
 142
 143         sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
 144 }
 145
 146 static inline void gl9750_wt_off(struct sdhci_host *host)
 147 {
 148         u32 wt_value;
 149         u32 wt_enable;
 150
 151         wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
 152         wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
 153
 154         if (wt_enable == GLI_9750_WT_EN_OFF)
 155                 return;
 156
 157         wt_value &= ~SDHCI_GLI_9750_WT_EN;
 158         wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
 159
 160         sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
 161 }
 162
 163 static void gli_set_9750(struct sdhci_host *host)
 164 {
 165         u32 driving_value;
 166         u32 pll_value;
 167         u32 sw_ctrl_value;
 168         u32 misc_value;
 169         u32 parameter_value;
 170         u32 control_value;
 171         u16 ctrl2;
 172
 173         gl9750_wt_on(host);
 174
 175         driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
 176         pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 177         sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
 178         misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
 179         parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
 180         control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
 181
 182         driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
 183         driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
 184         driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
 185                                     GLI_9750_DRIVING_1_VALUE);
 186         driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
 187                                     GLI_9750_DRIVING_2_VALUE);
 188         driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
 189         driving_value |= SDHCI_GLI_9750_SEL_2;
 190         sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
 191
 192         sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
 193         sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
 194                                     GLI_9750_SW_CTRL_4_VALUE);
 195         sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
 196
 197         /* reset the tuning flow after reinit and before starting tuning */
 198         pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
 199         pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
 200         pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
 201                                 GLI_9750_PLL_TX2_INV_VALUE);
 202         pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
 203                                 GLI_9750_PLL_TX2_DLY_VALUE);
 204
 205         misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
 206         misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
 207         misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
 208         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
 209                                  GLI_9750_MISC_TX1_INV_VALUE);
 210         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
 211                                  GLI_9750_MISC_RX_INV_VALUE);
 212         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
 213                                  GLI_9750_MISC_TX1_DLY_VALUE);
 214
 215         parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
 216         parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
 217                                       GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
 218
 219         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
 220         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
 221         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
 222                                     GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
 223         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
 224                                     GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
 225
 226         sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
 227         sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
 228
 229         /* disable tuned clk */
 230         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 231         ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
 232         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 233
 234         /* enable tuning parameters control */
 235         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
 236         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
 237                                     GLI_9750_TUNING_CONTROL_EN_ON);
 238         sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
 239
 240         /* write tuning parameters */
 241         sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
 242
 243         /* disable tuning parameters control */
 244         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
 245         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
 246                                     GLI_9750_TUNING_CONTROL_EN_OFF);
 247         sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
 248
 249         /* clear tuned clk */
 250         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 251         ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
 252         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 253
 254         gl9750_wt_off(host);
 255 }
 256
 257 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
 258 {
 259         u32 misc_value;
 260
 261         gl9750_wt_on(host);
 262
 263         misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
 264         misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
 265         if (b) {
 266                 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
 267                                          GLI_9750_MISC_RX_INV_ON);
 268         } else {
 269                 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
 270                                          GLI_9750_MISC_RX_INV_OFF);
 271         }
 272         sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
 273
 274         gl9750_wt_off(host);
 275 }
 276
 277 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
 278 {
 279         int i;
 280         int rx_inv;
 281
 282         for (rx_inv = 0; rx_inv < 2; rx_inv++) {
 283                 gli_set_9750_rx_inv(host, !!rx_inv);
 284                 sdhci_start_tuning(host);
 285
 286                 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
 287                         u16 ctrl;
 288
 289                         sdhci_send_tuning(host, opcode);
 290
 291                         if (!host->tuning_done) {
 292                                 sdhci_abort_tuning(host, opcode);
 293                                 break;
 294                         }
 295
 296                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 297                         if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
 298                                 if (ctrl & SDHCI_CTRL_TUNED_CLK)
 299                                         return 0; /* Success! */
 300                                 break;
 301                         }
 302                 }
 303         }
 304         if (!host->tuning_done) {
 305                 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
 306                         mmc_hostname(host->mmc));
 307                 return -ETIMEDOUT;
 308         }
 309
 310         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
 311                 mmc_hostname(host->mmc));
 312         sdhci_reset_tuning(host);
 313
 314         return -EAGAIN;
 315 }
 316
 317 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
 318 {
 319         host->mmc->retune_period = 0;
 320         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
 321                 host->mmc->retune_period = host->tuning_count;
 322
 323         gli_set_9750(host);
 324         host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
 325         sdhci_end_tuning(host);
 326
 327         return 0;
 328 }
 329
 330 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
 331 {
 332         u32 pll;
 333
 334         gl9750_wt_on(host);
 335         pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 336         pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
 337         sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
 338         gl9750_wt_off(host);
 339 }
 340
 341 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
 342 {
 343         u32 pll;
 344
 345         gl9750_wt_on(host);
 346         pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 347         pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
 348                  SDHCI_GLI_9750_PLL_PDIV |
 349                  SDHCI_GLI_9750_PLL_DIR);
 350         pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
 351                FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
 352                FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
 353         sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
 354         gl9750_wt_off(host);
 355
 356         /* wait for pll stable */
 357         mdelay(1);
 358 }
 359
 360 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
 361 {
 362         u32 pll;
 363         u32 ssc;
 364
 365         gl9750_wt_on(host);
 366         pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 367         ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
 368         pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
 369                  SDHCI_GLI_9750_PLLSSC_EN);
 370         ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
 371         pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
 372                FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
 373         ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
 374         sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
 375         sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
 376         gl9750_wt_off(host);
 377 }
 378
 379 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
 380 {
 381         /* set pll to 205MHz and enable ssc */
 382         gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7);
 383         gl9750_set_pll(host, 0x1, 0x246, 0x0);
 384 }
 385
 386 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
 387 {
 388         struct mmc_ios *ios = &host->mmc->ios;
 389         u16 clk;
 390
 391         host->mmc->actual_clock = 0;
 392
 393         gl9750_disable_ssc_pll(host);
 394         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 395
 396         if (clock == 0)
 397                 return;
 398
 399         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
 400         if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
 401                 host->mmc->actual_clock = 205000000;
 402                 gl9750_set_ssc_pll_205mhz(host);
 403         }
 404
 405         sdhci_enable_clk(host, clk);
 406 }
 407
 408 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
 409 {
 410         int ret;
 411
 412         ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
 413                                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
 414         if (ret < 0) {
 415                 pr_warn("%s: enable PCI MSI failed, error=%d\n",
 416                        mmc_hostname(slot->host->mmc), ret);
 417                 return;
 418         }
 419
 420         slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
 421 }
 422
 423 static inline void gl9755_wt_on(struct pci_dev *pdev)
 424 {
 425         u32 wt_value;
 426         u32 wt_enable;
 427
 428         pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
 429         wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
 430
 431         if (wt_enable == GLI_9755_WT_EN_ON)
 432                 return;
 433
 434         wt_value &= ~PCI_GLI_9755_WT_EN;
 435         wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
 436
 437         pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
 438 }
 439
 440 static inline void gl9755_wt_off(struct pci_dev *pdev)
 441 {
 442         u32 wt_value;
 443         u32 wt_enable;
 444
 445         pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
 446         wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
 447
 448         if (wt_enable == GLI_9755_WT_EN_OFF)
 449                 return;
 450
 451         wt_value &= ~PCI_GLI_9755_WT_EN;
 452         wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
 453
 454         pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
 455 }
 456
 457 static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
 458 {
 459         u32 pll;
 460
 461         gl9755_wt_on(pdev);
 462         pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
 463         pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
 464         pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
 465         gl9755_wt_off(pdev);
 466 }
 467
 468 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
 469 {
 470         u32 pll;
 471
 472         gl9755_wt_on(pdev);
 473         pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
 474         pll &= ~(PCI_GLI_9755_PLL_LDIV |
 475                  PCI_GLI_9755_PLL_PDIV |
 476                  PCI_GLI_9755_PLL_DIR);
 477         pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
 478                FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
 479                FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
 480         pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
 481         gl9755_wt_off(pdev);
 482
 483         /* wait for pll stable */
 484         mdelay(1);
 485 }
 486
 487 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
 488 {
 489         u32 pll;
 490         u32 ssc;
 491
 492         gl9755_wt_on(pdev);
 493         pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
 494         pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
 495         pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
 496                  PCI_GLI_9755_PLLSSC_EN);
 497         ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
 498         pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
 499                FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
 500         ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
 501         pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
 502         pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
 503         gl9755_wt_off(pdev);
 504 }
 505
 506 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
 507 {
 508         /* set pll to 205MHz and enable ssc */
 509         gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7);
 510         gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
 511 }
 512
 513 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
 514 {
 515         struct sdhci_pci_slot *slot = sdhci_priv(host);
 516         struct mmc_ios *ios = &host->mmc->ios;
 517         struct pci_dev *pdev;
 518         u16 clk;
 519
 520         pdev = slot->chip->pdev;
 521         host->mmc->actual_clock = 0;
 522
 523         gl9755_disable_ssc_pll(pdev);
 524         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 525
 526         if (clock == 0)
 527                 return;
 528
 529         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
 530         if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
 531                 host->mmc->actual_clock = 205000000;
 532                 gl9755_set_ssc_pll_205mhz(pdev);
 533         }
 534
 535         sdhci_enable_clk(host, clk);
 536 }
 537
 538 static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
 539 {
 540         struct pci_dev *pdev = slot->chip->pdev;
 541         u32 value;
 542
 543         gl9755_wt_on(pdev);
 544
 545         pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
 546         value &= ~PCI_GLI_9755_LFCLK;
 547         value &= ~PCI_GLI_9755_DMACLK;
 548         pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
 549
 550         gl9755_wt_off(pdev);
 551 }
 552
 553 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
 554 {
 555         struct sdhci_host *host = slot->host;
 556
 557         gli_pcie_enable_msi(slot);
 558         slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 559         sdhci_enable_v4_mode(host);
 560
 561         return 0;
 562 }
 563
 564 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
 565 {
 566         struct sdhci_host *host = slot->host;
 567
 568         gl9755_hw_setting(slot);
 569         gli_pcie_enable_msi(slot);
 570         slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 571         sdhci_enable_v4_mode(host);
 572
 573         return 0;
 574 }
 575
 576 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
 577 {
 578         /*
 579          * According to Section 3.6.1 signal voltage switch procedure in
 580          * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
 581          * follows:
 582          * (6) Set 1.8V Signal Enable in the Host Control 2 register.
 583          * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
 584          *     period.
 585          * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
 586          *     step (12).
 587          *
 588          * Wait 5ms after set 1.8V signal enable in Host Control 2 register
 589          * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
 590          */
 591         usleep_range(5000, 5500);
 592 }
 593
 594 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
 595 {
 596         sdhci_reset(host, mask);
 597         gli_set_9750(host);
 598 }
 599
 600 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
 601 {
 602         u32 value;
 603
 604         value = readl(host->ioaddr + reg);
 605         if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
 606                 value |= 0xc8;
 607
 608         return value;
 609 }
 610
 611 #ifdef CONFIG_PM_SLEEP
 612 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
 613 {
 614         struct sdhci_pci_slot *slot = chip->slots[0];
 615
 616         pci_free_irq_vectors(slot->chip->pdev);
 617         gli_pcie_enable_msi(slot);
 618
 619         return sdhci_pci_resume_host(chip);
 620 }
 621
 622 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip)
 623 {
 624         struct sdhci_pci_slot *slot = chip->slots[0];
 625         int ret;
 626
 627         ret = sdhci_pci_gli_resume(chip);
 628         if (ret)
 629                 return ret;
 630
 631         return cqhci_resume(slot->host->mmc);
 632 }
 633
 634 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip)
 635 {
 636         struct sdhci_pci_slot *slot = chip->slots[0];
 637         int ret;
 638
 639         ret = cqhci_suspend(slot->host->mmc);
 640         if (ret)
 641                 return ret;
 642
 643         return sdhci_suspend_host(slot->host);
 644 }
 645 #endif
 646
 647 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
 648                                           struct mmc_ios *ios)
 649 {
 650         struct sdhci_host *host = mmc_priv(mmc);
 651         u32 val;
 652
 653         val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
 654         if (ios->enhanced_strobe)
 655                 val |= SDHCI_GLI_9763E_HS400_ES_BIT;
 656         else
 657                 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
 658
 659         sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
 660 }
 661
 662 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
 663                                         unsigned int timing)
 664 {
 665         u16 ctrl_2;
 666
 667         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 668         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 669         if (timing == MMC_TIMING_MMC_HS200)
 670                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 671         else if (timing == MMC_TIMING_MMC_HS)
 672                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 673         else if (timing == MMC_TIMING_MMC_DDR52)
 674                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 675         else if (timing == MMC_TIMING_MMC_HS400)
 676                 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
 677
 678         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 679 }
 680
 681 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
 682 {
 683         sdhci_dumpregs(mmc_priv(mmc));
 684 }
 685
 686 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
 687 {
 688         struct cqhci_host *cq_host = mmc->cqe_private;
 689         u32 value;
 690
 691         value = cqhci_readl(cq_host, CQHCI_CFG);
 692         value |= CQHCI_ENABLE;
 693         cqhci_writel(cq_host, value, CQHCI_CFG);
 694 }
 695
 696 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
 697 {
 698         struct sdhci_host *host = mmc_priv(mmc);
 699
 700         sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
 701         sdhci_cqe_enable(mmc);
 702 }
 703
 704 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
 705 {
 706         int cmd_error = 0;
 707         int data_error = 0;
 708
 709         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
 710                 return intmask;
 711
 712         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
 713
 714         return 0;
 715 }
 716
 717 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
 718 {
 719         struct sdhci_host *host = mmc_priv(mmc);
 720         struct cqhci_host *cq_host = mmc->cqe_private;
 721         u32 value;
 722
 723         value = cqhci_readl(cq_host, CQHCI_CFG);
 724         value &= ~CQHCI_ENABLE;
 725         cqhci_writel(cq_host, value, CQHCI_CFG);
 726         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 727 }
 728
 729 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
 730         .enable         = sdhci_gl9763e_cqe_enable,
 731         .disable        = sdhci_cqe_disable,
 732         .dumpregs       = sdhci_gl9763e_dumpregs,
 733         .pre_enable     = sdhci_gl9763e_cqe_pre_enable,
 734         .post_disable   = sdhci_gl9763e_cqe_post_disable,
 735 };
 736
 737 static int gl9763e_add_host(struct sdhci_pci_slot *slot)
 738 {
 739         struct device *dev = &slot->chip->pdev->dev;
 740         struct sdhci_host *host = slot->host;
 741         struct cqhci_host *cq_host;
 742         bool dma64;
 743         int ret;
 744
 745         ret = sdhci_setup_host(host);
 746         if (ret)
 747                 return ret;
 748
 749         cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
 750         if (!cq_host) {
 751                 ret = -ENOMEM;
 752                 goto cleanup;
 753         }
 754
 755         cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
 756         cq_host->ops = &sdhci_gl9763e_cqhci_ops;
 757
 758         dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
 759         if (dma64)
 760                 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
 761
 762         ret = cqhci_init(cq_host, host->mmc, dma64);
 763         if (ret)
 764                 goto cleanup;
 765
 766         ret = __sdhci_add_host(host);
 767         if (ret)
 768                 goto cleanup;
 769
 770         return 0;
 771
 772 cleanup:
 773         sdhci_cleanup_host(host);
 774         return ret;
 775 }
 776
 777 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask)
 778 {
 779         if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
 780             host->mmc->cqe_private)
 781                 cqhci_deactivate(host->mmc);
 782         sdhci_reset(host, mask);
 783 }
 784
 785 static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
 786 {
 787         struct pci_dev *pdev = slot->chip->pdev;
 788         u32 value;
 789
 790         pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
 791         value &= ~GLI_9763E_VHS_REV;
 792         value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
 793         pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
 794
 795         pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
 796         value |= GLI_9763E_SCR_AXI_REQ;
 797         pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
 798
 799         pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
 800         value &= ~GLI_9763E_HS400_SLOW;
 801         pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
 802
 803         pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
 804         value &= ~GLI_9763E_CFG2_L1DLY;
 805         /* set ASPM L1 entry delay to 260us */
 806         value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MAX);
 807         pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
 808
 809         pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
 810         value &= ~GLI_9763E_HS400_RXDLY;
 811         value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
 812         pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
 813
 814         pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
 815         value &= ~GLI_9763E_VHS_REV;
 816         value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
 817         pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
 818 }
 819
 820 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
 821 {
 822         struct pci_dev *pdev = slot->chip->pdev;
 823         struct sdhci_host *host = slot->host;
 824         u32 value;
 825
 826         host->mmc->caps |= MMC_CAP_8_BIT_DATA |
 827                            MMC_CAP_1_8V_DDR |
 828                            MMC_CAP_NONREMOVABLE;
 829         host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
 830                             MMC_CAP2_HS400_1_8V |
 831                             MMC_CAP2_HS400_ES |
 832                             MMC_CAP2_NO_SDIO |
 833                             MMC_CAP2_NO_SD;
 834
 835         pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
 836         if (!(value & GLI_9763E_MB_CMDQ_OFF))
 837                 if (value & GLI_9763E_MB_ERP_ON)
 838                         host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
 839
 840         gli_pcie_enable_msi(slot);
 841         host->mmc_host_ops.hs400_enhanced_strobe =
 842                                         gl9763e_hs400_enhanced_strobe;
 843         gli_set_gl9763e(slot);
 844         sdhci_enable_v4_mode(host);
 845
 846         return 0;
 847 }
 848
 849 static const struct sdhci_ops sdhci_gl9755_ops = {
 850         .set_clock              = sdhci_gl9755_set_clock,
 851         .enable_dma             = sdhci_pci_enable_dma,
 852         .set_bus_width          = sdhci_set_bus_width,
 853         .reset                  = sdhci_reset,
 854         .set_uhs_signaling      = sdhci_set_uhs_signaling,
 855         .voltage_switch         = sdhci_gli_voltage_switch,
 856 };
 857
 858 const struct sdhci_pci_fixes sdhci_gl9755 = {
 859         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 860         .quirks2        = SDHCI_QUIRK2_BROKEN_DDR50,
 861         .probe_slot     = gli_probe_slot_gl9755,
 862         .ops            = &sdhci_gl9755_ops,
 863 #ifdef CONFIG_PM_SLEEP
 864         .resume         = sdhci_pci_gli_resume,
 865 #endif
 866 };
 867
 868 static const struct sdhci_ops sdhci_gl9750_ops = {
 869         .read_l                 = sdhci_gl9750_readl,
 870         .set_clock              = sdhci_gl9750_set_clock,
 871         .enable_dma             = sdhci_pci_enable_dma,
 872         .set_bus_width          = sdhci_set_bus_width,
 873         .reset                  = sdhci_gl9750_reset,
 874         .set_uhs_signaling      = sdhci_set_uhs_signaling,
 875         .voltage_switch         = sdhci_gli_voltage_switch,
 876         .platform_execute_tuning = gl9750_execute_tuning,
 877 };
 878
 879 const struct sdhci_pci_fixes sdhci_gl9750 = {
 880         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 881         .quirks2        = SDHCI_QUIRK2_BROKEN_DDR50,
 882         .probe_slot     = gli_probe_slot_gl9750,
 883         .ops            = &sdhci_gl9750_ops,
 884 #ifdef CONFIG_PM_SLEEP
 885         .resume         = sdhci_pci_gli_resume,
 886 #endif
 887 };
 888
 889 static const struct sdhci_ops sdhci_gl9763e_ops = {
 890         .set_clock              = sdhci_set_clock,
 891         .enable_dma             = sdhci_pci_enable_dma,
 892         .set_bus_width          = sdhci_set_bus_width,
 893         .reset                  = sdhci_gl9763e_reset,
 894         .set_uhs_signaling      = sdhci_set_gl9763e_signaling,
 895         .voltage_switch         = sdhci_gli_voltage_switch,
 896         .irq                    = sdhci_gl9763e_cqhci_irq,
 897 };
 898
 899 const struct sdhci_pci_fixes sdhci_gl9763e = {
 900         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 901         .probe_slot     = gli_probe_slot_gl9763e,
 902         .ops            = &sdhci_gl9763e_ops,
 903 #ifdef CONFIG_PM_SLEEP
 904         .resume         = sdhci_cqhci_gli_resume,
 905         .suspend        = sdhci_cqhci_gli_suspend,
 906 #endif
 907         .add_host       = gl9763e_add_host,
 908 };