1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Genesys Logic, Inc.
5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
7 * Version: v0.9.0 (2019-08-08)
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/pci.h>
13 #include <linux/mmc/mmc.h>
14 #include <linux/delay.h>
16 #include "sdhci-pci.h"
19 /* Genesys Logic extra registers */
20 #define SDHCI_GLI_9750_WT 0x800
21 #define SDHCI_GLI_9750_WT_EN BIT(0)
22 #define GLI_9750_WT_EN_ON 0x1
23 #define GLI_9750_WT_EN_OFF 0x0
25 #define SDHCI_GLI_9750_CFG2 0x848
26 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24)
27 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F
29 #define SDHCI_GLI_9750_DRIVING 0x860
30 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)
31 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)
32 #define GLI_9750_DRIVING_1_VALUE 0xFFF
33 #define GLI_9750_DRIVING_2_VALUE 0x3
34 #define SDHCI_GLI_9750_SEL_1 BIT(29)
35 #define SDHCI_GLI_9750_SEL_2 BIT(31)
36 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
38 #define SDHCI_GLI_9750_PLL 0x864
39 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)
40 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)
41 #define SDHCI_GLI_9750_PLL_DIR BIT(15)
42 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
43 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
44 #define GLI_9750_PLL_TX2_INV_VALUE 0x1
45 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0
46 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)
47 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31)
49 #define SDHCI_GLI_9750_PLLSSC 0x86C
50 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)
52 #define SDHCI_GLI_9750_SW_CTRL 0x874
53 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
54 #define GLI_9750_SW_CTRL_4_VALUE 0x3
56 #define SDHCI_GLI_9750_MISC 0x878
57 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2)
58 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3)
59 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)
60 #define GLI_9750_MISC_TX1_INV_VALUE 0x0
61 #define GLI_9750_MISC_RX_INV_ON 0x1
62 #define GLI_9750_MISC_RX_INV_OFF 0x0
63 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
64 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5
66 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540
67 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
68 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1
69 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0
70 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16)
71 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)
72 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1
73 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2
75 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544
76 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)
77 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1
79 #define SDHCI_GLI_9763E_CTRL_HS400 0x7
81 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C
82 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8)
84 #define PCIE_GLI_9763E_VHS 0x884
85 #define GLI_9763E_VHS_REV GENMASK(19, 16)
86 #define GLI_9763E_VHS_REV_R 0x0
87 #define GLI_9763E_VHS_REV_M 0x1
88 #define GLI_9763E_VHS_REV_W 0x2
89 #define PCIE_GLI_9763E_MB 0x888
90 #define GLI_9763E_MB_CMDQ_OFF BIT(19)
91 #define GLI_9763E_MB_ERP_ON BIT(7)
92 #define PCIE_GLI_9763E_SCR 0x8E0
93 #define GLI_9763E_SCR_AXI_REQ BIT(9)
95 #define PCIE_GLI_9763E_CFG2 0x8A4
96 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19)
97 #define GLI_9763E_CFG2_L1DLY_MID 0x54
99 #define PCIE_GLI_9763E_MMC_CTRL 0x960
100 #define GLI_9763E_HS400_SLOW BIT(3)
102 #define PCIE_GLI_9763E_CLKRXDLY 0x934
103 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28)
104 #define GLI_9763E_HS400_RXDLY_5 0x5
106 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
107 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
108 SDHCI_TRNS_BLK_CNT_EN | \
111 #define PCI_GLI_9755_WT 0x800
112 #define PCI_GLI_9755_WT_EN BIT(0)
113 #define GLI_9755_WT_EN_ON 0x1
114 #define GLI_9755_WT_EN_OFF 0x0
116 #define PCI_GLI_9755_PECONF 0x44
117 #define PCI_GLI_9755_LFCLK GENMASK(14, 12)
118 #define PCI_GLI_9755_DMACLK BIT(29)
120 #define PCI_GLI_9755_CFG2 0x48
121 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24)
122 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F
124 #define PCI_GLI_9755_PLL 0x64
125 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)
126 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)
127 #define PCI_GLI_9755_PLL_DIR BIT(15)
128 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)
129 #define PCI_GLI_9755_PLLSSC_EN BIT(31)
131 #define PCI_GLI_9755_PLLSSC 0x68
132 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)
134 #define PCI_GLI_9755_SerDes 0x70
135 #define PCI_GLI_9755_SCP_DIS BIT(19)
137 #define GLI_MAX_TUNING_LOOP 40
139 /* Genesys Logic chipset */
140 static inline void gl9750_wt_on(struct sdhci_host *host)
145 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
146 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
148 if (wt_enable == GLI_9750_WT_EN_ON)
151 wt_value &= ~SDHCI_GLI_9750_WT_EN;
152 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
154 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
157 static inline void gl9750_wt_off(struct sdhci_host *host)
162 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
163 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
165 if (wt_enable == GLI_9750_WT_EN_OFF)
168 wt_value &= ~SDHCI_GLI_9750_WT_EN;
169 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
171 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
174 static void gli_set_9750(struct sdhci_host *host)
186 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
187 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
188 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
189 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
190 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
191 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
193 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
194 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
195 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
196 GLI_9750_DRIVING_1_VALUE);
197 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
198 GLI_9750_DRIVING_2_VALUE);
199 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
200 driving_value |= SDHCI_GLI_9750_SEL_2;
201 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
203 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
204 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
205 GLI_9750_SW_CTRL_4_VALUE);
206 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
208 /* reset the tuning flow after reinit and before starting tuning */
209 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
210 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
211 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
212 GLI_9750_PLL_TX2_INV_VALUE);
213 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
214 GLI_9750_PLL_TX2_DLY_VALUE);
216 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
217 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
218 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
219 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
220 GLI_9750_MISC_TX1_INV_VALUE);
221 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
222 GLI_9750_MISC_RX_INV_VALUE);
223 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
224 GLI_9750_MISC_TX1_DLY_VALUE);
226 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
227 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
228 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
230 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
231 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
232 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
233 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
234 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
235 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
237 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
238 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
240 /* disable tuned clk */
241 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
242 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
243 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
245 /* enable tuning parameters control */
246 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
247 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
248 GLI_9750_TUNING_CONTROL_EN_ON);
249 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
251 /* write tuning parameters */
252 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
254 /* disable tuning parameters control */
255 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
256 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
257 GLI_9750_TUNING_CONTROL_EN_OFF);
258 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
260 /* clear tuned clk */
261 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
262 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
263 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
268 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
274 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
275 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
277 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
278 GLI_9750_MISC_RX_INV_ON);
280 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
281 GLI_9750_MISC_RX_INV_OFF);
283 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
288 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
293 for (rx_inv = 0; rx_inv < 2; rx_inv++) {
294 gli_set_9750_rx_inv(host, !!rx_inv);
295 sdhci_start_tuning(host);
297 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
300 sdhci_send_tuning(host, opcode);
302 if (!host->tuning_done) {
303 sdhci_abort_tuning(host, opcode);
307 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
308 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
309 if (ctrl & SDHCI_CTRL_TUNED_CLK)
310 return 0; /* Success! */
315 if (!host->tuning_done) {
316 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
317 mmc_hostname(host->mmc));
321 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
322 mmc_hostname(host->mmc));
323 sdhci_reset_tuning(host);
328 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
330 host->mmc->retune_period = 0;
331 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
332 host->mmc->retune_period = host->tuning_count;
335 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
336 sdhci_end_tuning(host);
341 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
346 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
347 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
348 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
352 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
357 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
358 pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
359 SDHCI_GLI_9750_PLL_PDIV |
360 SDHCI_GLI_9750_PLL_DIR);
361 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
362 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
363 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
364 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
367 /* wait for pll stable */
371 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
377 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
378 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
379 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
380 SDHCI_GLI_9750_PLLSSC_EN);
381 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
382 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
383 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
384 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
385 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
386 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
390 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
392 /* set pll to 205MHz and enable ssc */
393 gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7);
394 gl9750_set_pll(host, 0x1, 0x246, 0x0);
397 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
399 struct mmc_ios *ios = &host->mmc->ios;
402 host->mmc->actual_clock = 0;
404 gl9750_disable_ssc_pll(host);
405 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
410 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
411 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
412 host->mmc->actual_clock = 205000000;
413 gl9750_set_ssc_pll_205mhz(host);
416 sdhci_enable_clk(host, clk);
419 static void gl9750_hw_setting(struct sdhci_host *host)
425 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
426 value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
427 /* set ASPM L1 entry delay to 7.9us */
428 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,
429 GLI_9750_CFG2_L1DLY_VALUE);
430 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);
435 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
439 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
440 PCI_IRQ_MSI | PCI_IRQ_MSIX);
442 pr_warn("%s: enable PCI MSI failed, error=%d\n",
443 mmc_hostname(slot->host->mmc), ret);
447 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
450 static inline void gl9755_wt_on(struct pci_dev *pdev)
455 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
456 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
458 if (wt_enable == GLI_9755_WT_EN_ON)
461 wt_value &= ~PCI_GLI_9755_WT_EN;
462 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
464 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
467 static inline void gl9755_wt_off(struct pci_dev *pdev)
472 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
473 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
475 if (wt_enable == GLI_9755_WT_EN_OFF)
478 wt_value &= ~PCI_GLI_9755_WT_EN;
479 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
481 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
484 static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
489 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
490 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
491 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
495 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
500 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
501 pll &= ~(PCI_GLI_9755_PLL_LDIV |
502 PCI_GLI_9755_PLL_PDIV |
503 PCI_GLI_9755_PLL_DIR);
504 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
505 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
506 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
507 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
510 /* wait for pll stable */
514 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
520 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
521 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
522 pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
523 PCI_GLI_9755_PLLSSC_EN);
524 ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
525 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
526 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
527 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
528 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
529 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
533 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
535 /* set pll to 205MHz and enable ssc */
536 gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7);
537 gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
540 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
542 struct sdhci_pci_slot *slot = sdhci_priv(host);
543 struct mmc_ios *ios = &host->mmc->ios;
544 struct pci_dev *pdev;
547 pdev = slot->chip->pdev;
548 host->mmc->actual_clock = 0;
550 gl9755_disable_ssc_pll(pdev);
551 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
556 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
557 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
558 host->mmc->actual_clock = 205000000;
559 gl9755_set_ssc_pll_205mhz(pdev);
562 sdhci_enable_clk(host, clk);
565 static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
567 struct pci_dev *pdev = slot->chip->pdev;
572 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
573 value &= ~PCI_GLI_9755_LFCLK;
574 value &= ~PCI_GLI_9755_DMACLK;
575 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
577 /* enable short circuit protection */
578 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value);
579 value &= ~PCI_GLI_9755_SCP_DIS;
580 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value);
582 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value);
583 value &= ~PCI_GLI_9755_CFG2_L1DLY;
584 /* set ASPM L1 entry delay to 7.9us */
585 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY,
586 GLI_9755_CFG2_L1DLY_VALUE);
587 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
592 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
594 struct sdhci_host *host = slot->host;
596 gl9750_hw_setting(host);
597 gli_pcie_enable_msi(slot);
598 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
599 sdhci_enable_v4_mode(host);
604 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
606 struct sdhci_host *host = slot->host;
608 gl9755_hw_setting(slot);
609 gli_pcie_enable_msi(slot);
610 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
611 sdhci_enable_v4_mode(host);
616 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
619 * According to Section 3.6.1 signal voltage switch procedure in
620 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
622 * (6) Set 1.8V Signal Enable in the Host Control 2 register.
623 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
625 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
628 * Wait 5ms after set 1.8V signal enable in Host Control 2 register
629 * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
631 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
632 * slightly longer than 5ms before the control register reports that
633 * 1.8V is ready, and far longer still before the card will actually
636 usleep_range(100000, 110000);
639 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
641 sdhci_reset(host, mask);
645 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
649 value = readl(host->ioaddr + reg);
650 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
656 #ifdef CONFIG_PM_SLEEP
657 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
659 struct sdhci_pci_slot *slot = chip->slots[0];
661 pci_free_irq_vectors(slot->chip->pdev);
662 gli_pcie_enable_msi(slot);
664 return sdhci_pci_resume_host(chip);
667 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip)
669 struct sdhci_pci_slot *slot = chip->slots[0];
672 ret = sdhci_pci_gli_resume(chip);
676 return cqhci_resume(slot->host->mmc);
679 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip)
681 struct sdhci_pci_slot *slot = chip->slots[0];
684 ret = cqhci_suspend(slot->host->mmc);
688 return sdhci_suspend_host(slot->host);
692 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
695 struct sdhci_host *host = mmc_priv(mmc);
698 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
699 if (ios->enhanced_strobe)
700 val |= SDHCI_GLI_9763E_HS400_ES_BIT;
702 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
704 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
707 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
712 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
713 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
714 if (timing == MMC_TIMING_MMC_HS200)
715 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
716 else if (timing == MMC_TIMING_MMC_HS)
717 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
718 else if (timing == MMC_TIMING_MMC_DDR52)
719 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
720 else if (timing == MMC_TIMING_MMC_HS400)
721 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
723 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
726 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
728 sdhci_dumpregs(mmc_priv(mmc));
731 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
733 struct cqhci_host *cq_host = mmc->cqe_private;
736 value = cqhci_readl(cq_host, CQHCI_CFG);
737 value |= CQHCI_ENABLE;
738 cqhci_writel(cq_host, value, CQHCI_CFG);
741 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
743 struct sdhci_host *host = mmc_priv(mmc);
745 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
746 sdhci_cqe_enable(mmc);
749 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
754 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
757 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
762 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
764 struct sdhci_host *host = mmc_priv(mmc);
765 struct cqhci_host *cq_host = mmc->cqe_private;
768 value = cqhci_readl(cq_host, CQHCI_CFG);
769 value &= ~CQHCI_ENABLE;
770 cqhci_writel(cq_host, value, CQHCI_CFG);
771 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
774 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
775 .enable = sdhci_gl9763e_cqe_enable,
776 .disable = sdhci_cqe_disable,
777 .dumpregs = sdhci_gl9763e_dumpregs,
778 .pre_enable = sdhci_gl9763e_cqe_pre_enable,
779 .post_disable = sdhci_gl9763e_cqe_post_disable,
782 static int gl9763e_add_host(struct sdhci_pci_slot *slot)
784 struct device *dev = &slot->chip->pdev->dev;
785 struct sdhci_host *host = slot->host;
786 struct cqhci_host *cq_host;
790 ret = sdhci_setup_host(host);
794 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
800 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
801 cq_host->ops = &sdhci_gl9763e_cqhci_ops;
803 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
805 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
807 ret = cqhci_init(cq_host, host->mmc, dma64);
811 ret = __sdhci_add_host(host);
818 sdhci_cleanup_host(host);
822 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask)
824 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
825 host->mmc->cqe_private)
826 cqhci_deactivate(host->mmc);
827 sdhci_reset(host, mask);
830 static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
832 struct pci_dev *pdev = slot->chip->pdev;
835 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
836 value &= ~GLI_9763E_VHS_REV;
837 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
838 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
840 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
841 value |= GLI_9763E_SCR_AXI_REQ;
842 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
844 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
845 value &= ~GLI_9763E_HS400_SLOW;
846 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
848 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
849 value &= ~GLI_9763E_CFG2_L1DLY;
850 /* set ASPM L1 entry delay to 21us */
851 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
852 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
854 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
855 value &= ~GLI_9763E_HS400_RXDLY;
856 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
857 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
859 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
860 value &= ~GLI_9763E_VHS_REV;
861 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
862 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
865 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
867 struct pci_dev *pdev = slot->chip->pdev;
868 struct sdhci_host *host = slot->host;
871 host->mmc->caps |= MMC_CAP_8_BIT_DATA |
873 MMC_CAP_NONREMOVABLE;
874 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
875 MMC_CAP2_HS400_1_8V |
880 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
881 if (!(value & GLI_9763E_MB_CMDQ_OFF))
882 if (value & GLI_9763E_MB_ERP_ON)
883 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
885 gli_pcie_enable_msi(slot);
886 host->mmc_host_ops.hs400_enhanced_strobe =
887 gl9763e_hs400_enhanced_strobe;
888 gli_set_gl9763e(slot);
889 sdhci_enable_v4_mode(host);
894 static const struct sdhci_ops sdhci_gl9755_ops = {
895 .set_clock = sdhci_gl9755_set_clock,
896 .enable_dma = sdhci_pci_enable_dma,
897 .set_bus_width = sdhci_set_bus_width,
898 .reset = sdhci_reset,
899 .set_uhs_signaling = sdhci_set_uhs_signaling,
900 .voltage_switch = sdhci_gli_voltage_switch,
903 const struct sdhci_pci_fixes sdhci_gl9755 = {
904 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
905 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
906 .probe_slot = gli_probe_slot_gl9755,
907 .ops = &sdhci_gl9755_ops,
908 #ifdef CONFIG_PM_SLEEP
909 .resume = sdhci_pci_gli_resume,
913 static const struct sdhci_ops sdhci_gl9750_ops = {
914 .read_l = sdhci_gl9750_readl,
915 .set_clock = sdhci_gl9750_set_clock,
916 .enable_dma = sdhci_pci_enable_dma,
917 .set_bus_width = sdhci_set_bus_width,
918 .reset = sdhci_gl9750_reset,
919 .set_uhs_signaling = sdhci_set_uhs_signaling,
920 .voltage_switch = sdhci_gli_voltage_switch,
921 .platform_execute_tuning = gl9750_execute_tuning,
924 const struct sdhci_pci_fixes sdhci_gl9750 = {
925 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
926 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
927 .probe_slot = gli_probe_slot_gl9750,
928 .ops = &sdhci_gl9750_ops,
929 #ifdef CONFIG_PM_SLEEP
930 .resume = sdhci_pci_gli_resume,
934 static const struct sdhci_ops sdhci_gl9763e_ops = {
935 .set_clock = sdhci_set_clock,
936 .enable_dma = sdhci_pci_enable_dma,
937 .set_bus_width = sdhci_set_bus_width,
938 .reset = sdhci_gl9763e_reset,
939 .set_uhs_signaling = sdhci_set_gl9763e_signaling,
940 .voltage_switch = sdhci_gli_voltage_switch,
941 .irq = sdhci_gl9763e_cqhci_irq,
944 const struct sdhci_pci_fixes sdhci_gl9763e = {
945 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
946 .probe_slot = gli_probe_slot_gl9763e,
947 .ops = &sdhci_gl9763e_ops,
948 #ifdef CONFIG_PM_SLEEP
949 .resume = sdhci_cqhci_gli_resume,
950 .suspend = sdhci_cqhci_gli_suspend,
952 .add_host = gl9763e_add_host,