1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * Thanks to the following companies for their support:
8 * - JMicron (hardware and technical support)
11 #include <linux/bitfield.h>
12 #include <linux/string.h>
13 #include <linux/delay.h>
14 #include <linux/highmem.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/device.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/scatterlist.h>
24 #include <linux/iopoll.h>
25 #include <linux/gpio.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/mmc/sdhci-pci-data.h>
29 #include <linux/acpi.h>
30 #include <linux/dmi.h>
33 #include <asm/iosf_mbi.h>
39 #include "sdhci-pci.h"
41 static void sdhci_pci_hw_reset(struct sdhci_host *host);
43 #ifdef CONFIG_PM_SLEEP
44 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
46 mmc_pm_flag_t pm_flags = 0;
47 bool cap_cd_wake = false;
50 for (i = 0; i < chip->num_slots; i++) {
51 struct sdhci_pci_slot *slot = chip->slots[i];
54 pm_flags |= slot->host->mmc->pm_flags;
55 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
60 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
61 return device_wakeup_enable(&chip->pdev->dev);
62 else if (!cap_cd_wake)
63 return device_wakeup_disable(&chip->pdev->dev);
68 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
72 sdhci_pci_init_wakeup(chip);
74 for (i = 0; i < chip->num_slots; i++) {
75 struct sdhci_pci_slot *slot = chip->slots[i];
76 struct sdhci_host *host;
83 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
84 mmc_retune_needed(host->mmc);
86 ret = sdhci_suspend_host(host);
90 if (device_may_wakeup(&chip->pdev->dev))
91 mmc_gpio_set_cd_wake(host->mmc, true);
98 sdhci_resume_host(chip->slots[i]->host);
102 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
104 struct sdhci_pci_slot *slot;
107 for (i = 0; i < chip->num_slots; i++) {
108 slot = chip->slots[i];
112 ret = sdhci_resume_host(slot->host);
116 mmc_gpio_set_cd_wake(slot->host->mmc, false);
122 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
126 ret = cqhci_suspend(chip->slots[0]->host->mmc);
130 return sdhci_pci_suspend_host(chip);
133 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
137 ret = sdhci_pci_resume_host(chip);
141 return cqhci_resume(chip->slots[0]->host->mmc);
146 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
148 struct sdhci_pci_slot *slot;
149 struct sdhci_host *host;
152 for (i = 0; i < chip->num_slots; i++) {
153 slot = chip->slots[i];
159 ret = sdhci_runtime_suspend_host(host);
161 goto err_pci_runtime_suspend;
163 if (chip->rpm_retune &&
164 host->tuning_mode != SDHCI_TUNING_MODE_3)
165 mmc_retune_needed(host->mmc);
170 err_pci_runtime_suspend:
172 sdhci_runtime_resume_host(chip->slots[i]->host, 0);
176 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
178 struct sdhci_pci_slot *slot;
181 for (i = 0; i < chip->num_slots; i++) {
182 slot = chip->slots[i];
186 ret = sdhci_runtime_resume_host(slot->host, 0);
194 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
198 ret = cqhci_suspend(chip->slots[0]->host->mmc);
202 return sdhci_pci_runtime_suspend_host(chip);
205 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
209 ret = sdhci_pci_runtime_resume_host(chip);
213 return cqhci_resume(chip->slots[0]->host->mmc);
217 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
222 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
225 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
230 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
232 sdhci_dumpregs(mmc_priv(mmc));
235 /*****************************************************************************\
237 * Hardware specific quirk handling *
239 \*****************************************************************************/
241 static int ricoh_probe(struct sdhci_pci_chip *chip)
243 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
244 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
245 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
249 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
252 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
253 & SDHCI_TIMEOUT_CLK_MASK) |
255 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
256 & SDHCI_CLOCK_BASE_MASK) |
258 SDHCI_TIMEOUT_CLK_UNIT |
265 #ifdef CONFIG_PM_SLEEP
266 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
268 /* Apply a delay to allow controller to settle */
269 /* Otherwise it becomes confused if card state changed
272 return sdhci_pci_resume_host(chip);
276 static const struct sdhci_pci_fixes sdhci_ricoh = {
277 .probe = ricoh_probe,
278 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
279 SDHCI_QUIRK_FORCE_DMA |
280 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
283 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
284 .probe_slot = ricoh_mmc_probe_slot,
285 #ifdef CONFIG_PM_SLEEP
286 .resume = ricoh_mmc_resume,
288 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
289 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
290 SDHCI_QUIRK_NO_CARD_NO_RESET |
291 SDHCI_QUIRK_MISSING_CAPS
294 static const struct sdhci_pci_fixes sdhci_ene_712 = {
295 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
296 SDHCI_QUIRK_BROKEN_DMA,
299 static const struct sdhci_pci_fixes sdhci_ene_714 = {
300 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
301 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
302 SDHCI_QUIRK_BROKEN_DMA,
305 static const struct sdhci_pci_fixes sdhci_cafe = {
306 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
307 SDHCI_QUIRK_NO_BUSY_IRQ |
308 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
309 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
312 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
313 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
316 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
318 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
323 * ADMA operation is disabled for Moorestown platform due to
326 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
329 * slots number is fixed here for MRST as SDIO3/5 are never used and
330 * have hardware bugs.
336 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
338 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
344 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
346 struct sdhci_pci_slot *slot = dev_id;
347 struct sdhci_host *host = slot->host;
349 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
353 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
355 int err, irq, gpio = slot->cd_gpio;
357 slot->cd_gpio = -EINVAL;
358 slot->cd_irq = -EINVAL;
360 if (!gpio_is_valid(gpio))
363 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
367 err = gpio_direction_input(gpio);
371 irq = gpio_to_irq(gpio);
375 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
376 IRQF_TRIGGER_FALLING, "sd_cd", slot);
380 slot->cd_gpio = gpio;
386 devm_gpio_free(&slot->chip->pdev->dev, gpio);
388 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
391 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
393 if (slot->cd_irq >= 0)
394 free_irq(slot->cd_irq, slot);
399 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
403 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
409 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
411 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
412 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
416 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
418 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
422 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
423 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
424 .probe_slot = mrst_hc_probe_slot,
427 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
428 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
429 .probe = mrst_hc_probe,
432 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
433 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
434 .allow_runtime_pm = true,
435 .own_cd_for_runtime_pm = true,
438 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
440 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
441 .allow_runtime_pm = true,
442 .probe_slot = mfd_sdio_probe_slot,
445 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
446 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
447 .allow_runtime_pm = true,
448 .probe_slot = mfd_emmc_probe_slot,
451 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
452 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
453 .probe_slot = pch_hc_probe_slot,
458 #define BYT_IOSF_SCCEP 0x63
459 #define BYT_IOSF_OCP_NETCTRL0 0x1078
460 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
462 static void byt_ocp_setting(struct pci_dev *pdev)
466 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC &&
467 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO &&
468 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD &&
469 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2)
472 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
474 dev_err(&pdev->dev, "%s read error\n", __func__);
478 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
481 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
483 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
485 dev_err(&pdev->dev, "%s write error\n", __func__);
489 dev_dbg(&pdev->dev, "%s completed\n", __func__);
494 static inline void byt_ocp_setting(struct pci_dev *pdev)
502 INTEL_DSM_V18_SWITCH = 3,
503 INTEL_DSM_V33_SWITCH = 4,
504 INTEL_DSM_DRV_STRENGTH = 9,
505 INTEL_DSM_D3_RETUNE = 10,
517 static const guid_t intel_dsm_guid =
518 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
519 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
521 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
522 unsigned int fn, u32 *result)
524 union acpi_object *obj;
528 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
532 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
537 len = min_t(size_t, obj->buffer.length, 4);
540 memcpy(result, obj->buffer.pointer, len);
547 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
548 unsigned int fn, u32 *result)
550 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
553 return __intel_dsm(intel_host, dev, fn, result);
556 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
557 struct mmc_host *mmc)
562 intel_host->d3_retune = true;
564 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
566 pr_debug("%s: DSM not supported, error %d\n",
567 mmc_hostname(mmc), err);
571 pr_debug("%s: DSM function mask %#x\n",
572 mmc_hostname(mmc), intel_host->dsm_fns);
574 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
575 intel_host->drv_strength = err ? 0 : val;
577 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
578 intel_host->d3_retune = err ? true : !!val;
581 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
585 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
587 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
588 /* For eMMC, minimum is 1us but give it 9us for good measure */
591 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
592 /* For eMMC, minimum is 200us but give it 300us for good measure */
593 usleep_range(300, 1000);
596 static int intel_select_drive_strength(struct mmc_card *card,
597 unsigned int max_dtr, int host_drv,
598 int card_drv, int *drv_type)
600 struct sdhci_host *host = mmc_priv(card->host);
601 struct sdhci_pci_slot *slot = sdhci_priv(host);
602 struct intel_host *intel_host = sdhci_pci_priv(slot);
604 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv))
607 return intel_host->drv_strength;
610 static int bxt_get_cd(struct mmc_host *mmc)
612 int gpio_cd = mmc_gpio_get_cd(mmc);
613 struct sdhci_host *host = mmc_priv(mmc);
620 spin_lock_irqsave(&host->lock, flags);
622 if (host->flags & SDHCI_DEVICE_DEAD)
625 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
627 spin_unlock_irqrestore(&host->lock, flags);
632 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
633 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
635 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
641 sdhci_set_power(host, mode, vdd);
643 if (mode == MMC_POWER_OFF)
647 * Bus power might not enable after D3 -> D0 transition due to the
648 * present state not yet having propagated. Retry for up to 2ms.
650 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
651 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
652 if (reg & SDHCI_POWER_ON)
654 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
655 reg |= SDHCI_POWER_ON;
656 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
660 #define INTEL_HS400_ES_REG 0x78
661 #define INTEL_HS400_ES_BIT BIT(0)
663 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
666 struct sdhci_host *host = mmc_priv(mmc);
669 val = sdhci_readl(host, INTEL_HS400_ES_REG);
670 if (ios->enhanced_strobe)
671 val |= INTEL_HS400_ES_BIT;
673 val &= ~INTEL_HS400_ES_BIT;
674 sdhci_writel(host, val, INTEL_HS400_ES_REG);
677 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
680 struct device *dev = mmc_dev(mmc);
681 struct sdhci_host *host = mmc_priv(mmc);
682 struct sdhci_pci_slot *slot = sdhci_priv(host);
683 struct intel_host *intel_host = sdhci_pci_priv(slot);
688 err = sdhci_start_signal_voltage_switch(mmc, ios);
692 switch (ios->signal_voltage) {
693 case MMC_SIGNAL_VOLTAGE_330:
694 fn = INTEL_DSM_V33_SWITCH;
696 case MMC_SIGNAL_VOLTAGE_180:
697 fn = INTEL_DSM_V18_SWITCH;
703 err = intel_dsm(intel_host, dev, fn, &result);
704 pr_debug("%s: %s DSM fn %u error %d result %u\n",
705 mmc_hostname(mmc), __func__, fn, err, result);
710 static const struct sdhci_ops sdhci_intel_byt_ops = {
711 .set_clock = sdhci_set_clock,
712 .set_power = sdhci_intel_set_power,
713 .enable_dma = sdhci_pci_enable_dma,
714 .set_bus_width = sdhci_set_bus_width,
715 .reset = sdhci_reset,
716 .set_uhs_signaling = sdhci_set_uhs_signaling,
717 .hw_reset = sdhci_pci_hw_reset,
720 static const struct sdhci_ops sdhci_intel_glk_ops = {
721 .set_clock = sdhci_set_clock,
722 .set_power = sdhci_intel_set_power,
723 .enable_dma = sdhci_pci_enable_dma,
724 .set_bus_width = sdhci_set_bus_width,
725 .reset = sdhci_reset,
726 .set_uhs_signaling = sdhci_set_uhs_signaling,
727 .hw_reset = sdhci_pci_hw_reset,
728 .irq = sdhci_cqhci_irq,
731 static void byt_read_dsm(struct sdhci_pci_slot *slot)
733 struct intel_host *intel_host = sdhci_pci_priv(slot);
734 struct device *dev = &slot->chip->pdev->dev;
735 struct mmc_host *mmc = slot->host->mmc;
737 intel_dsm_init(intel_host, dev, mmc);
738 slot->chip->rpm_retune = intel_host->d3_retune;
741 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
743 int err = sdhci_execute_tuning(mmc, opcode);
744 struct sdhci_host *host = mmc_priv(mmc);
750 * Tuning can leave the IP in an active state (Buffer Read Enable bit
751 * set) which prevents the entry to low power states (i.e. S0i3). Data
752 * reset will clear it.
754 sdhci_reset(host, SDHCI_RESET_DATA);
759 static void byt_probe_slot(struct sdhci_pci_slot *slot)
761 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
762 struct device *dev = &slot->chip->pdev->dev;
763 struct mmc_host *mmc = slot->host->mmc;
767 byt_ocp_setting(slot->chip->pdev);
769 ops->execute_tuning = intel_execute_tuning;
770 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
772 device_property_read_u32(dev, "max-frequency", &mmc->f_max);
775 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
777 byt_probe_slot(slot);
778 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
779 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
780 MMC_CAP_CMD_DURING_TFR |
781 MMC_CAP_WAIT_WHILE_BUSY;
782 slot->hw_reset = sdhci_pci_int_hw_reset;
783 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
784 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
785 slot->host->mmc_host_ops.select_drive_strength =
786 intel_select_drive_strength;
790 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
792 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
793 dmi_match(DMI_BIOS_VENDOR, "LENOVO");
796 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
798 int ret = byt_emmc_probe_slot(slot);
800 if (!glk_broken_cqhci(slot))
801 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
803 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
804 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
805 slot->host->mmc_host_ops.hs400_enhanced_strobe =
806 intel_hs400_enhanced_strobe;
807 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
813 static const struct cqhci_host_ops glk_cqhci_ops = {
814 .enable = sdhci_cqe_enable,
815 .disable = sdhci_cqe_disable,
816 .dumpregs = sdhci_pci_dumpregs,
819 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
821 struct device *dev = &slot->chip->pdev->dev;
822 struct sdhci_host *host = slot->host;
823 struct cqhci_host *cq_host;
827 ret = sdhci_setup_host(host);
831 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
837 cq_host->mmio = host->ioaddr + 0x200;
838 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
839 cq_host->ops = &glk_cqhci_ops;
841 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
843 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
845 ret = cqhci_init(cq_host, host->mmc, dma64);
849 ret = __sdhci_add_host(host);
856 sdhci_cleanup_host(host);
861 #define GLK_RX_CTRL1 0x834
862 #define GLK_TUN_VAL 0x840
863 #define GLK_PATH_PLL GENMASK(13, 8)
864 #define GLK_DLY GENMASK(6, 0)
865 /* Workaround firmware failing to restore the tuning value */
866 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
868 struct sdhci_pci_slot *slot = chip->slots[0];
869 struct intel_host *intel_host = sdhci_pci_priv(slot);
870 struct sdhci_host *host = slot->host;
875 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
878 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
879 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
882 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
883 intel_host->glk_tun_val = glk_tun_val;
887 if (!intel_host->glk_tun_val)
890 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
891 intel_host->rpm_retune_ok = true;
895 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
896 (intel_host->glk_tun_val << 1));
897 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
900 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
901 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
903 intel_host->rpm_retune_ok = true;
904 chip->rpm_retune = true;
905 mmc_retune_needed(host->mmc);
906 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
909 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
911 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
913 glk_rpm_retune_wa(chip, susp);
916 static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
918 glk_rpm_retune_chk(chip, true);
920 return sdhci_cqhci_runtime_suspend(chip);
923 static int glk_runtime_resume(struct sdhci_pci_chip *chip)
925 glk_rpm_retune_chk(chip, false);
927 return sdhci_cqhci_runtime_resume(chip);
932 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
935 unsigned long long max_freq;
937 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
938 "MXFQ", NULL, &max_freq);
939 if (ACPI_FAILURE(status)) {
940 dev_err(&slot->chip->pdev->dev,
941 "MXFQ not found in acpi table\n");
945 slot->host->mmc->f_max = max_freq * 1000000;
950 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
956 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
960 byt_probe_slot(slot);
962 err = ni_set_max_freq(slot);
966 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
967 MMC_CAP_WAIT_WHILE_BUSY;
971 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
973 byt_probe_slot(slot);
974 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
975 MMC_CAP_WAIT_WHILE_BUSY;
979 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
981 byt_probe_slot(slot);
982 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
983 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
985 slot->cd_override_level = true;
986 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
987 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
988 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
989 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
990 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
992 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
993 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
994 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
999 #ifdef CONFIG_PM_SLEEP
1001 static int byt_resume(struct sdhci_pci_chip *chip)
1003 byt_ocp_setting(chip->pdev);
1005 return sdhci_pci_resume_host(chip);
1012 static int byt_runtime_resume(struct sdhci_pci_chip *chip)
1014 byt_ocp_setting(chip->pdev);
1016 return sdhci_pci_runtime_resume_host(chip);
1021 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
1022 #ifdef CONFIG_PM_SLEEP
1023 .resume = byt_resume,
1026 .runtime_resume = byt_runtime_resume,
1028 .allow_runtime_pm = true,
1029 .probe_slot = byt_emmc_probe_slot,
1030 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1032 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1033 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1034 SDHCI_QUIRK2_STOP_WITH_TC,
1035 .ops = &sdhci_intel_byt_ops,
1036 .priv_size = sizeof(struct intel_host),
1039 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
1040 .allow_runtime_pm = true,
1041 .probe_slot = glk_emmc_probe_slot,
1042 .add_host = glk_emmc_add_host,
1043 #ifdef CONFIG_PM_SLEEP
1044 .suspend = sdhci_cqhci_suspend,
1045 .resume = sdhci_cqhci_resume,
1048 .runtime_suspend = glk_runtime_suspend,
1049 .runtime_resume = glk_runtime_resume,
1051 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1053 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1054 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1055 SDHCI_QUIRK2_STOP_WITH_TC,
1056 .ops = &sdhci_intel_glk_ops,
1057 .priv_size = sizeof(struct intel_host),
1060 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
1061 #ifdef CONFIG_PM_SLEEP
1062 .resume = byt_resume,
1065 .runtime_resume = byt_runtime_resume,
1067 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1069 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1070 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1071 .allow_runtime_pm = true,
1072 .probe_slot = ni_byt_sdio_probe_slot,
1073 .ops = &sdhci_intel_byt_ops,
1074 .priv_size = sizeof(struct intel_host),
1077 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
1078 #ifdef CONFIG_PM_SLEEP
1079 .resume = byt_resume,
1082 .runtime_resume = byt_runtime_resume,
1084 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1086 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1087 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1088 .allow_runtime_pm = true,
1089 .probe_slot = byt_sdio_probe_slot,
1090 .ops = &sdhci_intel_byt_ops,
1091 .priv_size = sizeof(struct intel_host),
1094 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
1095 #ifdef CONFIG_PM_SLEEP
1096 .resume = byt_resume,
1099 .runtime_resume = byt_runtime_resume,
1101 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1103 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1104 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1105 SDHCI_QUIRK2_STOP_WITH_TC,
1106 .allow_runtime_pm = true,
1107 .own_cd_for_runtime_pm = true,
1108 .probe_slot = byt_sd_probe_slot,
1109 .ops = &sdhci_intel_byt_ops,
1110 .priv_size = sizeof(struct intel_host),
1113 /* Define Host controllers for Intel Merrifield platform */
1114 #define INTEL_MRFLD_EMMC_0 0
1115 #define INTEL_MRFLD_EMMC_1 1
1116 #define INTEL_MRFLD_SD 2
1117 #define INTEL_MRFLD_SDIO 3
1120 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1122 struct acpi_device *device, *child;
1124 device = ACPI_COMPANION(&slot->chip->pdev->dev);
1128 acpi_device_fix_up_power(device);
1129 list_for_each_entry(child, &device->children, node)
1130 if (child->status.present && child->status.enabled)
1131 acpi_device_fix_up_power(child);
1134 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1137 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
1139 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1142 case INTEL_MRFLD_EMMC_0:
1143 case INTEL_MRFLD_EMMC_1:
1144 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1145 MMC_CAP_8_BIT_DATA |
1148 case INTEL_MRFLD_SD:
1149 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1151 case INTEL_MRFLD_SDIO:
1152 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1153 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
1154 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1155 MMC_CAP_POWER_OFF_CARD;
1161 intel_mrfld_mmc_fix_up_power_slot(slot);
1165 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
1166 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1167 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
1168 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1169 .allow_runtime_pm = true,
1170 .probe_slot = intel_mrfld_mmc_probe_slot,
1173 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1178 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1183 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1184 * [bit 1:2] and enable over current debouncing [bit 6].
1191 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
1194 static int jmicron_probe(struct sdhci_pci_chip *chip)
1199 if (chip->pdev->revision == 0) {
1200 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1201 SDHCI_QUIRK_32BIT_DMA_SIZE |
1202 SDHCI_QUIRK_32BIT_ADMA_SIZE |
1203 SDHCI_QUIRK_RESET_AFTER_REQUEST |
1204 SDHCI_QUIRK_BROKEN_SMALL_PIO;
1208 * JMicron chips can have two interfaces to the same hardware
1209 * in order to work around limitations in Microsoft's driver.
1210 * We need to make sure we only bind to one of them.
1212 * This code assumes two things:
1214 * 1. The PCI code adds subfunctions in order.
1216 * 2. The MMC interface has a lower subfunction number
1217 * than the SD interface.
1219 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1220 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1221 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1222 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1225 struct pci_dev *sd_dev;
1228 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1229 mmcdev, sd_dev)) != NULL) {
1230 if ((PCI_SLOT(chip->pdev->devfn) ==
1231 PCI_SLOT(sd_dev->devfn)) &&
1232 (chip->pdev->bus == sd_dev->bus))
1237 pci_dev_put(sd_dev);
1238 dev_info(&chip->pdev->dev, "Refusing to bind to "
1239 "secondary interface.\n");
1245 * JMicron chips need a bit of a nudge to enable the power
1248 ret = jmicron_pmos(chip, 1);
1250 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1254 /* quirk for unsable RO-detection on JM388 chips */
1255 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1256 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1257 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1262 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1266 scratch = readb(host->ioaddr + 0xC0);
1273 writeb(scratch, host->ioaddr + 0xC0);
1276 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1278 if (slot->chip->pdev->revision == 0) {
1281 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1282 version = (version & SDHCI_VENDOR_VER_MASK) >>
1283 SDHCI_VENDOR_VER_SHIFT;
1286 * Older versions of the chip have lots of nasty glitches
1287 * in the ADMA engine. It's best just to avoid it
1291 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1294 /* JM388 MMC doesn't support 1.8V while SD supports it */
1295 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1296 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1297 MMC_VDD_29_30 | MMC_VDD_30_31 |
1298 MMC_VDD_165_195; /* allow 1.8V */
1299 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1300 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1304 * The secondary interface requires a bit set to get the
1307 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1308 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1309 jmicron_enable_mmc(slot->host, 1);
1311 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1316 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1321 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1322 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1323 jmicron_enable_mmc(slot->host, 0);
1326 #ifdef CONFIG_PM_SLEEP
1327 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1331 ret = sdhci_pci_suspend_host(chip);
1335 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1336 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1337 for (i = 0; i < chip->num_slots; i++)
1338 jmicron_enable_mmc(chip->slots[i]->host, 0);
1344 static int jmicron_resume(struct sdhci_pci_chip *chip)
1348 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1349 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1350 for (i = 0; i < chip->num_slots; i++)
1351 jmicron_enable_mmc(chip->slots[i]->host, 1);
1354 ret = jmicron_pmos(chip, 1);
1356 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1360 return sdhci_pci_resume_host(chip);
1364 static const struct sdhci_pci_fixes sdhci_jmicron = {
1365 .probe = jmicron_probe,
1367 .probe_slot = jmicron_probe_slot,
1368 .remove_slot = jmicron_remove_slot,
1370 #ifdef CONFIG_PM_SLEEP
1371 .suspend = jmicron_suspend,
1372 .resume = jmicron_resume,
1376 /* SysKonnect CardBus2SDIO extra registers */
1377 #define SYSKT_CTRL 0x200
1378 #define SYSKT_RDFIFO_STAT 0x204
1379 #define SYSKT_WRFIFO_STAT 0x208
1380 #define SYSKT_POWER_DATA 0x20c
1381 #define SYSKT_POWER_330 0xef
1382 #define SYSKT_POWER_300 0xf8
1383 #define SYSKT_POWER_184 0xcc
1384 #define SYSKT_POWER_CMD 0x20d
1385 #define SYSKT_POWER_START (1 << 7)
1386 #define SYSKT_POWER_STATUS 0x20e
1387 #define SYSKT_POWER_STATUS_OK (1 << 0)
1388 #define SYSKT_BOARD_REV 0x210
1389 #define SYSKT_CHIP_REV 0x211
1390 #define SYSKT_CONF_DATA 0x212
1391 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1392 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1393 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1395 static int syskt_probe(struct sdhci_pci_chip *chip)
1397 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1398 chip->pdev->class &= ~0x0000FF;
1399 chip->pdev->class |= PCI_SDHCI_IFDMA;
1404 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1408 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1409 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1410 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1411 "board rev %d.%d, chip rev %d.%d\n",
1412 board_rev >> 4, board_rev & 0xf,
1413 chip_rev >> 4, chip_rev & 0xf);
1414 if (chip_rev >= 0x20)
1415 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1417 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1418 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1420 tm = 10; /* Wait max 1 ms */
1422 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1423 if (ps & SYSKT_POWER_STATUS_OK)
1428 dev_err(&slot->chip->pdev->dev,
1429 "power regulator never stabilized");
1430 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1437 static const struct sdhci_pci_fixes sdhci_syskt = {
1438 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1439 .probe = syskt_probe,
1440 .probe_slot = syskt_probe_slot,
1443 static int via_probe(struct sdhci_pci_chip *chip)
1445 if (chip->pdev->revision == 0x10)
1446 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1451 static const struct sdhci_pci_fixes sdhci_via = {
1455 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1457 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1461 static const struct sdhci_pci_fixes sdhci_rtsx = {
1462 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1463 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1464 SDHCI_QUIRK2_BROKEN_DDR50,
1465 .probe_slot = rtsx_probe_slot,
1468 /*AMD chipset generation*/
1469 enum amd_chipset_gen {
1470 AMD_CHIPSET_BEFORE_ML,
1473 AMD_CHIPSET_UNKNOWN,
1477 #define AMD_SD_AUTO_PATTERN 0xB8
1478 #define AMD_MSLEEP_DURATION 4
1479 #define AMD_SD_MISC_CONTROL 0xD0
1480 #define AMD_MAX_TUNE_VALUE 0x0B
1481 #define AMD_AUTO_TUNE_SEL 0x10800
1482 #define AMD_FIFO_PTR 0x30
1483 #define AMD_BIT_MASK 0x1F
1485 static void amd_tuning_reset(struct sdhci_host *host)
1489 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1490 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1491 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1493 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1494 val &= ~SDHCI_CTRL_EXEC_TUNING;
1495 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1498 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1502 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1503 val &= ~AMD_BIT_MASK;
1504 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1505 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1508 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1512 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1513 val |= AMD_FIFO_PTR;
1514 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1517 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1519 struct sdhci_pci_slot *slot = sdhci_priv(host);
1520 struct pci_dev *pdev = slot->chip->pdev;
1522 u8 valid_win_max = 0;
1523 u8 valid_win_end = 0;
1524 u8 ctrl, tune_around;
1526 amd_tuning_reset(host);
1528 for (tune_around = 0; tune_around < 12; tune_around++) {
1529 amd_config_tuning_phase(pdev, tune_around);
1531 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1533 msleep(AMD_MSLEEP_DURATION);
1534 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1535 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1536 } else if (++valid_win > valid_win_max) {
1537 valid_win_max = valid_win;
1538 valid_win_end = tune_around;
1542 if (!valid_win_max) {
1543 dev_err(&pdev->dev, "no tuning point found\n");
1547 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1549 amd_enable_manual_tuning(pdev);
1551 host->mmc->retune_period = 0;
1556 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1558 struct sdhci_host *host = mmc_priv(mmc);
1560 /* AMD requires custom HS200 tuning */
1561 if (host->timing == MMC_TIMING_MMC_HS200)
1562 return amd_execute_tuning_hs200(host, opcode);
1564 /* Otherwise perform standard SDHCI tuning */
1565 return sdhci_execute_tuning(mmc, opcode);
1568 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1570 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1572 ops->execute_tuning = amd_execute_tuning;
1577 static int amd_probe(struct sdhci_pci_chip *chip)
1579 struct pci_dev *smbus_dev;
1580 enum amd_chipset_gen gen;
1582 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1583 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1585 gen = AMD_CHIPSET_BEFORE_ML;
1587 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1588 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1590 if (smbus_dev->revision < 0x51)
1591 gen = AMD_CHIPSET_CZ;
1593 gen = AMD_CHIPSET_NL;
1595 gen = AMD_CHIPSET_UNKNOWN;
1599 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1600 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1605 static u32 sdhci_read_present_state(struct sdhci_host *host)
1607 return sdhci_readl(host, SDHCI_PRESENT_STATE);
1610 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
1612 struct sdhci_pci_slot *slot = sdhci_priv(host);
1613 struct pci_dev *pdev = slot->chip->pdev;
1617 * SDHC 0x7906 requires a hard reset to clear all internal state.
1618 * Otherwise it can get into a bad state where the DATA lines are always
1621 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) {
1622 pci_clear_master(pdev);
1624 pci_save_state(pdev);
1626 pci_set_power_state(pdev, PCI_D3cold);
1627 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc),
1628 pdev->current_state);
1629 pci_set_power_state(pdev, PCI_D0);
1631 pci_restore_state(pdev);
1634 * SDHCI_RESET_ALL says the card detect logic should not be
1635 * reset, but since we need to reset the entire controller
1636 * we should wait until the card detect logic has stabilized.
1638 * This normally takes about 40ms.
1641 sdhci_read_present_state,
1644 present_state & SDHCI_CD_STABLE,
1650 return sdhci_reset(host, mask);
1653 static const struct sdhci_ops amd_sdhci_pci_ops = {
1654 .set_clock = sdhci_set_clock,
1655 .enable_dma = sdhci_pci_enable_dma,
1656 .set_bus_width = sdhci_set_bus_width,
1657 .reset = amd_sdhci_reset,
1658 .set_uhs_signaling = sdhci_set_uhs_signaling,
1661 static const struct sdhci_pci_fixes sdhci_amd = {
1663 .ops = &amd_sdhci_pci_ops,
1664 .probe_slot = amd_probe_slot,
1667 static const struct pci_device_id pci_ids[] = {
1668 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1669 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1670 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1671 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1672 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1673 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1674 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1675 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1676 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1677 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1678 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1679 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1680 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1681 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1682 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1683 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1684 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1685 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1686 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1687 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1688 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1689 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1690 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1691 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1692 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1693 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1694 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1695 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1696 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1697 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1698 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1699 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1700 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1701 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1702 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1703 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1704 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1705 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1706 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1707 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1708 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1709 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1710 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1711 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1712 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1713 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1714 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1715 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1716 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1717 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1718 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1719 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1720 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1721 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1722 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1723 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1724 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1725 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1726 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1727 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1728 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1729 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc),
1730 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd),
1731 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc),
1732 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd),
1733 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc),
1734 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd),
1735 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd),
1736 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc),
1737 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd),
1738 SDHCI_PCI_DEVICE(O2, 8120, o2),
1739 SDHCI_PCI_DEVICE(O2, 8220, o2),
1740 SDHCI_PCI_DEVICE(O2, 8221, o2),
1741 SDHCI_PCI_DEVICE(O2, 8320, o2),
1742 SDHCI_PCI_DEVICE(O2, 8321, o2),
1743 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1744 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1745 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1746 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1747 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1748 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1749 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
1750 SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
1751 SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
1752 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1753 /* Generic SD host controller */
1754 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1755 { /* end: all zeroes */ },
1758 MODULE_DEVICE_TABLE(pci, pci_ids);
1760 /*****************************************************************************\
1762 * SDHCI core callbacks *
1764 \*****************************************************************************/
1766 int sdhci_pci_enable_dma(struct sdhci_host *host)
1768 struct sdhci_pci_slot *slot;
1769 struct pci_dev *pdev;
1771 slot = sdhci_priv(host);
1772 pdev = slot->chip->pdev;
1774 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1775 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1776 (host->flags & SDHCI_USE_SDMA)) {
1777 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1778 "doesn't fully claim to support it.\n");
1781 pci_set_master(pdev);
1786 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1788 struct sdhci_pci_slot *slot = sdhci_priv(host);
1789 int rst_n_gpio = slot->rst_n_gpio;
1791 if (!gpio_is_valid(rst_n_gpio))
1793 gpio_set_value_cansleep(rst_n_gpio, 0);
1794 /* For eMMC, minimum is 1us but give it 10us for good measure */
1796 gpio_set_value_cansleep(rst_n_gpio, 1);
1797 /* For eMMC, minimum is 200us but give it 300us for good measure */
1798 usleep_range(300, 1000);
1801 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1803 struct sdhci_pci_slot *slot = sdhci_priv(host);
1806 slot->hw_reset(host);
1809 static const struct sdhci_ops sdhci_pci_ops = {
1810 .set_clock = sdhci_set_clock,
1811 .enable_dma = sdhci_pci_enable_dma,
1812 .set_bus_width = sdhci_set_bus_width,
1813 .reset = sdhci_reset,
1814 .set_uhs_signaling = sdhci_set_uhs_signaling,
1815 .hw_reset = sdhci_pci_hw_reset,
1818 /*****************************************************************************\
1822 \*****************************************************************************/
1824 #ifdef CONFIG_PM_SLEEP
1825 static int sdhci_pci_suspend(struct device *dev)
1827 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
1832 if (chip->fixes && chip->fixes->suspend)
1833 return chip->fixes->suspend(chip);
1835 return sdhci_pci_suspend_host(chip);
1838 static int sdhci_pci_resume(struct device *dev)
1840 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
1845 if (chip->fixes && chip->fixes->resume)
1846 return chip->fixes->resume(chip);
1848 return sdhci_pci_resume_host(chip);
1853 static int sdhci_pci_runtime_suspend(struct device *dev)
1855 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
1860 if (chip->fixes && chip->fixes->runtime_suspend)
1861 return chip->fixes->runtime_suspend(chip);
1863 return sdhci_pci_runtime_suspend_host(chip);
1866 static int sdhci_pci_runtime_resume(struct device *dev)
1868 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
1873 if (chip->fixes && chip->fixes->runtime_resume)
1874 return chip->fixes->runtime_resume(chip);
1876 return sdhci_pci_runtime_resume_host(chip);
1880 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1881 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1882 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1883 sdhci_pci_runtime_resume, NULL)
1886 /*****************************************************************************\
1888 * Device probing/removal *
1890 \*****************************************************************************/
1892 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1893 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1896 struct sdhci_pci_slot *slot;
1897 struct sdhci_host *host;
1898 int ret, bar = first_bar + slotno;
1899 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1901 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1902 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1903 return ERR_PTR(-ENODEV);
1906 if (pci_resource_len(pdev, bar) < 0x100) {
1907 dev_err(&pdev->dev, "Invalid iomem size. You may "
1908 "experience problems.\n");
1911 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1912 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1913 return ERR_PTR(-ENODEV);
1916 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1917 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1918 return ERR_PTR(-ENODEV);
1921 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1923 dev_err(&pdev->dev, "cannot allocate host\n");
1924 return ERR_CAST(host);
1927 slot = sdhci_priv(host);
1931 slot->rst_n_gpio = -EINVAL;
1932 slot->cd_gpio = -EINVAL;
1935 /* Retrieve platform data if there is any */
1936 if (*sdhci_pci_get_data)
1937 slot->data = sdhci_pci_get_data(pdev, slotno);
1940 if (slot->data->setup) {
1941 ret = slot->data->setup(slot->data);
1943 dev_err(&pdev->dev, "platform setup failed\n");
1947 slot->rst_n_gpio = slot->data->rst_n_gpio;
1948 slot->cd_gpio = slot->data->cd_gpio;
1951 host->hw_name = "PCI";
1952 host->ops = chip->fixes && chip->fixes->ops ?
1955 host->quirks = chip->quirks;
1956 host->quirks2 = chip->quirks2;
1958 host->irq = pdev->irq;
1960 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1962 dev_err(&pdev->dev, "cannot request region\n");
1966 host->ioaddr = pcim_iomap_table(pdev)[bar];
1968 if (chip->fixes && chip->fixes->probe_slot) {
1969 ret = chip->fixes->probe_slot(slot);
1974 if (gpio_is_valid(slot->rst_n_gpio)) {
1975 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1976 gpio_direction_output(slot->rst_n_gpio, 1);
1977 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1978 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1980 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1981 slot->rst_n_gpio = -EINVAL;
1985 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
1986 host->mmc->slotno = slotno;
1987 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1989 if (device_can_wakeup(&pdev->dev))
1990 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1992 if (host->mmc->caps & MMC_CAP_CD_WAKE)
1993 device_init_wakeup(&pdev->dev, true);
1995 if (slot->cd_idx >= 0) {
1996 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
1997 slot->cd_override_level, 0);
1998 if (ret && ret != -EPROBE_DEFER)
1999 ret = mmc_gpiod_request_cd(host->mmc, NULL,
2001 slot->cd_override_level,
2003 if (ret == -EPROBE_DEFER)
2007 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
2012 if (chip->fixes && chip->fixes->add_host)
2013 ret = chip->fixes->add_host(slot);
2015 ret = sdhci_add_host(host);
2019 sdhci_pci_add_own_cd(slot);
2022 * Check if the chip needs a separate GPIO for card detect to wake up
2023 * from runtime suspend. If it is not there, don't allow runtime PM.
2024 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
2026 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
2027 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
2028 chip->allow_runtime_pm = false;
2033 if (chip->fixes && chip->fixes->remove_slot)
2034 chip->fixes->remove_slot(slot, 0);
2037 if (slot->data && slot->data->cleanup)
2038 slot->data->cleanup(slot->data);
2041 sdhci_free_host(host);
2043 return ERR_PTR(ret);
2046 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
2051 sdhci_pci_remove_own_cd(slot);
2054 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
2055 if (scratch == (u32)-1)
2058 sdhci_remove_host(slot->host, dead);
2060 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
2061 slot->chip->fixes->remove_slot(slot, dead);
2063 if (slot->data && slot->data->cleanup)
2064 slot->data->cleanup(slot->data);
2066 sdhci_free_host(slot->host);
2069 static void sdhci_pci_runtime_pm_allow(struct device *dev)
2071 pm_suspend_ignore_children(dev, 1);
2072 pm_runtime_set_autosuspend_delay(dev, 50);
2073 pm_runtime_use_autosuspend(dev);
2074 pm_runtime_allow(dev);
2075 /* Stay active until mmc core scans for a card */
2076 pm_runtime_put_noidle(dev);
2079 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
2081 pm_runtime_forbid(dev);
2082 pm_runtime_get_noresume(dev);
2085 static int sdhci_pci_probe(struct pci_dev *pdev,
2086 const struct pci_device_id *ent)
2088 struct sdhci_pci_chip *chip;
2089 struct sdhci_pci_slot *slot;
2091 u8 slots, first_bar;
2094 BUG_ON(pdev == NULL);
2095 BUG_ON(ent == NULL);
2097 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
2098 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
2100 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
2104 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
2105 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
2107 BUG_ON(slots > MAX_SLOTS);
2109 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
2113 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
2115 if (first_bar > 5) {
2116 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
2120 ret = pcim_enable_device(pdev);
2124 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
2129 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
2131 chip->quirks = chip->fixes->quirks;
2132 chip->quirks2 = chip->fixes->quirks2;
2133 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
2135 chip->num_slots = slots;
2136 chip->pm_retune = true;
2137 chip->rpm_retune = true;
2139 pci_set_drvdata(pdev, chip);
2141 if (chip->fixes && chip->fixes->probe) {
2142 ret = chip->fixes->probe(chip);
2147 slots = chip->num_slots; /* Quirk may have changed this */
2149 for (i = 0; i < slots; i++) {
2150 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
2152 for (i--; i >= 0; i--)
2153 sdhci_pci_remove_slot(chip->slots[i]);
2154 return PTR_ERR(slot);
2157 chip->slots[i] = slot;
2160 if (chip->allow_runtime_pm)
2161 sdhci_pci_runtime_pm_allow(&pdev->dev);
2166 static void sdhci_pci_remove(struct pci_dev *pdev)
2169 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
2171 if (chip->allow_runtime_pm)
2172 sdhci_pci_runtime_pm_forbid(&pdev->dev);
2174 for (i = 0; i < chip->num_slots; i++)
2175 sdhci_pci_remove_slot(chip->slots[i]);
2178 static struct pci_driver sdhci_driver = {
2179 .name = "sdhci-pci",
2180 .id_table = pci_ids,
2181 .probe = sdhci_pci_probe,
2182 .remove = sdhci_pci_remove,
2184 .pm = &sdhci_pci_pm_ops
2188 module_pci_driver(sdhci_driver);
2190 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2191 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2192 MODULE_LICENSE("GPL");