2 * SDHCI Controller driver for TI's OMAP SoCs
4 * Copyright (C) 2017 Texas Instruments
5 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/delay.h>
21 #include <linux/mmc/slot-gpio.h>
22 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/sys_soc.h>
30 #include <linux/thermal.h>
32 #include "sdhci-pltfm.h"
34 #define SDHCI_OMAP_CON 0x12c
35 #define CON_DW8 BIT(5)
36 #define CON_DMA_MASTER BIT(20)
37 #define CON_DDR BIT(19)
38 #define CON_CLKEXTFREE BIT(16)
39 #define CON_PADEN BIT(15)
40 #define CON_CTPL BIT(11)
41 #define CON_INIT BIT(1)
44 #define SDHCI_OMAP_DLL 0x0134
45 #define DLL_SWT BIT(20)
46 #define DLL_FORCE_SR_C_SHIFT 13
47 #define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
48 #define DLL_FORCE_VALUE BIT(12)
49 #define DLL_CALIB BIT(1)
51 #define SDHCI_OMAP_CMD 0x20c
53 #define SDHCI_OMAP_PSTATE 0x0224
54 #define PSTATE_DLEV_DAT0 BIT(20)
55 #define PSTATE_DATI BIT(1)
57 #define SDHCI_OMAP_HCTL 0x228
58 #define HCTL_SDBP BIT(8)
59 #define HCTL_SDVS_SHIFT 9
60 #define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT)
61 #define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT)
62 #define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT)
63 #define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT)
65 #define SDHCI_OMAP_SYSCTL 0x22c
66 #define SYSCTL_CEN BIT(2)
67 #define SYSCTL_CLKD_SHIFT 6
68 #define SYSCTL_CLKD_MASK 0x3ff
70 #define SDHCI_OMAP_STAT 0x230
72 #define SDHCI_OMAP_IE 0x234
73 #define INT_CC_EN BIT(0)
75 #define SDHCI_OMAP_AC12 0x23c
76 #define AC12_V1V8_SIGEN BIT(19)
77 #define AC12_SCLK_SEL BIT(23)
79 #define SDHCI_OMAP_CAPA 0x240
80 #define CAPA_VS33 BIT(24)
81 #define CAPA_VS30 BIT(25)
82 #define CAPA_VS18 BIT(26)
84 #define SDHCI_OMAP_CAPA2 0x0244
85 #define CAPA2_TSDR50 BIT(13)
87 #define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
89 #define SYSCTL_CLKD_MAX 0x3FF
91 #define IOV_1V8 1800000 /* 180000 uV */
92 #define IOV_3V0 3000000 /* 300000 uV */
93 #define IOV_3V3 3300000 /* 330000 uV */
95 #define MAX_PHASE_DELAY 0x7C
97 /* sdhci-omap controller flags */
98 #define SDHCI_OMAP_REQUIRE_IODELAY BIT(0)
100 struct sdhci_omap_data {
105 struct sdhci_omap_host {
109 struct regulator *pbias;
111 struct sdhci_host *host;
117 struct pinctrl *pinctrl;
118 struct pinctrl_state **pinctrl_state;
122 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
123 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
125 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
128 return readl(host->base + offset);
131 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
132 unsigned int offset, u32 data)
134 writel(data, host->base + offset);
137 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
138 bool power_on, unsigned int iov)
141 struct device *dev = omap_host->dev;
143 if (IS_ERR(omap_host->pbias))
147 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
149 dev_err(dev, "pbias set voltage failed\n");
153 if (omap_host->pbias_enabled)
156 ret = regulator_enable(omap_host->pbias);
158 dev_err(dev, "pbias reg enable fail\n");
162 omap_host->pbias_enabled = true;
164 if (!omap_host->pbias_enabled)
167 ret = regulator_disable(omap_host->pbias);
169 dev_err(dev, "pbias reg disable fail\n");
172 omap_host->pbias_enabled = false;
178 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
182 struct sdhci_host *host = omap_host->host;
183 struct mmc_host *mmc = host->mmc;
185 ret = sdhci_omap_set_pbias(omap_host, false, 0);
189 if (!IS_ERR(mmc->supply.vqmmc)) {
190 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
192 dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
197 ret = sdhci_omap_set_pbias(omap_host, true, iov);
204 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
205 unsigned char signal_voltage)
210 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
211 reg &= ~HCTL_SDVS_MASK;
213 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
218 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
221 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
224 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
226 bool timedout = ktime_after(ktime_get(), timeout);
228 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
230 if (WARN_ON(timedout))
236 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
238 struct sdhci_host *host = mmc_priv(mmc);
239 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
240 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
243 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
245 reg |= (CON_CTPL | CON_CLKEXTFREE);
247 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
248 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
250 sdhci_enable_sdio_irq(mmc, enable);
253 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
259 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
260 reg |= DLL_FORCE_VALUE;
261 reg &= ~DLL_FORCE_SR_C_MASK;
262 reg |= (count << DLL_FORCE_SR_C_SHIFT);
263 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
266 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
267 for (i = 0; i < 1000; i++) {
268 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
273 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
276 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
280 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
281 reg &= ~AC12_SCLK_SEL;
282 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
284 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
285 reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
286 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
289 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
291 struct sdhci_host *host = mmc_priv(mmc);
292 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
293 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
294 struct thermal_zone_device *thermal_dev;
295 struct device *dev = omap_host->dev;
296 struct mmc_ios *ios = &mmc->ios;
297 u32 start_window = 0, max_window = 0;
298 bool single_point_failure = false;
299 bool dcrc_was_enabled = false;
300 u8 cur_match, prev_match = 0;
301 u32 length = 0, max_len = 0;
308 /* clock tuning is not needed for upto 52MHz */
309 if (ios->clock <= 52000000)
312 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
313 if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
316 thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
317 if (IS_ERR(thermal_dev)) {
318 dev_err(dev, "Unable to get thermal zone for tuning\n");
319 return PTR_ERR(thermal_dev);
322 ret = thermal_zone_get_temp(thermal_dev, &temperature);
326 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
328 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
331 * OMAP5/DRA74X/DRA72x Errata i802:
332 * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
333 * during the tuning procedure. So disable it during the
336 if (host->ier & SDHCI_INT_DATA_CRC) {
337 host->ier &= ~SDHCI_INT_DATA_CRC;
338 dcrc_was_enabled = true;
341 omap_host->is_tuning = true;
344 * Stage 1: Search for a maximum pass window ignoring any
345 * any single point failures. If the tuning value ends up
346 * near it, move away from it in stage 2 below
348 while (phase_delay <= MAX_PHASE_DELAY) {
349 sdhci_omap_set_dll(omap_host, phase_delay);
351 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
355 } else if (single_point_failure) {
356 /* ignore single point failure */
359 start_window = phase_delay;
363 single_point_failure = prev_match;
366 if (length > max_len) {
367 max_window = start_window;
371 prev_match = cur_match;
376 dev_err(dev, "Unable to find match\n");
382 * Assign tuning value as a ratio of maximum pass window based
385 if (temperature < -20000)
386 phase_delay = min(max_window + 4 * max_len - 24,
388 DIV_ROUND_UP(13 * max_len, 16) * 4);
389 else if (temperature < 20000)
390 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
391 else if (temperature < 40000)
392 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
393 else if (temperature < 70000)
394 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
395 else if (temperature < 90000)
396 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
397 else if (temperature < 120000)
398 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
400 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
403 * Stage 2: Search for a single point failure near the chosen tuning
404 * value in two steps. First in the +3 to +10 range and then in the
405 * +2 to -10 range. If found, move away from it in the appropriate
406 * direction by the appropriate amount depending on the temperature.
408 for (i = 3; i <= 10; i++) {
409 sdhci_omap_set_dll(omap_host, phase_delay + i);
411 if (mmc_send_tuning(mmc, opcode, NULL)) {
412 if (temperature < 10000)
413 phase_delay += i + 6;
414 else if (temperature < 20000)
415 phase_delay += i - 12;
416 else if (temperature < 70000)
417 phase_delay += i - 8;
419 phase_delay += i - 6;
421 goto single_failure_found;
425 for (i = 2; i >= -10; i--) {
426 sdhci_omap_set_dll(omap_host, phase_delay + i);
428 if (mmc_send_tuning(mmc, opcode, NULL)) {
429 if (temperature < 10000)
430 phase_delay += i + 12;
431 else if (temperature < 20000)
432 phase_delay += i + 8;
433 else if (temperature < 70000)
434 phase_delay += i + 8;
435 else if (temperature < 90000)
436 phase_delay += i + 10;
438 phase_delay += i + 12;
440 goto single_failure_found;
444 single_failure_found:
445 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
446 if (!(reg & AC12_SCLK_SEL)) {
451 sdhci_omap_set_dll(omap_host, phase_delay);
453 omap_host->is_tuning = false;
458 omap_host->is_tuning = false;
459 dev_err(dev, "Tuning failed\n");
460 sdhci_omap_disable_tuning(omap_host);
463 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
464 /* Reenable forbidden interrupt */
465 if (dcrc_was_enabled)
466 host->ier |= SDHCI_INT_DATA_CRC;
467 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
468 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
472 static int sdhci_omap_card_busy(struct mmc_host *mmc)
476 struct sdhci_host *host = mmc_priv(mmc);
477 struct sdhci_pltfm_host *pltfm_host;
478 struct sdhci_omap_host *omap_host;
481 pltfm_host = sdhci_priv(host);
482 omap_host = sdhci_pltfm_priv(pltfm_host);
484 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
485 ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
486 reg &= ~CON_CLKEXTFREE;
487 if (ac12 & AC12_V1V8_SIGEN)
488 reg |= CON_CLKEXTFREE;
490 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
492 disable_irq(host->irq);
493 ier |= SDHCI_INT_CARD_INT;
494 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
495 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
498 * Delay is required for PSTATE to correctly reflect
499 * DLEV/CLEV values after PADEN is set.
501 usleep_range(50, 100);
502 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
503 if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
506 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
507 reg &= ~(CON_CLKEXTFREE | CON_PADEN);
508 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
510 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
511 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
512 enable_irq(host->irq);
517 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
523 struct sdhci_host *host = mmc_priv(mmc);
524 struct sdhci_pltfm_host *pltfm_host;
525 struct sdhci_omap_host *omap_host;
528 pltfm_host = sdhci_priv(host);
529 omap_host = sdhci_pltfm_priv(pltfm_host);
530 dev = omap_host->dev;
532 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
533 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
534 if (!(reg & CAPA_VS33))
537 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
539 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
540 reg &= ~AC12_V1V8_SIGEN;
541 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
544 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
545 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
546 if (!(reg & CAPA_VS18))
549 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
551 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
552 reg |= AC12_V1V8_SIGEN;
553 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
560 ret = sdhci_omap_enable_iov(omap_host, iov);
562 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
566 dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
570 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
573 struct pinctrl_state *pinctrl_state;
574 struct device *dev = omap_host->dev;
576 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
579 if (omap_host->timing == timing)
582 sdhci_omap_stop_clock(omap_host);
584 pinctrl_state = omap_host->pinctrl_state[timing];
585 ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
587 dev_err(dev, "failed to select pinctrl state\n");
591 sdhci_omap_start_clock(omap_host);
592 omap_host->timing = timing;
595 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
598 if (omap_host->bus_mode == MMC_POWER_OFF)
599 sdhci_omap_disable_tuning(omap_host);
600 omap_host->power_mode = power_mode;
603 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
608 if (omap_host->bus_mode == mode)
611 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
612 if (mode == MMC_BUSMODE_OPENDRAIN)
616 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
618 omap_host->bus_mode = mode;
621 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
623 struct sdhci_host *host = mmc_priv(mmc);
624 struct sdhci_pltfm_host *pltfm_host;
625 struct sdhci_omap_host *omap_host;
627 pltfm_host = sdhci_priv(host);
628 omap_host = sdhci_pltfm_priv(pltfm_host);
630 sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
631 sdhci_omap_set_timing(omap_host, ios->timing);
632 sdhci_set_ios(mmc, ios);
633 sdhci_omap_set_power_mode(omap_host, ios->power_mode);
636 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
641 dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
642 if (dsor > SYSCTL_CLKD_MAX)
643 dsor = SYSCTL_CLKD_MAX;
648 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
652 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
654 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
657 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
661 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
663 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
666 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
668 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
669 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
670 unsigned long clkdiv;
672 sdhci_omap_stop_clock(omap_host);
677 clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
678 clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
679 sdhci_enable_clk(host, clkdiv);
681 sdhci_omap_start_clock(omap_host);
684 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
687 struct mmc_host *mmc = host->mmc;
689 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
692 static int sdhci_omap_enable_dma(struct sdhci_host *host)
695 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
696 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
698 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
699 reg |= CON_DMA_MASTER;
700 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
705 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
707 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
709 return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
712 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
714 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
715 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
718 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
719 if (width == MMC_BUS_WIDTH_8)
723 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
725 sdhci_set_bus_width(host, width);
728 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
732 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
733 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
735 if (omap_host->power_mode == power_mode)
738 if (power_mode != MMC_POWER_ON)
741 disable_irq(host->irq);
743 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
745 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
746 sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
749 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
751 bool timedout = ktime_after(ktime_get(), timeout);
753 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
755 if (WARN_ON(timedout))
760 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
762 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
763 sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
765 enable_irq(host->irq);
768 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
772 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
773 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
775 sdhci_omap_stop_clock(omap_host);
777 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
778 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
782 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
784 sdhci_set_uhs_signaling(host, timing);
785 sdhci_omap_start_clock(omap_host);
788 void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
790 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
791 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
793 /* Don't reset data lines during tuning operation */
794 if (omap_host->is_tuning)
795 mask &= ~SDHCI_RESET_DATA;
797 sdhci_reset(host, mask);
800 #define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\
802 #define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE)
804 static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask)
806 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
807 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
809 if (omap_host->is_tuning && host->cmd && !host->data_early &&
810 (intmask & CMD_ERR_MASK)) {
813 * Since we are not resetting data lines during tuning
814 * operation, data error or data complete interrupts
815 * might still arrive. Mark this request as a failure
816 * but still wait for the data interrupt
818 if (intmask & SDHCI_INT_TIMEOUT)
819 host->cmd->error = -ETIMEDOUT;
821 host->cmd->error = -EILSEQ;
826 * Sometimes command error interrupts and command complete
827 * interrupt will arrive together. Clear all command related
830 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS);
831 intmask &= ~CMD_MASK;
837 static struct sdhci_ops sdhci_omap_ops = {
838 .set_clock = sdhci_omap_set_clock,
839 .set_power = sdhci_omap_set_power,
840 .enable_dma = sdhci_omap_enable_dma,
841 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
842 .get_min_clock = sdhci_omap_get_min_clock,
843 .set_bus_width = sdhci_omap_set_bus_width,
844 .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
845 .reset = sdhci_omap_reset,
846 .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
847 .irq = sdhci_omap_irq,
850 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
854 struct device *dev = omap_host->dev;
855 struct regulator *vqmmc;
857 vqmmc = regulator_get(dev, "vqmmc");
859 ret = PTR_ERR(vqmmc);
863 /* voltage capabilities might be set by boot loader, clear it */
864 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
865 reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
867 if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
869 if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
872 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
875 regulator_put(vqmmc);
880 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
881 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
882 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
883 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
884 SDHCI_QUIRK_NO_HISPD_BIT |
885 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
886 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
887 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
888 SDHCI_QUIRK2_RSP_136_HAS_CRC |
889 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
890 .ops = &sdhci_omap_ops,
893 static const struct sdhci_omap_data k2g_data = {
897 static const struct sdhci_omap_data dra7_data = {
899 .flags = SDHCI_OMAP_REQUIRE_IODELAY,
902 static const struct of_device_id omap_sdhci_match[] = {
903 { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
904 { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
907 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
909 static struct pinctrl_state
910 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
911 u32 *caps, u32 capmask)
913 struct device *dev = omap_host->dev;
914 char *version = omap_host->version;
915 struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
918 if (!(*caps & capmask))
922 snprintf(str, 20, "%s-%s", mode, version);
923 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
926 if (IS_ERR(pinctrl_state))
927 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
929 if (IS_ERR(pinctrl_state)) {
930 dev_err(dev, "no pinctrl state for %s mode", mode);
935 return pinctrl_state;
938 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
941 struct device *dev = omap_host->dev;
942 struct sdhci_host *host = omap_host->host;
943 struct mmc_host *mmc = host->mmc;
944 u32 *caps = &mmc->caps;
945 u32 *caps2 = &mmc->caps2;
946 struct pinctrl_state *state;
947 struct pinctrl_state **pinctrl_state;
949 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
952 pinctrl_state = devm_kcalloc(dev,
953 MMC_TIMING_MMC_HS200 + 1,
954 sizeof(*pinctrl_state),
959 omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
960 if (IS_ERR(omap_host->pinctrl)) {
961 dev_err(dev, "Cannot get pinctrl\n");
962 return PTR_ERR(omap_host->pinctrl);
965 state = pinctrl_lookup_state(omap_host->pinctrl, "default");
967 dev_err(dev, "no pinctrl state for default mode\n");
968 return PTR_ERR(state);
970 pinctrl_state[MMC_TIMING_LEGACY] = state;
972 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
975 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
977 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
980 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
982 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
985 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
987 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
990 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
992 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
995 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
997 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
999 if (!IS_ERR(state)) {
1000 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1002 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1006 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1009 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1010 MMC_CAP_SD_HIGHSPEED);
1012 pinctrl_state[MMC_TIMING_SD_HS] = state;
1014 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1015 MMC_CAP_MMC_HIGHSPEED);
1017 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1019 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1020 MMC_CAP2_HS200_1_8V_SDR);
1022 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
1024 omap_host->pinctrl_state = pinctrl_state;
1029 static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
1031 .machine = "DRA7[45]*",
1032 .revision = "ES1.[01]",
1039 static int sdhci_omap_probe(struct platform_device *pdev)
1043 struct device *dev = &pdev->dev;
1044 struct sdhci_host *host;
1045 struct sdhci_pltfm_host *pltfm_host;
1046 struct sdhci_omap_host *omap_host;
1047 struct mmc_host *mmc;
1048 const struct of_device_id *match;
1049 struct sdhci_omap_data *data;
1050 const struct soc_device_attribute *soc;
1052 match = of_match_device(omap_sdhci_match, dev);
1056 data = (struct sdhci_omap_data *)match->data;
1058 dev_err(dev, "no sdhci omap data\n");
1061 offset = data->offset;
1063 host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1064 sizeof(*omap_host));
1066 dev_err(dev, "Failed sdhci_pltfm_init\n");
1067 return PTR_ERR(host);
1070 pltfm_host = sdhci_priv(host);
1071 omap_host = sdhci_pltfm_priv(pltfm_host);
1072 omap_host->host = host;
1073 omap_host->base = host->ioaddr;
1074 omap_host->dev = dev;
1075 omap_host->power_mode = MMC_POWER_UNDEFINED;
1076 omap_host->timing = MMC_TIMING_LEGACY;
1077 omap_host->flags = data->flags;
1078 host->ioaddr += offset;
1081 sdhci_get_of_property(pdev);
1082 ret = mmc_of_parse(mmc);
1084 goto err_pltfm_free;
1086 soc = soc_device_match(sdhci_omap_soc_devices);
1088 omap_host->version = "rev11";
1089 if (!strcmp(dev_name(dev), "4809c000.mmc"))
1090 mmc->f_max = 96000000;
1091 if (!strcmp(dev_name(dev), "480b4000.mmc"))
1092 mmc->f_max = 48000000;
1093 if (!strcmp(dev_name(dev), "480ad000.mmc"))
1094 mmc->f_max = 48000000;
1097 if (!mmc_can_gpio_ro(mmc))
1098 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1100 pltfm_host->clk = devm_clk_get(dev, "fck");
1101 if (IS_ERR(pltfm_host->clk)) {
1102 ret = PTR_ERR(pltfm_host->clk);
1103 goto err_pltfm_free;
1106 ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1108 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1109 goto err_pltfm_free;
1112 omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1113 if (IS_ERR(omap_host->pbias)) {
1114 ret = PTR_ERR(omap_host->pbias);
1116 goto err_pltfm_free;
1117 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1119 omap_host->pbias_enabled = false;
1122 * omap_device_pm_domain has callbacks to enable the main
1123 * functional clock, interface clock and also configure the
1124 * SYSCONFIG register of omap devices. The callback will be invoked
1125 * as part of pm_runtime_get_sync.
1127 pm_runtime_enable(dev);
1128 ret = pm_runtime_get_sync(dev);
1130 dev_err(dev, "pm_runtime_get_sync failed\n");
1131 pm_runtime_put_noidle(dev);
1132 goto err_rpm_disable;
1135 ret = sdhci_omap_set_capabilities(omap_host);
1137 dev_err(dev, "failed to set system capabilities\n");
1141 host->mmc_host_ops.start_signal_voltage_switch =
1142 sdhci_omap_start_signal_voltage_switch;
1143 host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
1144 host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
1145 host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
1146 host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
1148 ret = sdhci_setup_host(host);
1152 ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1154 goto err_cleanup_host;
1156 ret = __sdhci_add_host(host);
1158 goto err_cleanup_host;
1163 sdhci_cleanup_host(host);
1166 pm_runtime_put_sync(dev);
1169 pm_runtime_disable(dev);
1172 sdhci_pltfm_free(pdev);
1176 static int sdhci_omap_remove(struct platform_device *pdev)
1178 struct device *dev = &pdev->dev;
1179 struct sdhci_host *host = platform_get_drvdata(pdev);
1181 sdhci_remove_host(host, true);
1182 pm_runtime_put_sync(dev);
1183 pm_runtime_disable(dev);
1184 sdhci_pltfm_free(pdev);
1189 static struct platform_driver sdhci_omap_driver = {
1190 .probe = sdhci_omap_probe,
1191 .remove = sdhci_omap_remove,
1193 .name = "sdhci-omap",
1194 .of_match_table = omap_sdhci_match,
1198 module_platform_driver(sdhci_omap_driver);
1200 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1201 MODULE_AUTHOR("Texas Instruments Inc.");
1202 MODULE_LICENSE("GPL v2");
1203 MODULE_ALIAS("platform:sdhci_omap");