2 * SDHCI Controller driver for TI's OMAP SoCs
4 * Copyright (C) 2017 Texas Instruments
5 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/delay.h>
21 #include <linux/mmc/slot-gpio.h>
22 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/sys_soc.h>
31 #include "sdhci-pltfm.h"
33 #define SDHCI_OMAP_CON 0x12c
34 #define CON_DW8 BIT(5)
35 #define CON_DMA_MASTER BIT(20)
36 #define CON_DDR BIT(19)
37 #define CON_CLKEXTFREE BIT(16)
38 #define CON_PADEN BIT(15)
39 #define CON_CTPL BIT(11)
40 #define CON_INIT BIT(1)
43 #define SDHCI_OMAP_DLL 0x0134
44 #define DLL_SWT BIT(20)
45 #define DLL_FORCE_SR_C_SHIFT 13
46 #define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
47 #define DLL_FORCE_VALUE BIT(12)
48 #define DLL_CALIB BIT(1)
50 #define SDHCI_OMAP_CMD 0x20c
52 #define SDHCI_OMAP_PSTATE 0x0224
53 #define PSTATE_DLEV_DAT0 BIT(20)
54 #define PSTATE_DATI BIT(1)
56 #define SDHCI_OMAP_HCTL 0x228
57 #define HCTL_SDBP BIT(8)
58 #define HCTL_SDVS_SHIFT 9
59 #define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT)
60 #define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT)
61 #define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT)
62 #define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT)
64 #define SDHCI_OMAP_SYSCTL 0x22c
65 #define SYSCTL_CEN BIT(2)
66 #define SYSCTL_CLKD_SHIFT 6
67 #define SYSCTL_CLKD_MASK 0x3ff
69 #define SDHCI_OMAP_STAT 0x230
71 #define SDHCI_OMAP_IE 0x234
72 #define INT_CC_EN BIT(0)
74 #define SDHCI_OMAP_AC12 0x23c
75 #define AC12_V1V8_SIGEN BIT(19)
76 #define AC12_SCLK_SEL BIT(23)
78 #define SDHCI_OMAP_CAPA 0x240
79 #define CAPA_VS33 BIT(24)
80 #define CAPA_VS30 BIT(25)
81 #define CAPA_VS18 BIT(26)
83 #define SDHCI_OMAP_CAPA2 0x0244
84 #define CAPA2_TSDR50 BIT(13)
86 #define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
88 #define SYSCTL_CLKD_MAX 0x3FF
90 #define IOV_1V8 1800000 /* 180000 uV */
91 #define IOV_3V0 3000000 /* 300000 uV */
92 #define IOV_3V3 3300000 /* 330000 uV */
94 #define MAX_PHASE_DELAY 0x7C
96 /* sdhci-omap controller flags */
97 #define SDHCI_OMAP_REQUIRE_IODELAY BIT(0)
99 struct sdhci_omap_data {
104 struct sdhci_omap_host {
108 struct regulator *pbias;
110 struct sdhci_host *host;
116 struct pinctrl *pinctrl;
117 struct pinctrl_state **pinctrl_state;
120 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
121 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
123 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
126 return readl(host->base + offset);
129 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
130 unsigned int offset, u32 data)
132 writel(data, host->base + offset);
135 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
136 bool power_on, unsigned int iov)
139 struct device *dev = omap_host->dev;
141 if (IS_ERR(omap_host->pbias))
145 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
147 dev_err(dev, "pbias set voltage failed\n");
151 if (omap_host->pbias_enabled)
154 ret = regulator_enable(omap_host->pbias);
156 dev_err(dev, "pbias reg enable fail\n");
160 omap_host->pbias_enabled = true;
162 if (!omap_host->pbias_enabled)
165 ret = regulator_disable(omap_host->pbias);
167 dev_err(dev, "pbias reg disable fail\n");
170 omap_host->pbias_enabled = false;
176 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
180 struct sdhci_host *host = omap_host->host;
181 struct mmc_host *mmc = host->mmc;
183 ret = sdhci_omap_set_pbias(omap_host, false, 0);
187 if (!IS_ERR(mmc->supply.vqmmc)) {
188 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
190 dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
195 ret = sdhci_omap_set_pbias(omap_host, true, iov);
202 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
203 unsigned char signal_voltage)
208 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
209 reg &= ~HCTL_SDVS_MASK;
211 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
216 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
219 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
222 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
223 while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)) {
224 if (WARN_ON(ktime_after(ktime_get(), timeout)))
230 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
232 struct sdhci_host *host = mmc_priv(mmc);
233 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
234 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
237 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
239 reg |= (CON_CTPL | CON_CLKEXTFREE);
241 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
242 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
244 sdhci_enable_sdio_irq(mmc, enable);
247 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
253 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
254 reg |= DLL_FORCE_VALUE;
255 reg &= ~DLL_FORCE_SR_C_MASK;
256 reg |= (count << DLL_FORCE_SR_C_SHIFT);
257 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
260 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
261 for (i = 0; i < 1000; i++) {
262 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
267 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
270 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
274 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
275 reg &= ~AC12_SCLK_SEL;
276 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
278 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
279 reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
280 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
283 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
285 struct sdhci_host *host = mmc_priv(mmc);
286 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
287 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
288 struct device *dev = omap_host->dev;
289 struct mmc_ios *ios = &mmc->ios;
290 u32 start_window = 0, max_window = 0;
291 u8 cur_match, prev_match = 0;
292 u32 length = 0, max_len = 0;
298 pltfm_host = sdhci_priv(host);
299 omap_host = sdhci_pltfm_priv(pltfm_host);
300 dev = omap_host->dev;
302 /* clock tuning is not needed for upto 52MHz */
303 if (ios->clock <= 52000000)
306 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
307 if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
310 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
312 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
315 * OMAP5/DRA74X/DRA72x Errata i802:
316 * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
317 * during the tuning procedure. So disable it during the
320 ier &= ~SDHCI_INT_DATA_CRC;
321 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
322 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
324 while (phase_delay <= MAX_PHASE_DELAY) {
325 sdhci_omap_set_dll(omap_host, phase_delay);
327 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
332 start_window = phase_delay;
337 if (length > max_len) {
338 max_window = start_window;
342 prev_match = cur_match;
347 dev_err(dev, "Unable to find match\n");
352 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
353 if (!(reg & AC12_SCLK_SEL)) {
358 phase_delay = max_window + 4 * (max_len >> 1);
359 sdhci_omap_set_dll(omap_host, phase_delay);
364 dev_err(dev, "Tuning failed\n");
365 sdhci_omap_disable_tuning(omap_host);
368 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
369 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
370 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
374 static int sdhci_omap_card_busy(struct mmc_host *mmc)
378 struct sdhci_host *host = mmc_priv(mmc);
379 struct sdhci_pltfm_host *pltfm_host;
380 struct sdhci_omap_host *omap_host;
383 pltfm_host = sdhci_priv(host);
384 omap_host = sdhci_pltfm_priv(pltfm_host);
386 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
387 ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
388 reg &= ~CON_CLKEXTFREE;
389 if (ac12 & AC12_V1V8_SIGEN)
390 reg |= CON_CLKEXTFREE;
392 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
394 disable_irq(host->irq);
395 ier |= SDHCI_INT_CARD_INT;
396 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
397 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
400 * Delay is required for PSTATE to correctly reflect
401 * DLEV/CLEV values after PADEN is set.
403 usleep_range(50, 100);
404 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
405 if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
408 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
409 reg &= ~(CON_CLKEXTFREE | CON_PADEN);
410 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
412 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
413 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
414 enable_irq(host->irq);
419 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
425 struct sdhci_host *host = mmc_priv(mmc);
426 struct sdhci_pltfm_host *pltfm_host;
427 struct sdhci_omap_host *omap_host;
430 pltfm_host = sdhci_priv(host);
431 omap_host = sdhci_pltfm_priv(pltfm_host);
432 dev = omap_host->dev;
434 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
435 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
436 if (!(reg & CAPA_VS33))
439 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
441 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
442 reg &= ~AC12_V1V8_SIGEN;
443 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
446 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
447 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
448 if (!(reg & CAPA_VS18))
451 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
453 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
454 reg |= AC12_V1V8_SIGEN;
455 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
462 ret = sdhci_omap_enable_iov(omap_host, iov);
464 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
468 dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
472 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
475 struct pinctrl_state *pinctrl_state;
476 struct device *dev = omap_host->dev;
478 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
481 if (omap_host->timing == timing)
484 sdhci_omap_stop_clock(omap_host);
486 pinctrl_state = omap_host->pinctrl_state[timing];
487 ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
489 dev_err(dev, "failed to select pinctrl state\n");
493 sdhci_omap_start_clock(omap_host);
494 omap_host->timing = timing;
497 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
500 if (omap_host->bus_mode == MMC_POWER_OFF)
501 sdhci_omap_disable_tuning(omap_host);
502 omap_host->power_mode = power_mode;
505 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
510 if (omap_host->bus_mode == mode)
513 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
514 if (mode == MMC_BUSMODE_OPENDRAIN)
518 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
520 omap_host->bus_mode = mode;
523 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
525 struct sdhci_host *host = mmc_priv(mmc);
526 struct sdhci_pltfm_host *pltfm_host;
527 struct sdhci_omap_host *omap_host;
529 pltfm_host = sdhci_priv(host);
530 omap_host = sdhci_pltfm_priv(pltfm_host);
532 sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
533 sdhci_omap_set_timing(omap_host, ios->timing);
534 sdhci_set_ios(mmc, ios);
535 sdhci_omap_set_power_mode(omap_host, ios->power_mode);
538 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
543 dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
544 if (dsor > SYSCTL_CLKD_MAX)
545 dsor = SYSCTL_CLKD_MAX;
550 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
554 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
556 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
559 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
563 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
565 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
568 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
570 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
571 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
572 unsigned long clkdiv;
574 sdhci_omap_stop_clock(omap_host);
579 clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
580 clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
581 sdhci_enable_clk(host, clkdiv);
583 sdhci_omap_start_clock(omap_host);
586 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
589 struct mmc_host *mmc = host->mmc;
591 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
594 static int sdhci_omap_enable_dma(struct sdhci_host *host)
597 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
598 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
600 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
601 reg |= CON_DMA_MASTER;
602 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
607 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
609 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
611 return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
614 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
616 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
617 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
620 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
621 if (width == MMC_BUS_WIDTH_8)
625 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
627 sdhci_set_bus_width(host, width);
630 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
634 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
635 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
637 if (omap_host->power_mode == power_mode)
640 if (power_mode != MMC_POWER_ON)
643 disable_irq(host->irq);
645 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
647 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
648 sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
651 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
652 while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)) {
653 if (WARN_ON(ktime_after(ktime_get(), timeout)))
658 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
660 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
661 sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
663 enable_irq(host->irq);
666 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
670 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
671 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
673 sdhci_omap_stop_clock(omap_host);
675 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
676 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
680 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
682 sdhci_set_uhs_signaling(host, timing);
683 sdhci_omap_start_clock(omap_host);
686 static struct sdhci_ops sdhci_omap_ops = {
687 .set_clock = sdhci_omap_set_clock,
688 .set_power = sdhci_omap_set_power,
689 .enable_dma = sdhci_omap_enable_dma,
690 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
691 .get_min_clock = sdhci_omap_get_min_clock,
692 .set_bus_width = sdhci_omap_set_bus_width,
693 .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
694 .reset = sdhci_reset,
695 .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
698 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
702 struct device *dev = omap_host->dev;
703 struct regulator *vqmmc;
705 vqmmc = regulator_get(dev, "vqmmc");
707 ret = PTR_ERR(vqmmc);
711 /* voltage capabilities might be set by boot loader, clear it */
712 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
713 reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
715 if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
717 if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
720 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
723 regulator_put(vqmmc);
728 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
729 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
730 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
731 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
732 SDHCI_QUIRK_NO_HISPD_BIT |
733 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
734 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
735 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
736 SDHCI_QUIRK2_RSP_136_HAS_CRC |
737 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
738 .ops = &sdhci_omap_ops,
741 static const struct sdhci_omap_data k2g_data = {
745 static const struct sdhci_omap_data dra7_data = {
747 .flags = SDHCI_OMAP_REQUIRE_IODELAY,
750 static const struct of_device_id omap_sdhci_match[] = {
751 { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
752 { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
755 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
757 static struct pinctrl_state
758 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
759 u32 *caps, u32 capmask)
761 struct device *dev = omap_host->dev;
762 char *version = omap_host->version;
763 struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
766 if (!(*caps & capmask))
770 snprintf(str, 20, "%s-%s", mode, version);
771 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
774 if (IS_ERR(pinctrl_state))
775 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
777 if (IS_ERR(pinctrl_state)) {
778 dev_err(dev, "no pinctrl state for %s mode", mode);
783 return pinctrl_state;
786 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
789 struct device *dev = omap_host->dev;
790 struct sdhci_host *host = omap_host->host;
791 struct mmc_host *mmc = host->mmc;
792 u32 *caps = &mmc->caps;
793 u32 *caps2 = &mmc->caps2;
794 struct pinctrl_state *state;
795 struct pinctrl_state **pinctrl_state;
797 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
800 pinctrl_state = devm_kcalloc(dev,
801 MMC_TIMING_MMC_HS200 + 1,
802 sizeof(*pinctrl_state),
807 omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
808 if (IS_ERR(omap_host->pinctrl)) {
809 dev_err(dev, "Cannot get pinctrl\n");
810 return PTR_ERR(omap_host->pinctrl);
813 state = pinctrl_lookup_state(omap_host->pinctrl, "default");
815 dev_err(dev, "no pinctrl state for default mode\n");
816 return PTR_ERR(state);
818 pinctrl_state[MMC_TIMING_LEGACY] = state;
820 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
823 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
825 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
828 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
830 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
833 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
835 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
838 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
840 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
843 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
845 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
847 if (!IS_ERR(state)) {
848 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
850 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
854 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
857 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
858 MMC_CAP_SD_HIGHSPEED);
860 pinctrl_state[MMC_TIMING_SD_HS] = state;
862 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
863 MMC_CAP_MMC_HIGHSPEED);
865 pinctrl_state[MMC_TIMING_MMC_HS] = state;
867 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
868 MMC_CAP2_HS200_1_8V_SDR);
870 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
872 omap_host->pinctrl_state = pinctrl_state;
877 static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
879 .machine = "DRA7[45]*",
880 .revision = "ES1.[01]",
887 static int sdhci_omap_probe(struct platform_device *pdev)
891 struct device *dev = &pdev->dev;
892 struct sdhci_host *host;
893 struct sdhci_pltfm_host *pltfm_host;
894 struct sdhci_omap_host *omap_host;
895 struct mmc_host *mmc;
896 const struct of_device_id *match;
897 struct sdhci_omap_data *data;
898 const struct soc_device_attribute *soc;
900 match = of_match_device(omap_sdhci_match, dev);
904 data = (struct sdhci_omap_data *)match->data;
906 dev_err(dev, "no sdhci omap data\n");
909 offset = data->offset;
911 host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
914 dev_err(dev, "Failed sdhci_pltfm_init\n");
915 return PTR_ERR(host);
918 pltfm_host = sdhci_priv(host);
919 omap_host = sdhci_pltfm_priv(pltfm_host);
920 omap_host->host = host;
921 omap_host->base = host->ioaddr;
922 omap_host->dev = dev;
923 omap_host->power_mode = MMC_POWER_UNDEFINED;
924 omap_host->timing = MMC_TIMING_LEGACY;
925 omap_host->flags = data->flags;
926 host->ioaddr += offset;
929 sdhci_get_of_property(pdev);
930 ret = mmc_of_parse(mmc);
934 soc = soc_device_match(sdhci_omap_soc_devices);
936 omap_host->version = "rev11";
937 if (!strcmp(dev_name(dev), "4809c000.mmc"))
938 mmc->f_max = 96000000;
939 if (!strcmp(dev_name(dev), "480b4000.mmc"))
940 mmc->f_max = 48000000;
941 if (!strcmp(dev_name(dev), "480ad000.mmc"))
942 mmc->f_max = 48000000;
945 pltfm_host->clk = devm_clk_get(dev, "fck");
946 if (IS_ERR(pltfm_host->clk)) {
947 ret = PTR_ERR(pltfm_host->clk);
951 ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
953 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
957 omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
958 if (IS_ERR(omap_host->pbias)) {
959 ret = PTR_ERR(omap_host->pbias);
962 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
964 omap_host->pbias_enabled = false;
967 * omap_device_pm_domain has callbacks to enable the main
968 * functional clock, interface clock and also configure the
969 * SYSCONFIG register of omap devices. The callback will be invoked
970 * as part of pm_runtime_get_sync.
972 pm_runtime_enable(dev);
973 ret = pm_runtime_get_sync(dev);
975 dev_err(dev, "pm_runtime_get_sync failed\n");
976 pm_runtime_put_noidle(dev);
977 goto err_rpm_disable;
980 ret = sdhci_omap_set_capabilities(omap_host);
982 dev_err(dev, "failed to set system capabilities\n");
986 host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
987 host->mmc_host_ops.start_signal_voltage_switch =
988 sdhci_omap_start_signal_voltage_switch;
989 host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
990 host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
991 host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
992 host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
994 ret = sdhci_setup_host(host);
998 ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1000 goto err_cleanup_host;
1002 ret = __sdhci_add_host(host);
1004 goto err_cleanup_host;
1009 sdhci_cleanup_host(host);
1012 pm_runtime_put_sync(dev);
1015 pm_runtime_disable(dev);
1018 sdhci_pltfm_free(pdev);
1022 static int sdhci_omap_remove(struct platform_device *pdev)
1024 struct device *dev = &pdev->dev;
1025 struct sdhci_host *host = platform_get_drvdata(pdev);
1027 sdhci_remove_host(host, true);
1028 pm_runtime_put_sync(dev);
1029 pm_runtime_disable(dev);
1030 sdhci_pltfm_free(pdev);
1035 static struct platform_driver sdhci_omap_driver = {
1036 .probe = sdhci_omap_probe,
1037 .remove = sdhci_omap_remove,
1039 .name = "sdhci-omap",
1040 .of_match_table = omap_sdhci_match,
1044 module_platform_driver(sdhci_omap_driver);
1046 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1047 MODULE_AUTHOR("Texas Instruments Inc.");
1048 MODULE_LICENSE("GPL v2");
1049 MODULE_ALIAS("platform:sdhci_omap");