drivers/mmc/host/sdhci-of-at91.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Atmel SDMMC controller driver.
   4  *
   5  * Copyright (C) 2015 Atmel,
   6  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
   7  */
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/mmc/slot-gpio.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/pm.h>
  21 #include <linux/pm_runtime.h>
  22
  23 #include "sdhci-pltfm.h"
  24
  25 #define SDMMC_MC1R      0x204
  26 #define         SDMMC_MC1R_DDR          BIT(3)
  27 #define         SDMMC_MC1R_FCD          BIT(7)
  28 #define SDMMC_CACR      0x230
  29 #define         SDMMC_CACR_CAPWREN      BIT(0)
  30 #define         SDMMC_CACR_KEY          (0x46 << 8)
  31 #define SDMMC_CALCR     0x240
  32 #define         SDMMC_CALCR_EN          BIT(0)
  33 #define         SDMMC_CALCR_ALWYSON     BIT(4)
  34
  35 #define SDHCI_AT91_PRESET_COMMON_CONF   0x400 /* drv type B, programmable clock mode */
  36
  37 struct sdhci_at91_soc_data {
  38         const struct sdhci_pltfm_data *pdata;
  39         bool baseclk_is_generated_internally;
  40         unsigned int divider_for_baseclk;
  41 };
  42
  43 struct sdhci_at91_priv {
  44         const struct sdhci_at91_soc_data *soc_data;
  45         struct clk *hclock;
  46         struct clk *gck;
  47         struct clk *mainck;
  48         bool restore_needed;
  49         bool cal_always_on;
  50 };
  51
  52 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
  53 {
  54         u8 mc1r;
  55
  56         mc1r = readb(host->ioaddr + SDMMC_MC1R);
  57         mc1r |= SDMMC_MC1R_FCD;
  58         writeb(mc1r, host->ioaddr + SDMMC_MC1R);
  59 }
  60
  61 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
  62 {
  63         u16 clk;
  64         unsigned long timeout;
  65
  66         host->mmc->actual_clock = 0;
  67
  68         /*
  69          * There is no requirement to disable the internal clock before
  70          * changing the SD clock configuration. Moreover, disabling the
  71          * internal clock, changing the configuration and re-enabling the
  72          * internal clock causes some bugs. It can prevent to get the internal
  73          * clock stable flag ready and an unexpected switch to the base clock
  74          * when using presets.
  75          */
  76         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  77         clk &= SDHCI_CLOCK_INT_EN;
  78         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  79
  80         if (clock == 0)
  81                 return;
  82
  83         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
  84
  85         clk |= SDHCI_CLOCK_INT_EN;
  86         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  87
  88         /* Wait max 20 ms */
  89         timeout = 20;
  90         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  91                 & SDHCI_CLOCK_INT_STABLE)) {
  92                 if (timeout == 0) {
  93                         pr_err("%s: Internal clock never stabilised.\n",
  94                                mmc_hostname(host->mmc));
  95                         return;
  96                 }
  97                 timeout--;
  98                 mdelay(1);
  99         }
 100
 101         clk |= SDHCI_CLOCK_CARD_EN;
 102         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 103 }
 104
 105 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
 106                                          unsigned int timing)
 107 {
 108         if (timing == MMC_TIMING_MMC_DDR52)
 109                 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
 110         sdhci_set_uhs_signaling(host, timing);
 111 }
 112
 113 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
 114 {
 115         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 116         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 117
 118         sdhci_reset(host, mask);
 119
 120         if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
 121             || mmc_gpio_get_cd(host->mmc) >= 0)
 122                 sdhci_at91_set_force_card_detect(host);
 123
 124         if (priv->cal_always_on && (mask & SDHCI_RESET_ALL))
 125                 sdhci_writel(host, SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN,
 126                              SDMMC_CALCR);
 127 }
 128
 129 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
 130         .set_clock              = sdhci_at91_set_clock,
 131         .set_bus_width          = sdhci_set_bus_width,
 132         .reset                  = sdhci_at91_reset,
 133         .set_uhs_signaling      = sdhci_at91_set_uhs_signaling,
 134         .set_power              = sdhci_set_power_and_bus_voltage,
 135 };
 136
 137 static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = {
 138         .ops = &sdhci_at91_sama5d2_ops,
 139 };
 140
 141 static const struct sdhci_at91_soc_data soc_data_sama5d2 = {
 142         .pdata = &sdhci_sama5d2_pdata,
 143         .baseclk_is_generated_internally = false,
 144 };
 145
 146 static const struct sdhci_at91_soc_data soc_data_sam9x60 = {
 147         .pdata = &sdhci_sama5d2_pdata,
 148         .baseclk_is_generated_internally = true,
 149         .divider_for_baseclk = 2,
 150 };
 151
 152 static const struct of_device_id sdhci_at91_dt_match[] = {
 153         { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
 154         { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 },
 155         {}
 156 };
 157 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
 158
 159 static int sdhci_at91_set_clks_presets(struct device *dev)
 160 {
 161         struct sdhci_host *host = dev_get_drvdata(dev);
 162         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 163         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 164         unsigned int                    caps0, caps1;
 165         unsigned int                    clk_base, clk_mul;
 166         unsigned int                    gck_rate, clk_base_rate;
 167         unsigned int                    preset_div;
 168
 169         clk_prepare_enable(priv->hclock);
 170         caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
 171         caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
 172
 173         gck_rate = clk_get_rate(priv->gck);
 174         if (priv->soc_data->baseclk_is_generated_internally)
 175                 clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk;
 176         else
 177                 clk_base_rate = clk_get_rate(priv->mainck);
 178
 179         clk_base = clk_base_rate / 1000000;
 180         clk_mul = gck_rate / clk_base_rate - 1;
 181
 182         caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK;
 183         caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base);
 184         caps1 &= ~SDHCI_CLOCK_MUL_MASK;
 185         caps1 |= FIELD_PREP(SDHCI_CLOCK_MUL_MASK, clk_mul);
 186         /* Set capabilities in r/w mode. */
 187         writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
 188         writel(caps0, host->ioaddr + SDHCI_CAPABILITIES);
 189         writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
 190         /* Set capabilities in ro mode. */
 191         writel(0, host->ioaddr + SDMMC_CACR);
 192
 193         dev_dbg(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n",
 194                 clk_mul, gck_rate, clk_base_rate);
 195
 196         /*
 197          * We have to set preset values because it depends on the clk_mul
 198          * value. Moreover, SDR104 is supported in a degraded mode since the
 199          * maximum sd clock value is 120 MHz instead of 208 MHz. For that
 200          * reason, we need to use presets to support SDR104.
 201          */
 202         preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1;
 203         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 204                host->ioaddr + SDHCI_PRESET_FOR_SDR12);
 205         preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
 206         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 207                host->ioaddr + SDHCI_PRESET_FOR_SDR25);
 208         preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1;
 209         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 210                host->ioaddr + SDHCI_PRESET_FOR_SDR50);
 211         preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1;
 212         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 213                host->ioaddr + SDHCI_PRESET_FOR_SDR104);
 214         preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
 215         writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
 216                host->ioaddr + SDHCI_PRESET_FOR_DDR50);
 217
 218         clk_prepare_enable(priv->mainck);
 219         clk_prepare_enable(priv->gck);
 220
 221         return 0;
 222 }
 223
 224 #ifdef CONFIG_PM_SLEEP
 225 static int sdhci_at91_suspend(struct device *dev)
 226 {
 227         struct sdhci_host *host = dev_get_drvdata(dev);
 228         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 229         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 230         int ret;
 231
 232         ret = pm_runtime_force_suspend(dev);
 233
 234         priv->restore_needed = true;
 235
 236         return ret;
 237 }
 238 #endif /* CONFIG_PM_SLEEP */
 239
 240 #ifdef CONFIG_PM
 241 static int sdhci_at91_runtime_suspend(struct device *dev)
 242 {
 243         struct sdhci_host *host = dev_get_drvdata(dev);
 244         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 245         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 246         int ret;
 247
 248         ret = sdhci_runtime_suspend_host(host);
 249
 250         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 251                 mmc_retune_needed(host->mmc);
 252
 253         clk_disable_unprepare(priv->gck);
 254         clk_disable_unprepare(priv->hclock);
 255         clk_disable_unprepare(priv->mainck);
 256
 257         return ret;
 258 }
 259
 260 static int sdhci_at91_runtime_resume(struct device *dev)
 261 {
 262         struct sdhci_host *host = dev_get_drvdata(dev);
 263         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 264         struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 265         int ret;
 266
 267         if (priv->restore_needed) {
 268                 ret = sdhci_at91_set_clks_presets(dev);
 269                 if (ret)
 270                         return ret;
 271
 272                 priv->restore_needed = false;
 273                 goto out;
 274         }
 275
 276         ret = clk_prepare_enable(priv->mainck);
 277         if (ret) {
 278                 dev_err(dev, "can't enable mainck\n");
 279                 return ret;
 280         }
 281
 282         ret = clk_prepare_enable(priv->hclock);
 283         if (ret) {
 284                 dev_err(dev, "can't enable hclock\n");
 285                 return ret;
 286         }
 287
 288         ret = clk_prepare_enable(priv->gck);
 289         if (ret) {
 290                 dev_err(dev, "can't enable gck\n");
 291                 return ret;
 292         }
 293
 294 out:
 295         return sdhci_runtime_resume_host(host, 0);
 296 }
 297 #endif /* CONFIG_PM */
 298
 299 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
 300         SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
 301         SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
 302                            sdhci_at91_runtime_resume,
 303                            NULL)
 304 };
 305
 306 static int sdhci_at91_probe(struct platform_device *pdev)
 307 {
 308         const struct of_device_id       *match;
 309         const struct sdhci_at91_soc_data        *soc_data;
 310         struct sdhci_host               *host;
 311         struct sdhci_pltfm_host         *pltfm_host;
 312         struct sdhci_at91_priv          *priv;
 313         int                             ret;
 314
 315         match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
 316         if (!match)
 317                 return -EINVAL;
 318         soc_data = match->data;
 319
 320         host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv));
 321         if (IS_ERR(host))
 322                 return PTR_ERR(host);
 323
 324         pltfm_host = sdhci_priv(host);
 325         priv = sdhci_pltfm_priv(pltfm_host);
 326         priv->soc_data = soc_data;
 327
 328         priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
 329         if (IS_ERR(priv->mainck)) {
 330                 if (soc_data->baseclk_is_generated_internally) {
 331                         priv->mainck = NULL;
 332                 } else {
 333                         dev_err(&pdev->dev, "failed to get baseclk\n");
 334                         ret = PTR_ERR(priv->mainck);
 335                         goto sdhci_pltfm_free;
 336                 }
 337         }
 338
 339         priv->hclock = devm_clk_get(&pdev->dev, "hclock");
 340         if (IS_ERR(priv->hclock)) {
 341                 dev_err(&pdev->dev, "failed to get hclock\n");
 342                 ret = PTR_ERR(priv->hclock);
 343                 goto sdhci_pltfm_free;
 344         }
 345
 346         priv->gck = devm_clk_get(&pdev->dev, "multclk");
 347         if (IS_ERR(priv->gck)) {
 348                 dev_err(&pdev->dev, "failed to get multclk\n");
 349                 ret = PTR_ERR(priv->gck);
 350                 goto sdhci_pltfm_free;
 351         }
 352
 353         ret = sdhci_at91_set_clks_presets(&pdev->dev);
 354         if (ret)
 355                 goto sdhci_pltfm_free;
 356
 357         priv->restore_needed = false;
 358
 359         /*
 360          * if SDCAL pin is wrongly connected, we must enable
 361          * the analog calibration cell permanently.
 362          */
 363         priv->cal_always_on =
 364                 device_property_read_bool(&pdev->dev,
 365                                           "microchip,sdcal-inverted");
 366
 367         ret = mmc_of_parse(host->mmc);
 368         if (ret)
 369                 goto clocks_disable_unprepare;
 370
 371         sdhci_get_of_property(pdev);
 372
 373         pm_runtime_get_noresume(&pdev->dev);
 374         pm_runtime_set_active(&pdev->dev);
 375         pm_runtime_enable(&pdev->dev);
 376         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 377         pm_runtime_use_autosuspend(&pdev->dev);
 378
 379         /* HS200 is broken at this moment */
 380         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
 381
 382         ret = sdhci_add_host(host);
 383         if (ret)
 384                 goto pm_runtime_disable;
 385
 386         /*
 387          * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
 388          * the assumption that all the clocks of the controller are disabled.
 389          * It means we can't get irq from it when it is runtime suspended.
 390          * For that reason, it is not planned to wake-up on a card detect irq
 391          * from the controller.
 392          * If we want to use runtime PM and to be able to wake-up on card
 393          * insertion, we have to use a GPIO for the card detection or we can
 394          * use polling. Be aware that using polling will resume/suspend the
 395          * controller between each attempt.
 396          * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
 397          * to enable polling via device tree with broken-cd property.
 398          */
 399         if (mmc_card_is_removable(host->mmc) &&
 400             mmc_gpio_get_cd(host->mmc) < 0) {
 401                 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
 402                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 403         }
 404
 405         /*
 406          * If the device attached to the MMC bus is not removable, it is safer
 407          * to set the Force Card Detect bit. People often don't connect the
 408          * card detect signal and use this pin for another purpose. If the card
 409          * detect pin is not muxed to SDHCI controller, a default value is
 410          * used. This value can be different from a SoC revision to another
 411          * one. Problems come when this default value is not card present. To
 412          * avoid this case, if the device is non removable then the card
 413          * detection procedure using the SDMCC_CD signal is bypassed.
 414          * This bit is reset when a software reset for all command is performed
 415          * so we need to implement our own reset function to set back this bit.
 416          *
 417          * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
 418          */
 419         if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
 420             || mmc_gpio_get_cd(host->mmc) >= 0)
 421                 sdhci_at91_set_force_card_detect(host);
 422
 423         pm_runtime_put_autosuspend(&pdev->dev);
 424
 425         return 0;
 426
 427 pm_runtime_disable:
 428         pm_runtime_disable(&pdev->dev);
 429         pm_runtime_set_suspended(&pdev->dev);
 430         pm_runtime_put_noidle(&pdev->dev);
 431 clocks_disable_unprepare:
 432         clk_disable_unprepare(priv->gck);
 433         clk_disable_unprepare(priv->mainck);
 434         clk_disable_unprepare(priv->hclock);
 435 sdhci_pltfm_free:
 436         sdhci_pltfm_free(pdev);
 437         return ret;
 438 }
 439
 440 static int sdhci_at91_remove(struct platform_device *pdev)
 441 {
 442         struct sdhci_host       *host = platform_get_drvdata(pdev);
 443         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 444         struct sdhci_at91_priv  *priv = sdhci_pltfm_priv(pltfm_host);
 445         struct clk *gck = priv->gck;
 446         struct clk *hclock = priv->hclock;
 447         struct clk *mainck = priv->mainck;
 448
 449         pm_runtime_get_sync(&pdev->dev);
 450         pm_runtime_disable(&pdev->dev);
 451         pm_runtime_put_noidle(&pdev->dev);
 452
 453         sdhci_pltfm_unregister(pdev);
 454
 455         clk_disable_unprepare(gck);
 456         clk_disable_unprepare(hclock);
 457         clk_disable_unprepare(mainck);
 458
 459         return 0;
 460 }
 461
 462 static struct platform_driver sdhci_at91_driver = {
 463         .driver         = {
 464                 .name   = "sdhci-at91",
 465                 .of_match_table = sdhci_at91_dt_match,
 466                 .pm     = &sdhci_at91_dev_pm_ops,
 467         },
 468         .probe          = sdhci_at91_probe,
 469         .remove         = sdhci_at91_remove,
 470 };
 471
 472 module_platform_driver(sdhci_at91_driver);
 473
 474 MODULE_DESCRIPTION("SDHCI driver for at91");
 475 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
 476 MODULE_LICENSE("GPL v2");