1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Arasan Secure Digital Host Controller Interface.
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
5 * Copyright (c) 2012 Wind River Systems, Inc.
6 * Copyright (C) 2013 Pengutronix e.K.
7 * Copyright (C) 2013 Xilinx Inc.
9 * Based on sdhci-of-esdhc.c
11 * Copyright (c) 2007 Freescale Semiconductor, Inc.
12 * Copyright (c) 2009 MontaVista Software, Inc.
14 * Authors: Xiaobo Xie <X.Xie@freescale.com>
15 * Anton Vorontsov <avorontsov@ru.mvista.com>
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/regmap.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
30 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
32 #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
33 #define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF
35 #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
36 #define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F
38 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
39 #define VENDOR_ENHANCED_STROBE BIT(0)
41 #define PHY_CLK_TOO_SLOW_HZ 400000
43 #define SDHCI_ITAPDLY_CHGWIN 0x200
44 #define SDHCI_ITAPDLY_ENABLE 0x100
45 #define SDHCI_OTAPDLY_ENABLE 0x40
47 /* Default settings for ZynqMP Clock Phases */
48 #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}
49 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
51 #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
52 #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
57 * atomic updates of the register without locking. This macro is used on SoCs
58 * that have that feature.
60 #define HIWORD_UPDATE(val, mask, shift) \
61 ((val) << (shift) | (mask) << ((shift) + 16))
64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
66 * @reg: Offset within the syscon of the register containing this field
67 * @width: Number of bits for this field
68 * @shift: Bit offset within @reg of this field (or -1 if not avail)
70 struct sdhci_arasan_soc_ctl_field {
77 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
79 * @baseclkfreq: Where to find corecfg_baseclkfreq
80 * @clockmultiplier: Where to find corecfg_clockmultiplier
81 * @support64b: Where to find SUPPORT64B bit
82 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
84 * It's up to the licensee of the Arsan IP block to make these available
85 * somewhere if needed. Presumably these will be scattered somewhere that's
86 * accessible via the syscon API.
88 struct sdhci_arasan_soc_ctl_map {
89 struct sdhci_arasan_soc_ctl_field baseclkfreq;
90 struct sdhci_arasan_soc_ctl_field clockmultiplier;
91 struct sdhci_arasan_soc_ctl_field support64b;
96 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
98 * @sdcardclk_ops: The output clock related operations
99 * @sampleclk_ops: The sample clock related operations
101 struct sdhci_arasan_clk_ops {
102 const struct clk_ops *sdcardclk_ops;
103 const struct clk_ops *sampleclk_ops;
107 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
109 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
110 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
111 * @sampleclk_hw: Struct for the clock we might provide to a PHY.
112 * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
113 * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
114 * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
115 * @set_clk_delays: Function pointer for setting Clock Delays
116 * @clk_of_data: Platform specific runtime clock data storage pointer
118 struct sdhci_arasan_clk_data {
119 struct clk_hw sdcardclk_hw;
120 struct clk *sdcardclk;
121 struct clk_hw sampleclk_hw;
122 struct clk *sampleclk;
123 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
124 int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
125 void (*set_clk_delays)(struct sdhci_host *host);
130 * struct sdhci_arasan_data - Arasan Controller Data
132 * @host: Pointer to the main SDHCI host structure.
133 * @clk_ahb: Pointer to the AHB clock
134 * @phy: Pointer to the generic phy
135 * @is_phy_on: True if the PHY is on; false if not.
136 * @has_cqe: True if controller has command queuing engine.
137 * @clk_data: Struct for the Arasan Controller Clock Data.
138 * @clk_ops: Struct for the Arasan Controller Clock Operations.
139 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
140 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
141 * @quirks: Arasan deviations from spec.
143 struct sdhci_arasan_data {
144 struct sdhci_host *host;
150 struct sdhci_arasan_clk_data clk_data;
151 const struct sdhci_arasan_clk_ops *clk_ops;
153 struct regmap *soc_ctl_base;
154 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
157 /* Controller does not have CD wired and will not function normally without */
158 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
159 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
160 * internal clock even when the clock isn't stable */
161 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
164 struct sdhci_arasan_of_data {
165 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
166 const struct sdhci_pltfm_data *pdata;
167 const struct sdhci_arasan_clk_ops *clk_ops;
170 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
171 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
172 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
173 .hiword_update = true,
176 static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
177 .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
178 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
179 .hiword_update = false,
182 static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
183 .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
184 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
185 .hiword_update = false,
188 static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
189 .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
190 .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
191 .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
192 .hiword_update = false,
196 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
198 * @host: The sdhci_host
199 * @fld: The field to write to
200 * @val: The value to write
202 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
203 * Note that if a field is specified as not available (shift < 0) then
204 * this function will silently return an error code. It will be noisy
205 * and print errors for any other (unexpected) errors.
207 * Return: 0 on success and error value on error
209 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
210 const struct sdhci_arasan_soc_ctl_field *fld,
213 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
214 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
215 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
217 u16 width = fld->width;
218 s16 shift = fld->shift;
222 * Silently return errors for shift < 0 so caller doesn't have
223 * to check for fields which are optional. For fields that
224 * are required then caller needs to do something special
230 if (sdhci_arasan->soc_ctl_map->hiword_update)
231 ret = regmap_write(soc_ctl_base, reg,
232 HIWORD_UPDATE(val, GENMASK(width, 0),
235 ret = regmap_update_bits(soc_ctl_base, reg,
236 GENMASK(shift + width, shift),
239 /* Yell about (unexpected) regmap errors */
241 pr_warn("%s: Regmap write fail: %d\n",
242 mmc_hostname(host->mmc), ret);
247 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
249 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
250 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
251 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
252 bool ctrl_phy = false;
254 if (!IS_ERR(sdhci_arasan->phy)) {
255 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
257 * If PHY off, set clock to max speed and power PHY on.
259 * Although PHY docs apparently suggest power cycling
260 * when changing the clock the PHY doesn't like to be
261 * powered on while at low speeds like those used in ID
262 * mode. Even worse is powering the PHY on while the
265 * To workaround the PHY limitations, the best we can
266 * do is to power it on at a faster speed and then slam
267 * through low speeds without power cycling.
269 sdhci_set_clock(host, host->max_clk);
270 phy_power_on(sdhci_arasan->phy);
271 sdhci_arasan->is_phy_on = true;
274 * We'll now fall through to the below case with
275 * ctrl_phy = false (so we won't turn off/on). The
276 * sdhci_set_clock() will set the real clock.
278 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
280 * At higher clock speeds the PHY is fine being power
281 * cycled and docs say you _should_ power cycle when
282 * changing clock speeds.
288 if (ctrl_phy && sdhci_arasan->is_phy_on) {
289 phy_power_off(sdhci_arasan->phy);
290 sdhci_arasan->is_phy_on = false;
293 /* Set the Input and Output Clock Phase Delays */
294 if (clk_data->set_clk_delays)
295 clk_data->set_clk_delays(host);
297 sdhci_set_clock(host, clock);
299 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
301 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
302 * after enabling the clock even though the clock is not
303 * stable. Trying to use a clock without waiting here results
304 * in EILSEQ while detecting some older/slower cards. The
305 * chosen delay is the maximum delay from sdhci_set_clock.
310 phy_power_on(sdhci_arasan->phy);
311 sdhci_arasan->is_phy_on = true;
315 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
319 struct sdhci_host *host = mmc_priv(mmc);
321 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
322 if (ios->enhanced_strobe)
323 vendor |= VENDOR_ENHANCED_STROBE;
325 vendor &= ~VENDOR_ENHANCED_STROBE;
327 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
330 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
333 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
334 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
336 sdhci_reset(host, mask);
338 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
339 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
340 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
341 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
345 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
348 switch (ios->signal_voltage) {
349 case MMC_SIGNAL_VOLTAGE_180:
351 * Plese don't switch to 1V8 as arasan,5.1 doesn't
352 * actually refer to this setting to indicate the
353 * signal voltage and the state machine will be broken
354 * actually if we force to enable 1V8. That's something
355 * like broken quirk but we could work around here.
358 case MMC_SIGNAL_VOLTAGE_330:
359 case MMC_SIGNAL_VOLTAGE_120:
360 /* We don't support 3V3 and 1V2 */
367 static const struct sdhci_ops sdhci_arasan_ops = {
368 .set_clock = sdhci_arasan_set_clock,
369 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
370 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
371 .set_bus_width = sdhci_set_bus_width,
372 .reset = sdhci_arasan_reset,
373 .set_uhs_signaling = sdhci_set_uhs_signaling,
374 .set_power = sdhci_set_power_and_bus_voltage,
377 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
382 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
385 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
390 static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
392 sdhci_dumpregs(mmc_priv(mmc));
395 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
397 struct sdhci_host *host = mmc_priv(mmc);
400 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
401 while (reg & SDHCI_DATA_AVAILABLE) {
402 sdhci_readl(host, SDHCI_BUFFER);
403 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
406 sdhci_cqe_enable(mmc);
409 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
410 .enable = sdhci_arasan_cqe_enable,
411 .disable = sdhci_cqe_disable,
412 .dumpregs = sdhci_arasan_dumpregs,
415 static const struct sdhci_ops sdhci_arasan_cqe_ops = {
416 .set_clock = sdhci_arasan_set_clock,
417 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
418 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
419 .set_bus_width = sdhci_set_bus_width,
420 .reset = sdhci_arasan_reset,
421 .set_uhs_signaling = sdhci_set_uhs_signaling,
422 .set_power = sdhci_set_power_and_bus_voltage,
423 .irq = sdhci_arasan_cqhci_irq,
426 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
427 .ops = &sdhci_arasan_cqe_ops,
428 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
429 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
430 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
433 #ifdef CONFIG_PM_SLEEP
435 * sdhci_arasan_suspend - Suspend method for the driver
436 * @dev: Address of the device structure
438 * Put the device in a low power state.
440 * Return: 0 on success and error value on error
442 static int sdhci_arasan_suspend(struct device *dev)
444 struct sdhci_host *host = dev_get_drvdata(dev);
445 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
446 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
449 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
450 mmc_retune_needed(host->mmc);
452 if (sdhci_arasan->has_cqe) {
453 ret = cqhci_suspend(host->mmc);
458 ret = sdhci_suspend_host(host);
462 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
463 ret = phy_power_off(sdhci_arasan->phy);
465 dev_err(dev, "Cannot power off phy.\n");
466 sdhci_resume_host(host);
469 sdhci_arasan->is_phy_on = false;
472 clk_disable(pltfm_host->clk);
473 clk_disable(sdhci_arasan->clk_ahb);
479 * sdhci_arasan_resume - Resume method for the driver
480 * @dev: Address of the device structure
482 * Resume operation after suspend
484 * Return: 0 on success and error value on error
486 static int sdhci_arasan_resume(struct device *dev)
488 struct sdhci_host *host = dev_get_drvdata(dev);
489 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
490 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
493 ret = clk_enable(sdhci_arasan->clk_ahb);
495 dev_err(dev, "Cannot enable AHB clock.\n");
499 ret = clk_enable(pltfm_host->clk);
501 dev_err(dev, "Cannot enable SD clock.\n");
505 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
506 ret = phy_power_on(sdhci_arasan->phy);
508 dev_err(dev, "Cannot power on phy.\n");
511 sdhci_arasan->is_phy_on = true;
514 ret = sdhci_resume_host(host);
516 dev_err(dev, "Cannot resume host.\n");
520 if (sdhci_arasan->has_cqe)
521 return cqhci_resume(host->mmc);
525 #endif /* ! CONFIG_PM_SLEEP */
527 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
528 sdhci_arasan_resume);
531 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
533 * @hw: Pointer to the hardware clock structure.
534 * @parent_rate: The parent rate (should be rate of clk_xin).
536 * Return the current actual rate of the SD card clock. This can be used
537 * to communicate with out PHY.
539 * Return: The card clock rate.
541 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
542 unsigned long parent_rate)
544 struct sdhci_arasan_clk_data *clk_data =
545 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
546 struct sdhci_arasan_data *sdhci_arasan =
547 container_of(clk_data, struct sdhci_arasan_data, clk_data);
548 struct sdhci_host *host = sdhci_arasan->host;
550 return host->mmc->actual_clock;
553 static const struct clk_ops arasan_sdcardclk_ops = {
554 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
558 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
560 * @hw: Pointer to the hardware clock structure.
561 * @parent_rate: The parent rate (should be rate of clk_xin).
563 * Return the current actual rate of the sampling clock. This can be used
564 * to communicate with out PHY.
566 * Return: The sample clock rate.
568 static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
569 unsigned long parent_rate)
571 struct sdhci_arasan_clk_data *clk_data =
572 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
573 struct sdhci_arasan_data *sdhci_arasan =
574 container_of(clk_data, struct sdhci_arasan_data, clk_data);
575 struct sdhci_host *host = sdhci_arasan->host;
577 return host->mmc->actual_clock;
580 static const struct clk_ops arasan_sampleclk_ops = {
581 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
585 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
587 * @hw: Pointer to the hardware clock structure.
588 * @degrees: The clock phase shift between 0 - 359.
590 * Set the SD Output Clock Tap Delays for Output path
592 * Return: 0 on success and error value on error
594 static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
596 struct sdhci_arasan_clk_data *clk_data =
597 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
598 struct sdhci_arasan_data *sdhci_arasan =
599 container_of(clk_data, struct sdhci_arasan_data, clk_data);
600 struct sdhci_host *host = sdhci_arasan->host;
601 const char *clk_name = clk_hw_get_name(hw);
602 u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
603 u8 tap_delay, tap_max = 0;
606 /* This is applicable for SDHCI_SPEC_300 and above */
607 if (host->version < SDHCI_SPEC_300)
610 switch (host->timing) {
611 case MMC_TIMING_MMC_HS:
612 case MMC_TIMING_SD_HS:
613 case MMC_TIMING_UHS_SDR25:
614 case MMC_TIMING_UHS_DDR50:
615 case MMC_TIMING_MMC_DDR52:
616 /* For 50MHz clock, 30 Taps are available */
619 case MMC_TIMING_UHS_SDR50:
620 /* For 100MHz clock, 15 Taps are available */
623 case MMC_TIMING_UHS_SDR104:
624 case MMC_TIMING_MMC_HS200:
625 /* For 200MHz clock, 8 Taps are available */
632 tap_delay = (degrees * tap_max) / 360;
634 /* Set the Clock Phase */
635 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
637 pr_err("Error setting Output Tap Delay\n");
639 /* Release DLL Reset */
640 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE);
645 static const struct clk_ops zynqmp_sdcardclk_ops = {
646 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
647 .set_phase = sdhci_zynqmp_sdcardclk_set_phase,
651 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
653 * @hw: Pointer to the hardware clock structure.
654 * @degrees: The clock phase shift between 0 - 359.
656 * Set the SD Input Clock Tap Delays for Input path
658 * Return: 0 on success and error value on error
660 static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
662 struct sdhci_arasan_clk_data *clk_data =
663 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
664 struct sdhci_arasan_data *sdhci_arasan =
665 container_of(clk_data, struct sdhci_arasan_data, clk_data);
666 struct sdhci_host *host = sdhci_arasan->host;
667 const char *clk_name = clk_hw_get_name(hw);
668 u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
669 u8 tap_delay, tap_max = 0;
672 /* This is applicable for SDHCI_SPEC_300 and above */
673 if (host->version < SDHCI_SPEC_300)
676 /* Assert DLL Reset */
677 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT);
679 switch (host->timing) {
680 case MMC_TIMING_MMC_HS:
681 case MMC_TIMING_SD_HS:
682 case MMC_TIMING_UHS_SDR25:
683 case MMC_TIMING_UHS_DDR50:
684 case MMC_TIMING_MMC_DDR52:
685 /* For 50MHz clock, 120 Taps are available */
688 case MMC_TIMING_UHS_SDR50:
689 /* For 100MHz clock, 60 Taps are available */
692 case MMC_TIMING_UHS_SDR104:
693 case MMC_TIMING_MMC_HS200:
694 /* For 200MHz clock, 30 Taps are available */
701 tap_delay = (degrees * tap_max) / 360;
703 /* Set the Clock Phase */
704 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
706 pr_err("Error setting Input Tap Delay\n");
711 static const struct clk_ops zynqmp_sampleclk_ops = {
712 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
713 .set_phase = sdhci_zynqmp_sampleclk_set_phase,
717 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
719 * @hw: Pointer to the hardware clock structure.
720 * @degrees: The clock phase shift between 0 - 359.
722 * Set the SD Output Clock Tap Delays for Output path
724 * Return: 0 on success and error value on error
726 static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
728 struct sdhci_arasan_clk_data *clk_data =
729 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
730 struct sdhci_arasan_data *sdhci_arasan =
731 container_of(clk_data, struct sdhci_arasan_data, clk_data);
732 struct sdhci_host *host = sdhci_arasan->host;
733 u8 tap_delay, tap_max = 0;
735 /* This is applicable for SDHCI_SPEC_300 and above */
736 if (host->version < SDHCI_SPEC_300)
739 switch (host->timing) {
740 case MMC_TIMING_MMC_HS:
741 case MMC_TIMING_SD_HS:
742 case MMC_TIMING_UHS_SDR25:
743 case MMC_TIMING_UHS_DDR50:
744 case MMC_TIMING_MMC_DDR52:
745 /* For 50MHz clock, 30 Taps are available */
748 case MMC_TIMING_UHS_SDR50:
749 /* For 100MHz clock, 15 Taps are available */
752 case MMC_TIMING_UHS_SDR104:
753 case MMC_TIMING_MMC_HS200:
754 /* For 200MHz clock, 8 Taps are available */
761 tap_delay = (degrees * tap_max) / 360;
763 /* Set the Clock Phase */
767 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
768 regval |= SDHCI_OTAPDLY_ENABLE;
769 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
770 regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
772 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
778 static const struct clk_ops versal_sdcardclk_ops = {
779 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
780 .set_phase = sdhci_versal_sdcardclk_set_phase,
784 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
786 * @hw: Pointer to the hardware clock structure.
787 * @degrees: The clock phase shift between 0 - 359.
789 * Set the SD Input Clock Tap Delays for Input path
791 * Return: 0 on success and error value on error
793 static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
795 struct sdhci_arasan_clk_data *clk_data =
796 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
797 struct sdhci_arasan_data *sdhci_arasan =
798 container_of(clk_data, struct sdhci_arasan_data, clk_data);
799 struct sdhci_host *host = sdhci_arasan->host;
800 u8 tap_delay, tap_max = 0;
802 /* This is applicable for SDHCI_SPEC_300 and above */
803 if (host->version < SDHCI_SPEC_300)
806 switch (host->timing) {
807 case MMC_TIMING_MMC_HS:
808 case MMC_TIMING_SD_HS:
809 case MMC_TIMING_UHS_SDR25:
810 case MMC_TIMING_UHS_DDR50:
811 case MMC_TIMING_MMC_DDR52:
812 /* For 50MHz clock, 120 Taps are available */
815 case MMC_TIMING_UHS_SDR50:
816 /* For 100MHz clock, 60 Taps are available */
819 case MMC_TIMING_UHS_SDR104:
820 case MMC_TIMING_MMC_HS200:
821 /* For 200MHz clock, 30 Taps are available */
828 tap_delay = (degrees * tap_max) / 360;
830 /* Set the Clock Phase */
834 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
835 regval |= SDHCI_ITAPDLY_CHGWIN;
836 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
837 regval |= SDHCI_ITAPDLY_ENABLE;
838 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
839 regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
841 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
842 regval &= ~SDHCI_ITAPDLY_CHGWIN;
843 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
849 static const struct clk_ops versal_sampleclk_ops = {
850 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
851 .set_phase = sdhci_versal_sampleclk_set_phase,
854 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
858 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
859 clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
860 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
862 /* Issue DLL Reset */
863 zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
865 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
867 sdhci_enable_clk(host, clk);
870 static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
872 struct sdhci_host *host = mmc_priv(mmc);
873 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
874 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
875 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
876 const char *clk_name = clk_hw_get_name(hw);
877 u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
881 arasan_zynqmp_dll_reset(host, device_id);
883 err = sdhci_execute_tuning(mmc, opcode);
887 arasan_zynqmp_dll_reset(host, device_id);
893 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
895 * @host: The sdhci_host
896 * @value: The value to write
898 * The corecfg_clockmultiplier is supposed to contain clock multiplier
899 * value of programmable clock generator.
902 * - Many existing devices don't seem to do this and work fine. To keep
903 * compatibility for old hardware where the device tree doesn't provide a
904 * register map, this function is a noop if a soc_ctl_map hasn't been provided
906 * - The value of corecfg_clockmultiplier should sync with that of corresponding
907 * value reading from sdhci_capability_register. So this function is called
908 * once at probe time and never called again.
910 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
913 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
914 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
915 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
916 sdhci_arasan->soc_ctl_map;
918 /* Having a map is optional */
922 /* If we have a map, we expect to have a syscon */
923 if (!sdhci_arasan->soc_ctl_base) {
924 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
925 mmc_hostname(host->mmc));
929 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
933 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
935 * @host: The sdhci_host
937 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
938 * function can be used to make that happen.
941 * - Many existing devices don't seem to do this and work fine. To keep
942 * compatibility for old hardware where the device tree doesn't provide a
943 * register map, this function is a noop if a soc_ctl_map hasn't been provided
945 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
946 * to achieve lower clock rates. That means that this function is called once
947 * at probe time and never called again.
949 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
951 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
952 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
953 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
954 sdhci_arasan->soc_ctl_map;
955 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
957 /* Having a map is optional */
961 /* If we have a map, we expect to have a syscon */
962 if (!sdhci_arasan->soc_ctl_base) {
963 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
964 mmc_hostname(host->mmc));
968 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
971 static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
973 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
974 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
975 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
977 clk_set_phase(clk_data->sampleclk,
978 clk_data->clk_phase_in[host->timing]);
979 clk_set_phase(clk_data->sdcardclk,
980 clk_data->clk_phase_out[host->timing]);
983 static void arasan_dt_read_clk_phase(struct device *dev,
984 struct sdhci_arasan_clk_data *clk_data,
985 unsigned int timing, const char *prop)
987 struct device_node *np = dev->of_node;
989 int clk_phase[2] = {0};
992 * Read Tap Delay values from DT, if the DT does not contain the
993 * Tap Values then use the pre-defined values.
995 if (of_property_read_variable_u32_array(np, prop, &clk_phase[0],
997 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
998 prop, clk_data->clk_phase_in[timing],
999 clk_data->clk_phase_out[timing]);
1003 /* The values read are Input and Output Clock Delays in order */
1004 clk_data->clk_phase_in[timing] = clk_phase[0];
1005 clk_data->clk_phase_out[timing] = clk_phase[1];
1009 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1011 * @dev: Pointer to our struct device.
1012 * @clk_data: Pointer to the Clock Data structure
1014 * Called at initialization to parse the values of Clock Delays.
1016 static void arasan_dt_parse_clk_phases(struct device *dev,
1017 struct sdhci_arasan_clk_data *clk_data)
1023 * This has been kept as a pointer and is assigned a function here.
1024 * So that different controller variants can assign their own handling
1027 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
1029 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
1030 u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1032 u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1035 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
1036 if (mio_bank == 2) {
1037 zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
1038 zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
1041 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1042 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
1043 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
1047 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
1048 u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1050 u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1053 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1054 clk_data->clk_phase_in[i] = versal_iclk_phase[i];
1055 clk_data->clk_phase_out[i] = versal_oclk_phase[i];
1059 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
1060 "clk-phase-legacy");
1061 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
1062 "clk-phase-mmc-hs");
1063 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
1065 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
1066 "clk-phase-uhs-sdr12");
1067 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
1068 "clk-phase-uhs-sdr25");
1069 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
1070 "clk-phase-uhs-sdr50");
1071 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
1072 "clk-phase-uhs-sdr104");
1073 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
1074 "clk-phase-uhs-ddr50");
1075 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
1076 "clk-phase-mmc-ddr52");
1077 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
1078 "clk-phase-mmc-hs200");
1079 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
1080 "clk-phase-mmc-hs400");
1083 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
1084 .ops = &sdhci_arasan_ops,
1085 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1086 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1087 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1088 SDHCI_QUIRK2_STOP_WITH_TC,
1091 static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
1092 .sdcardclk_ops = &arasan_sdcardclk_ops,
1093 .sampleclk_ops = &arasan_sampleclk_ops,
1096 static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
1097 .pdata = &sdhci_arasan_pdata,
1098 .clk_ops = &arasan_clk_ops,
1101 static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
1102 .ops = &sdhci_arasan_cqe_ops,
1103 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1104 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1105 SDHCI_QUIRK_NO_LED |
1106 SDHCI_QUIRK_32BIT_DMA_ADDR |
1107 SDHCI_QUIRK_32BIT_DMA_SIZE |
1108 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1109 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1110 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1111 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1112 SDHCI_QUIRK2_STOP_WITH_TC |
1113 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1116 static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
1117 .ops = &sdhci_arasan_ops,
1118 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1119 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1120 SDHCI_QUIRK_NO_LED |
1121 SDHCI_QUIRK_32BIT_DMA_ADDR |
1122 SDHCI_QUIRK_32BIT_DMA_SIZE |
1123 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1124 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1125 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1126 SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1127 SDHCI_QUIRK2_STOP_WITH_TC |
1128 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1131 static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
1132 .ops = &sdhci_arasan_ops,
1133 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1134 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1135 SDHCI_QUIRK_NO_LED |
1136 SDHCI_QUIRK_32BIT_DMA_ADDR |
1137 SDHCI_QUIRK_32BIT_DMA_SIZE |
1138 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1139 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1140 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1141 SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1142 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1145 static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
1146 .soc_ctl_map = &rk3399_soc_ctl_map,
1147 .pdata = &sdhci_arasan_cqe_pdata,
1148 .clk_ops = &arasan_clk_ops,
1151 static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
1152 .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
1153 .pdata = &sdhci_arasan_cqe_pdata,
1154 .clk_ops = &arasan_clk_ops,
1157 static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
1158 .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
1159 .pdata = &sdhci_arasan_cqe_pdata,
1160 .clk_ops = &arasan_clk_ops,
1163 static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
1164 .ops = &sdhci_arasan_ops,
1165 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1166 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1167 SDHCI_QUIRK2_STOP_WITH_TC,
1170 static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
1171 .sdcardclk_ops = &zynqmp_sdcardclk_ops,
1172 .sampleclk_ops = &zynqmp_sampleclk_ops,
1175 static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1176 .pdata = &sdhci_arasan_zynqmp_pdata,
1177 .clk_ops = &zynqmp_clk_ops,
1180 static const struct sdhci_arasan_clk_ops versal_clk_ops = {
1181 .sdcardclk_ops = &versal_sdcardclk_ops,
1182 .sampleclk_ops = &versal_sampleclk_ops,
1185 static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1186 .pdata = &sdhci_arasan_zynqmp_pdata,
1187 .clk_ops = &versal_clk_ops,
1190 static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
1191 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1192 .pdata = &sdhci_keembay_emmc_pdata,
1193 .clk_ops = &arasan_clk_ops,
1196 static struct sdhci_arasan_of_data intel_keembay_sd_data = {
1197 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1198 .pdata = &sdhci_keembay_sd_pdata,
1199 .clk_ops = &arasan_clk_ops,
1202 static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
1203 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1204 .pdata = &sdhci_keembay_sdio_pdata,
1205 .clk_ops = &arasan_clk_ops,
1208 static const struct of_device_id sdhci_arasan_of_match[] = {
1209 /* SoC-specific compatible strings w/ soc_ctl_map */
1211 .compatible = "rockchip,rk3399-sdhci-5.1",
1212 .data = &sdhci_arasan_rk3399_data,
1215 .compatible = "intel,lgm-sdhci-5.1-emmc",
1216 .data = &intel_lgm_emmc_data,
1219 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1220 .data = &intel_lgm_sdxc_data,
1223 .compatible = "intel,keembay-sdhci-5.1-emmc",
1224 .data = &intel_keembay_emmc_data,
1227 .compatible = "intel,keembay-sdhci-5.1-sd",
1228 .data = &intel_keembay_sd_data,
1231 .compatible = "intel,keembay-sdhci-5.1-sdio",
1232 .data = &intel_keembay_sdio_data,
1234 /* Generic compatible below here */
1236 .compatible = "arasan,sdhci-8.9a",
1237 .data = &sdhci_arasan_generic_data,
1240 .compatible = "arasan,sdhci-5.1",
1241 .data = &sdhci_arasan_generic_data,
1244 .compatible = "arasan,sdhci-4.9a",
1245 .data = &sdhci_arasan_generic_data,
1248 .compatible = "xlnx,zynqmp-8.9a",
1249 .data = &sdhci_arasan_zynqmp_data,
1252 .compatible = "xlnx,versal-8.9a",
1253 .data = &sdhci_arasan_versal_data,
1257 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
1260 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1262 * @sdhci_arasan: Our private data structure.
1263 * @clk_xin: Pointer to the functional clock
1264 * @dev: Pointer to our struct device.
1266 * Some PHY devices need to know what the actual card clock is. In order for
1267 * them to find out, we'll provide a clock through the common clock framework
1268 * for them to query.
1270 * Return: 0 on success and error value on error
1273 sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
1274 struct clk *clk_xin,
1277 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1278 struct device_node *np = dev->of_node;
1279 struct clk_init_data sdcardclk_init;
1280 const char *parent_clk_name;
1283 ret = of_property_read_string_index(np, "clock-output-names", 0,
1284 &sdcardclk_init.name);
1286 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1290 parent_clk_name = __clk_get_name(clk_xin);
1291 sdcardclk_init.parent_names = &parent_clk_name;
1292 sdcardclk_init.num_parents = 1;
1293 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
1294 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
1296 clk_data->sdcardclk_hw.init = &sdcardclk_init;
1297 clk_data->sdcardclk =
1298 devm_clk_register(dev, &clk_data->sdcardclk_hw);
1299 if (IS_ERR(clk_data->sdcardclk))
1300 return PTR_ERR(clk_data->sdcardclk);
1301 clk_data->sdcardclk_hw.init = NULL;
1303 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1304 clk_data->sdcardclk);
1306 dev_err(dev, "Failed to add sdcard clock provider\n");
1312 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1314 * @sdhci_arasan: Our private data structure.
1315 * @clk_xin: Pointer to the functional clock
1316 * @dev: Pointer to our struct device.
1318 * Some PHY devices need to know what the actual card clock is. In order for
1319 * them to find out, we'll provide a clock through the common clock framework
1320 * for them to query.
1322 * Return: 0 on success and error value on error
1325 sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
1326 struct clk *clk_xin,
1329 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1330 struct device_node *np = dev->of_node;
1331 struct clk_init_data sampleclk_init;
1332 const char *parent_clk_name;
1335 ret = of_property_read_string_index(np, "clock-output-names", 1,
1336 &sampleclk_init.name);
1338 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1342 parent_clk_name = __clk_get_name(clk_xin);
1343 sampleclk_init.parent_names = &parent_clk_name;
1344 sampleclk_init.num_parents = 1;
1345 sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
1346 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
1348 clk_data->sampleclk_hw.init = &sampleclk_init;
1349 clk_data->sampleclk =
1350 devm_clk_register(dev, &clk_data->sampleclk_hw);
1351 if (IS_ERR(clk_data->sampleclk))
1352 return PTR_ERR(clk_data->sampleclk);
1353 clk_data->sampleclk_hw.init = NULL;
1355 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1356 clk_data->sampleclk);
1358 dev_err(dev, "Failed to add sample clock provider\n");
1364 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1366 * @dev: Pointer to our struct device.
1368 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
1371 static void sdhci_arasan_unregister_sdclk(struct device *dev)
1373 struct device_node *np = dev->of_node;
1375 if (!of_find_property(np, "#clock-cells", NULL))
1378 of_clk_del_provider(dev->of_node);
1382 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1383 * @host: The sdhci_host
1384 * @value: The value to write
1386 * This should be set based on the System Address Bus.
1387 * 0: the Core supports only 32-bit System Address Bus.
1388 * 1: the Core supports 64-bit System Address Bus.
1391 * For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1392 * Keem Bay does not support 64-bit access.
1394 static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
1396 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1397 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1398 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
1400 /* Having a map is optional */
1401 soc_ctl_map = sdhci_arasan->soc_ctl_map;
1405 /* If we have a map, we expect to have a syscon */
1406 if (!sdhci_arasan->soc_ctl_base) {
1407 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1408 mmc_hostname(host->mmc));
1412 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
1416 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1418 * @sdhci_arasan: Our private data structure.
1419 * @clk_xin: Pointer to the functional clock
1420 * @dev: Pointer to our struct device.
1422 * Some PHY devices need to know what the actual card clock is. In order for
1423 * them to find out, we'll provide a clock through the common clock framework
1424 * for them to query.
1426 * Note: without seriously re-architecting SDHCI's clock code and testing on
1427 * all platforms, there's no way to create a totally beautiful clock here
1428 * with all clock ops implemented. Instead, we'll just create a clock that can
1429 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1430 * framework that we're doing things behind its back. This should be sufficient
1431 * to create nice clean device tree bindings and later (if needed) we can try
1432 * re-architecting SDHCI if we see some benefit to it.
1434 * Return: 0 on success and error value on error
1436 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
1437 struct clk *clk_xin,
1440 struct device_node *np = dev->of_node;
1444 /* Providing a clock to the PHY is optional; no error if missing */
1445 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1448 ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1453 ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1456 sdhci_arasan_unregister_sdclk(dev);
1464 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
1466 struct sdhci_host *host = sdhci_arasan->host;
1467 struct cqhci_host *cq_host;
1471 if (!sdhci_arasan->has_cqe)
1472 return sdhci_add_host(host);
1474 ret = sdhci_setup_host(host);
1478 cq_host = devm_kzalloc(host->mmc->parent,
1479 sizeof(*cq_host), GFP_KERNEL);
1485 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
1486 cq_host->ops = &sdhci_arasan_cqhci_ops;
1488 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1490 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1492 ret = cqhci_init(cq_host, host->mmc, dma64);
1496 ret = __sdhci_add_host(host);
1503 sdhci_cleanup_host(host);
1507 static int sdhci_arasan_probe(struct platform_device *pdev)
1510 struct device_node *node;
1511 struct clk *clk_xin;
1512 struct sdhci_host *host;
1513 struct sdhci_pltfm_host *pltfm_host;
1514 struct device *dev = &pdev->dev;
1515 struct device_node *np = dev->of_node;
1516 struct sdhci_arasan_data *sdhci_arasan;
1517 const struct sdhci_arasan_of_data *data;
1519 data = of_device_get_match_data(dev);
1520 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
1523 return PTR_ERR(host);
1525 pltfm_host = sdhci_priv(host);
1526 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1527 sdhci_arasan->host = host;
1529 sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
1530 sdhci_arasan->clk_ops = data->clk_ops;
1532 node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0);
1534 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
1537 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
1538 ret = dev_err_probe(dev,
1539 PTR_ERR(sdhci_arasan->soc_ctl_base),
1540 "Can't get syscon\n");
1541 goto err_pltfm_free;
1545 sdhci_get_of_property(pdev);
1547 sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
1548 if (IS_ERR(sdhci_arasan->clk_ahb)) {
1549 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
1550 "clk_ahb clock not found.\n");
1551 goto err_pltfm_free;
1554 clk_xin = devm_clk_get(dev, "clk_xin");
1555 if (IS_ERR(clk_xin)) {
1556 ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n");
1557 goto err_pltfm_free;
1560 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
1562 dev_err(dev, "Unable to enable AHB clock.\n");
1563 goto err_pltfm_free;
1566 /* If clock-frequency property is set, use the provided value */
1567 if (pltfm_host->clock &&
1568 pltfm_host->clock != clk_get_rate(clk_xin)) {
1569 ret = clk_set_rate(clk_xin, pltfm_host->clock);
1571 dev_err(&pdev->dev, "Failed to set SD clock rate\n");
1576 ret = clk_prepare_enable(clk_xin);
1578 dev_err(dev, "Unable to enable SD clock.\n");
1582 if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
1583 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
1585 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
1586 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
1588 pltfm_host->clk = clk_xin;
1590 if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1"))
1591 sdhci_arasan_update_clockmultiplier(host, 0x0);
1593 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1594 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
1595 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
1596 sdhci_arasan_update_clockmultiplier(host, 0x0);
1597 sdhci_arasan_update_support64b(host, 0x0);
1599 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1602 sdhci_arasan_update_baseclkfreq(host);
1604 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev);
1606 goto clk_disable_all;
1608 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1609 host->mmc_host_ops.execute_tuning =
1610 arasan_zynqmp_execute_tuning;
1613 arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data);
1615 ret = mmc_of_parse(host->mmc);
1617 ret = dev_err_probe(dev, ret, "parsing dt failed.\n");
1621 sdhci_arasan->phy = ERR_PTR(-ENODEV);
1622 if (of_device_is_compatible(np, "arasan,sdhci-5.1")) {
1623 sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan");
1624 if (IS_ERR(sdhci_arasan->phy)) {
1625 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy),
1626 "No phy for arasan,sdhci-5.1.\n");
1630 ret = phy_init(sdhci_arasan->phy);
1632 dev_err(dev, "phy_init err.\n");
1636 host->mmc_host_ops.hs400_enhanced_strobe =
1637 sdhci_arasan_hs400_enhanced_strobe;
1638 host->mmc_host_ops.start_signal_voltage_switch =
1639 sdhci_arasan_voltage_switch;
1640 sdhci_arasan->has_cqe = true;
1641 host->mmc->caps2 |= MMC_CAP2_CQE;
1643 if (!of_property_read_bool(np, "disable-cqe-dcmd"))
1644 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
1647 ret = sdhci_arasan_add_host(sdhci_arasan);
1654 if (!IS_ERR(sdhci_arasan->phy))
1655 phy_exit(sdhci_arasan->phy);
1657 sdhci_arasan_unregister_sdclk(dev);
1659 clk_disable_unprepare(clk_xin);
1661 clk_disable_unprepare(sdhci_arasan->clk_ahb);
1663 sdhci_pltfm_free(pdev);
1667 static int sdhci_arasan_remove(struct platform_device *pdev)
1670 struct sdhci_host *host = platform_get_drvdata(pdev);
1671 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1672 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1673 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
1675 if (!IS_ERR(sdhci_arasan->phy)) {
1676 if (sdhci_arasan->is_phy_on)
1677 phy_power_off(sdhci_arasan->phy);
1678 phy_exit(sdhci_arasan->phy);
1681 sdhci_arasan_unregister_sdclk(&pdev->dev);
1683 ret = sdhci_pltfm_unregister(pdev);
1685 clk_disable_unprepare(clk_ahb);
1690 static struct platform_driver sdhci_arasan_driver = {
1692 .name = "sdhci-arasan",
1693 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1694 .of_match_table = sdhci_arasan_of_match,
1695 .pm = &sdhci_arasan_dev_pm_ops,
1697 .probe = sdhci_arasan_probe,
1698 .remove = sdhci_arasan_remove,
1701 module_platform_driver(sdhci_arasan_driver);
1703 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
1704 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
1705 MODULE_LICENSE("GPL");