1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/delay.h>
11 #include <linux/mmc/mmc.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/pm_opp.h>
14 #include <linux/slab.h>
15 #include <linux/iopoll.h>
16 #include <linux/qcom_scm.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/interconnect.h>
19 #include <linux/pinctrl/consumer.h>
21 #include "sdhci-pltfm.h"
24 #define CORE_MCI_VERSION 0x50
25 #define CORE_VERSION_MAJOR_SHIFT 28
26 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
27 #define CORE_VERSION_MINOR_MASK 0xff
29 #define CORE_MCI_GENERICS 0x70
30 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
32 #define HC_MODE_EN 0x1
33 #define CORE_POWER 0x0
34 #define CORE_SW_RST BIT(7)
35 #define FF_CLK_SW_RST_DIS BIT(13)
37 #define CORE_PWRCTL_BUS_OFF BIT(0)
38 #define CORE_PWRCTL_BUS_ON BIT(1)
39 #define CORE_PWRCTL_IO_LOW BIT(2)
40 #define CORE_PWRCTL_IO_HIGH BIT(3)
41 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
42 #define CORE_PWRCTL_BUS_FAIL BIT(1)
43 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
44 #define CORE_PWRCTL_IO_FAIL BIT(3)
45 #define REQ_BUS_OFF BIT(0)
46 #define REQ_BUS_ON BIT(1)
47 #define REQ_IO_LOW BIT(2)
48 #define REQ_IO_HIGH BIT(3)
51 #define CORE_DLL_LOCK BIT(7)
52 #define CORE_DDR_DLL_LOCK BIT(11)
53 #define CORE_DLL_EN BIT(16)
54 #define CORE_CDR_EN BIT(17)
55 #define CORE_CK_OUT_EN BIT(18)
56 #define CORE_CDR_EXT_EN BIT(19)
57 #define CORE_DLL_PDN BIT(29)
58 #define CORE_DLL_RST BIT(30)
59 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
61 #define CORE_DDR_CAL_EN BIT(0)
62 #define CORE_FLL_CYCLE_CNT BIT(18)
63 #define CORE_DLL_CLOCK_DISABLE BIT(21)
65 #define DLL_USR_CTL_POR_VAL 0x10800
66 #define ENABLE_DLL_LOCK_STATUS BIT(26)
67 #define FINE_TUNE_MODE_EN BIT(27)
68 #define BIAS_OK_SIGNAL BIT(29)
70 #define DLL_CONFIG_3_LOW_FREQ_VAL 0x08
71 #define DLL_CONFIG_3_HIGH_FREQ_VAL 0x10
73 #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
74 #define CORE_CLK_PWRSAVE BIT(1)
75 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
76 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
77 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
78 #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
79 #define CORE_IO_PAD_PWR_SWITCH BIT(16)
80 #define CORE_HC_SELECT_IN_EN BIT(18)
81 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
82 #define CORE_HC_SELECT_IN_MASK (7 << 19)
84 #define CORE_3_0V_SUPPORT BIT(25)
85 #define CORE_1_8V_SUPPORT BIT(26)
86 #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
88 #define CORE_CSR_CDC_CTLR_CFG0 0x130
89 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
90 #define CORE_HW_AUTOCAL_ENA BIT(17)
92 #define CORE_CSR_CDC_CTLR_CFG1 0x134
93 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
94 #define CORE_TIMER_ENA BIT(16)
96 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
97 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
98 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
99 #define CORE_CDC_OFFSET_CFG 0x14C
100 #define CORE_CSR_CDC_DELAY_CFG 0x150
101 #define CORE_CDC_SLAVE_DDA_CFG 0x160
102 #define CORE_CSR_CDC_STATUS0 0x164
103 #define CORE_CALIBRATION_DONE BIT(0)
105 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
107 #define CORE_CSR_CDC_GEN_CFG 0x178
108 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
109 #define CORE_CDC_SWITCH_RC_EN BIT(1)
111 #define CORE_CDC_T4_DLY_SEL BIT(0)
112 #define CORE_CMDIN_RCLK_EN BIT(1)
113 #define CORE_START_CDC_TRAFFIC BIT(6)
115 #define CORE_PWRSAVE_DLL BIT(3)
117 #define DDR_CONFIG_POR_VAL 0x80040873
120 #define INVALID_TUNING_PHASE -1
121 #define SDHCI_MSM_MIN_CLOCK 400000
122 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
124 #define CDR_SELEXT_SHIFT 20
125 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
126 #define CMUX_SHIFT_PHASE_SHIFT 24
127 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
129 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
131 /* Timeout value to avoid infinite waiting for pwr_irq */
132 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
134 /* Max load for eMMC Vdd-io supply */
135 #define MMC_VQMMC_MAX_LOAD_UA 325000
137 #define msm_host_readl(msm_host, host, offset) \
138 msm_host->var_ops->msm_readl_relaxed(host, offset)
140 #define msm_host_writel(msm_host, val, host, offset) \
141 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
143 /* CQHCI vendor specific registers */
144 #define CQHCI_VENDOR_CFG1 0xA00
145 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13)
147 struct sdhci_msm_offset {
149 u32 core_mci_data_cnt;
151 u32 core_mci_fifo_cnt;
152 u32 core_mci_version;
154 u32 core_testbus_config;
155 u32 core_testbus_sel2_bit;
156 u32 core_testbus_ena;
157 u32 core_testbus_sel2;
158 u32 core_pwrctl_status;
159 u32 core_pwrctl_mask;
160 u32 core_pwrctl_clear;
162 u32 core_sdcc_debug_reg;
165 u32 core_vendor_spec;
166 u32 core_vendor_spec_adma_err_addr0;
167 u32 core_vendor_spec_adma_err_addr1;
168 u32 core_vendor_spec_func2;
169 u32 core_vendor_spec_capabilities0;
170 u32 core_ddr_200_cfg;
171 u32 core_vendor_spec3;
172 u32 core_dll_config_2;
173 u32 core_dll_config_3;
174 u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
176 u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */
179 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
180 .core_mci_data_cnt = 0x35c,
181 .core_mci_status = 0x324,
182 .core_mci_fifo_cnt = 0x308,
183 .core_mci_version = 0x318,
184 .core_generics = 0x320,
185 .core_testbus_config = 0x32c,
186 .core_testbus_sel2_bit = 3,
187 .core_testbus_ena = (1 << 31),
188 .core_testbus_sel2 = (1 << 3),
189 .core_pwrctl_status = 0x240,
190 .core_pwrctl_mask = 0x244,
191 .core_pwrctl_clear = 0x248,
192 .core_pwrctl_ctl = 0x24c,
193 .core_sdcc_debug_reg = 0x358,
194 .core_dll_config = 0x200,
195 .core_dll_status = 0x208,
196 .core_vendor_spec = 0x20c,
197 .core_vendor_spec_adma_err_addr0 = 0x214,
198 .core_vendor_spec_adma_err_addr1 = 0x218,
199 .core_vendor_spec_func2 = 0x210,
200 .core_vendor_spec_capabilities0 = 0x21c,
201 .core_ddr_200_cfg = 0x224,
202 .core_vendor_spec3 = 0x250,
203 .core_dll_config_2 = 0x254,
204 .core_dll_config_3 = 0x258,
205 .core_ddr_config = 0x25c,
206 .core_dll_usr_ctl = 0x388,
209 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
210 .core_hc_mode = 0x78,
211 .core_mci_data_cnt = 0x30,
212 .core_mci_status = 0x34,
213 .core_mci_fifo_cnt = 0x44,
214 .core_mci_version = 0x050,
215 .core_generics = 0x70,
216 .core_testbus_config = 0x0cc,
217 .core_testbus_sel2_bit = 4,
218 .core_testbus_ena = (1 << 3),
219 .core_testbus_sel2 = (1 << 4),
220 .core_pwrctl_status = 0xdc,
221 .core_pwrctl_mask = 0xe0,
222 .core_pwrctl_clear = 0xe4,
223 .core_pwrctl_ctl = 0xe8,
224 .core_sdcc_debug_reg = 0x124,
225 .core_dll_config = 0x100,
226 .core_dll_status = 0x108,
227 .core_vendor_spec = 0x10c,
228 .core_vendor_spec_adma_err_addr0 = 0x114,
229 .core_vendor_spec_adma_err_addr1 = 0x118,
230 .core_vendor_spec_func2 = 0x110,
231 .core_vendor_spec_capabilities0 = 0x11c,
232 .core_ddr_200_cfg = 0x184,
233 .core_vendor_spec3 = 0x1b0,
234 .core_dll_config_2 = 0x1b4,
235 .core_ddr_config_old = 0x1b8,
236 .core_ddr_config = 0x1bc,
239 struct sdhci_msm_variant_ops {
240 u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
241 void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
246 * From V5, register spaces have changed. Wrap this info in a structure
247 * and choose the data_structure based on version info mentioned in DT.
249 struct sdhci_msm_variant_info {
251 bool restore_dll_config;
252 const struct sdhci_msm_variant_ops *var_ops;
253 const struct sdhci_msm_offset *offset;
256 struct sdhci_msm_host {
257 struct platform_device *pdev;
258 void __iomem *core_mem; /* MSM SDCC mapped address */
259 void __iomem *ice_mem; /* MSM ICE mapped address (if available) */
260 int pwr_irq; /* power irq */
261 struct clk *bus_clk; /* SDHC bus voter clock */
262 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
263 /* core, iface, cal, sleep, and ice clocks */
264 struct clk_bulk_data bulk_clks[5];
265 unsigned long clk_rate;
266 struct mmc_host *mmc;
267 bool use_14lpp_dll_reset;
269 bool calibration_done;
270 u8 saved_tuning_phase;
274 wait_queue_head_t pwr_irq_wait;
278 bool restore_dll_config;
279 const struct sdhci_msm_variant_ops *var_ops;
280 const struct sdhci_msm_offset *offset;
283 bool updated_ddr_cfg;
284 bool uses_tassadar_dll;
290 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
292 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
293 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
295 return msm_host->offset;
299 * APIs to read/write to vendor specific registers which were there in the
300 * core_mem region before MCI was removed.
302 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
305 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
306 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
308 return readl_relaxed(msm_host->core_mem + offset);
311 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
314 return readl_relaxed(host->ioaddr + offset);
317 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
318 struct sdhci_host *host, u32 offset)
320 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
321 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
323 writel_relaxed(val, msm_host->core_mem + offset);
326 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
327 struct sdhci_host *host, u32 offset)
329 writel_relaxed(val, host->ioaddr + offset);
332 static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host)
334 struct mmc_ios ios = host->mmc->ios;
336 * The SDHC requires internal clock frequency to be double the
337 * actual clock that will be set for DDR mode. The controller
338 * uses the faster clock(100/400MHz) for some of its parts and
339 * send the actual required clock (50/200MHz) to the card.
341 if (ios.timing == MMC_TIMING_UHS_DDR50 ||
342 ios.timing == MMC_TIMING_MMC_DDR52 ||
343 ios.timing == MMC_TIMING_MMC_HS400 ||
344 host->flags & SDHCI_HS400_TUNING)
349 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
352 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
353 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
354 struct mmc_ios curr_ios = host->mmc->ios;
355 struct clk *core_clk = msm_host->bulk_clks[0].clk;
356 unsigned long achieved_rate;
357 unsigned int desired_rate;
361 mult = msm_get_clock_mult_for_bus_mode(host);
362 desired_rate = clock * mult;
363 rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate);
365 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
366 mmc_hostname(host->mmc), desired_rate, curr_ios.timing);
371 * Qualcomm clock drivers by default round clock _up_ if they can't
372 * make the requested rate. This is not good for SD. Yell if we
375 achieved_rate = clk_get_rate(core_clk);
376 if (achieved_rate > desired_rate)
377 pr_warn("%s: Card appears overclocked; req %u Hz, actual %lu Hz\n",
378 mmc_hostname(host->mmc), desired_rate, achieved_rate);
379 host->mmc->actual_clock = achieved_rate / mult;
381 /* Stash the rate we requested to use in sdhci_msm_runtime_resume() */
382 msm_host->clk_rate = desired_rate;
384 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
385 mmc_hostname(host->mmc), achieved_rate, curr_ios.timing);
388 /* Platform specific tuning */
389 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
393 struct mmc_host *mmc = host->mmc;
394 const struct sdhci_msm_offset *msm_offset =
395 sdhci_priv_msm_offset(host);
397 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
398 ck_out_en = !!(readl_relaxed(host->ioaddr +
399 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
401 while (ck_out_en != poll) {
402 if (--wait_cnt == 0) {
403 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
404 mmc_hostname(mmc), poll);
409 ck_out_en = !!(readl_relaxed(host->ioaddr +
410 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
416 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
419 static const u8 grey_coded_phase_table[] = {
420 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
421 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
425 struct mmc_host *mmc = host->mmc;
426 const struct sdhci_msm_offset *msm_offset =
427 sdhci_priv_msm_offset(host);
432 spin_lock_irqsave(&host->lock, flags);
434 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
435 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
436 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
437 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
439 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
440 rc = msm_dll_poll_ck_out_en(host, 0);
445 * Write the selected DLL clock output phase (0 ... 15)
446 * to CDR_SELEXT bit field of DLL_CONFIG register.
448 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
449 config &= ~CDR_SELEXT_MASK;
450 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
451 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
453 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
454 config |= CORE_CK_OUT_EN;
455 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
457 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
458 rc = msm_dll_poll_ck_out_en(host, 1);
462 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
463 config |= CORE_CDR_EN;
464 config &= ~CORE_CDR_EXT_EN;
465 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
469 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
470 mmc_hostname(mmc), phase);
472 spin_unlock_irqrestore(&host->lock, flags);
477 * Find out the greatest range of consecuitive selected
478 * DLL clock output phases that can be used as sampling
479 * setting for SD3.0 UHS-I card read operation (in SDR104
480 * timing mode) or for eMMC4.5 card read operation (in
481 * HS400/HS200 timing mode).
482 * Select the 3/4 of the range and configure the DLL with the
483 * selected DLL clock output phase.
486 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
487 u8 *phase_table, u8 total_phases)
490 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
491 u8 phases_per_row[MAX_PHASES] = { 0 };
492 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
493 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
494 bool phase_0_found = false, phase_15_found = false;
495 struct mmc_host *mmc = host->mmc;
497 if (!total_phases || (total_phases > MAX_PHASES)) {
498 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
499 mmc_hostname(mmc), total_phases);
503 for (cnt = 0; cnt < total_phases; cnt++) {
504 ranges[row_index][col_index] = phase_table[cnt];
505 phases_per_row[row_index] += 1;
508 if ((cnt + 1) == total_phases) {
510 /* check if next phase in phase_table is consecutive or not */
511 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
517 if (row_index >= MAX_PHASES)
520 /* Check if phase-0 is present in first valid window? */
522 phase_0_found = true;
523 phase_0_raw_index = 0;
524 /* Check if cycle exist between 2 valid windows */
525 for (cnt = 1; cnt <= row_index; cnt++) {
526 if (phases_per_row[cnt]) {
527 for (i = 0; i < phases_per_row[cnt]; i++) {
528 if (ranges[cnt][i] == 15) {
529 phase_15_found = true;
530 phase_15_raw_index = cnt;
538 /* If 2 valid windows form cycle then merge them as single window */
539 if (phase_0_found && phase_15_found) {
540 /* number of phases in raw where phase 0 is present */
541 u8 phases_0 = phases_per_row[phase_0_raw_index];
542 /* number of phases in raw where phase 15 is present */
543 u8 phases_15 = phases_per_row[phase_15_raw_index];
545 if (phases_0 + phases_15 >= MAX_PHASES)
547 * If there are more than 1 phase windows then total
548 * number of phases in both the windows should not be
549 * more than or equal to MAX_PHASES.
553 /* Merge 2 cyclic windows */
555 for (cnt = 0; cnt < phases_0; cnt++) {
556 ranges[phase_15_raw_index][i] =
557 ranges[phase_0_raw_index][cnt];
558 if (++i >= MAX_PHASES)
562 phases_per_row[phase_0_raw_index] = 0;
563 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
566 for (cnt = 0; cnt <= row_index; cnt++) {
567 if (phases_per_row[cnt] > curr_max) {
568 curr_max = phases_per_row[cnt];
569 selected_row_index = cnt;
573 i = (curr_max * 3) / 4;
577 ret = ranges[selected_row_index][i];
579 if (ret >= MAX_PHASES) {
581 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
582 mmc_hostname(mmc), ret);
588 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
590 u32 mclk_freq = 0, config;
591 const struct sdhci_msm_offset *msm_offset =
592 sdhci_priv_msm_offset(host);
594 /* Program the MCLK value to MCLK_FREQ bit field */
595 if (host->clock <= 112000000)
597 else if (host->clock <= 125000000)
599 else if (host->clock <= 137000000)
601 else if (host->clock <= 150000000)
603 else if (host->clock <= 162000000)
605 else if (host->clock <= 175000000)
607 else if (host->clock <= 187000000)
609 else if (host->clock <= 200000000)
612 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
613 config &= ~CMUX_SHIFT_PHASE_MASK;
614 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
615 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
618 /* Initialize the DLL (Programmable Delay Line) */
619 static int msm_init_cm_dll(struct sdhci_host *host)
621 struct mmc_host *mmc = host->mmc;
622 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
623 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
625 unsigned long flags, xo_clk = 0;
627 const struct sdhci_msm_offset *msm_offset =
630 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
631 xo_clk = clk_get_rate(msm_host->xo_clk);
633 spin_lock_irqsave(&host->lock, flags);
636 * Make sure that clock is always enabled when DLL
637 * tuning is in progress. Keeping PWRSAVE ON may
638 * turn off the clock.
640 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
641 config &= ~CORE_CLK_PWRSAVE;
642 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
644 if (msm_host->dll_config)
645 writel_relaxed(msm_host->dll_config,
646 host->ioaddr + msm_offset->core_dll_config);
648 if (msm_host->use_14lpp_dll_reset) {
649 config = readl_relaxed(host->ioaddr +
650 msm_offset->core_dll_config);
651 config &= ~CORE_CK_OUT_EN;
652 writel_relaxed(config, host->ioaddr +
653 msm_offset->core_dll_config);
655 config = readl_relaxed(host->ioaddr +
656 msm_offset->core_dll_config_2);
657 config |= CORE_DLL_CLOCK_DISABLE;
658 writel_relaxed(config, host->ioaddr +
659 msm_offset->core_dll_config_2);
662 config = readl_relaxed(host->ioaddr +
663 msm_offset->core_dll_config);
664 config |= CORE_DLL_RST;
665 writel_relaxed(config, host->ioaddr +
666 msm_offset->core_dll_config);
668 config = readl_relaxed(host->ioaddr +
669 msm_offset->core_dll_config);
670 config |= CORE_DLL_PDN;
671 writel_relaxed(config, host->ioaddr +
672 msm_offset->core_dll_config);
674 if (!msm_host->dll_config)
675 msm_cm_dll_set_freq(host);
677 if (msm_host->use_14lpp_dll_reset &&
678 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
681 config = readl_relaxed(host->ioaddr +
682 msm_offset->core_dll_config_2);
683 config &= CORE_FLL_CYCLE_CNT;
685 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
688 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
691 config = readl_relaxed(host->ioaddr +
692 msm_offset->core_dll_config_2);
693 config &= ~(0xFF << 10);
694 config |= mclk_freq << 10;
696 writel_relaxed(config, host->ioaddr +
697 msm_offset->core_dll_config_2);
698 /* wait for 5us before enabling DLL clock */
702 config = readl_relaxed(host->ioaddr +
703 msm_offset->core_dll_config);
704 config &= ~CORE_DLL_RST;
705 writel_relaxed(config, host->ioaddr +
706 msm_offset->core_dll_config);
708 config = readl_relaxed(host->ioaddr +
709 msm_offset->core_dll_config);
710 config &= ~CORE_DLL_PDN;
711 writel_relaxed(config, host->ioaddr +
712 msm_offset->core_dll_config);
714 if (msm_host->use_14lpp_dll_reset) {
715 if (!msm_host->dll_config)
716 msm_cm_dll_set_freq(host);
717 config = readl_relaxed(host->ioaddr +
718 msm_offset->core_dll_config_2);
719 config &= ~CORE_DLL_CLOCK_DISABLE;
720 writel_relaxed(config, host->ioaddr +
721 msm_offset->core_dll_config_2);
725 * Configure DLL user control register to enable DLL status.
726 * This setting is applicable to SDCC v5.1 onwards only.
728 if (msm_host->uses_tassadar_dll) {
729 config = DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN |
730 ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL;
731 writel_relaxed(config, host->ioaddr +
732 msm_offset->core_dll_usr_ctl);
734 config = readl_relaxed(host->ioaddr +
735 msm_offset->core_dll_config_3);
737 if (msm_host->clk_rate < 150000000)
738 config |= DLL_CONFIG_3_LOW_FREQ_VAL;
740 config |= DLL_CONFIG_3_HIGH_FREQ_VAL;
741 writel_relaxed(config, host->ioaddr +
742 msm_offset->core_dll_config_3);
745 config = readl_relaxed(host->ioaddr +
746 msm_offset->core_dll_config);
747 config |= CORE_DLL_EN;
748 writel_relaxed(config, host->ioaddr +
749 msm_offset->core_dll_config);
751 config = readl_relaxed(host->ioaddr +
752 msm_offset->core_dll_config);
753 config |= CORE_CK_OUT_EN;
754 writel_relaxed(config, host->ioaddr +
755 msm_offset->core_dll_config);
757 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
758 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
760 /* max. wait for 50us sec for LOCK bit to be set */
761 if (--wait_cnt == 0) {
762 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
764 spin_unlock_irqrestore(&host->lock, flags);
770 spin_unlock_irqrestore(&host->lock, flags);
774 static void msm_hc_select_default(struct sdhci_host *host)
776 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
777 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
779 const struct sdhci_msm_offset *msm_offset =
782 if (!msm_host->use_cdclp533) {
783 config = readl_relaxed(host->ioaddr +
784 msm_offset->core_vendor_spec3);
785 config &= ~CORE_PWRSAVE_DLL;
786 writel_relaxed(config, host->ioaddr +
787 msm_offset->core_vendor_spec3);
790 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
791 config &= ~CORE_HC_MCLK_SEL_MASK;
792 config |= CORE_HC_MCLK_SEL_DFLT;
793 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
796 * Disable HC_SELECT_IN to be able to use the UHS mode select
797 * configuration from Host Control2 register for all other
799 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
800 * in VENDOR_SPEC_FUNC
802 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
803 config &= ~CORE_HC_SELECT_IN_EN;
804 config &= ~CORE_HC_SELECT_IN_MASK;
805 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
808 * Make sure above writes impacting free running MCLK are completed
809 * before changing the clk_rate at GCC.
814 static void msm_hc_select_hs400(struct sdhci_host *host)
816 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
817 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
818 struct mmc_ios ios = host->mmc->ios;
819 u32 config, dll_lock;
821 const struct sdhci_msm_offset *msm_offset =
824 /* Select the divided clock (free running MCLK/2) */
825 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
826 config &= ~CORE_HC_MCLK_SEL_MASK;
827 config |= CORE_HC_MCLK_SEL_HS400;
829 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
831 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
834 if ((msm_host->tuning_done || ios.enhanced_strobe) &&
835 !msm_host->calibration_done) {
836 config = readl_relaxed(host->ioaddr +
837 msm_offset->core_vendor_spec);
838 config |= CORE_HC_SELECT_IN_HS400;
839 config |= CORE_HC_SELECT_IN_EN;
840 writel_relaxed(config, host->ioaddr +
841 msm_offset->core_vendor_spec);
843 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
845 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
846 * core_dll_status to be set. This should get set
847 * within 15 us at 200 MHz.
849 rc = readl_relaxed_poll_timeout(host->ioaddr +
850 msm_offset->core_dll_status,
854 CORE_DDR_DLL_LOCK)), 10,
856 if (rc == -ETIMEDOUT)
857 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
858 mmc_hostname(host->mmc), dll_lock);
861 * Make sure above writes impacting free running MCLK are completed
862 * before changing the clk_rate at GCC.
868 * sdhci_msm_hc_select_mode :- In general all timing modes are
869 * controlled via UHS mode select in Host Control2 register.
870 * eMMC specific HS200/HS400 doesn't have their respective modes
871 * defined here, hence we use these values.
873 * HS200 - SDR104 (Since they both are equivalent in functionality)
874 * HS400 - This involves multiple configurations
875 * Initially SDR104 - when tuning is required as HS200
876 * Then when switching to DDR @ 400MHz (HS400) we use
877 * the vendor specific HC_SELECT_IN to control the mode.
879 * In addition to controlling the modes we also need to select the
880 * correct input clock for DLL depending on the mode.
882 * HS400 - divided clock (free running MCLK/2)
883 * All other modes - default (free running MCLK)
885 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
887 struct mmc_ios ios = host->mmc->ios;
889 if (ios.timing == MMC_TIMING_MMC_HS400 ||
890 host->flags & SDHCI_HS400_TUNING)
891 msm_hc_select_hs400(host);
893 msm_hc_select_default(host);
896 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
898 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
899 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
900 u32 config, calib_done;
902 const struct sdhci_msm_offset *msm_offset =
905 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
908 * Retuning in HS400 (DDR mode) will fail, just reset the
909 * tuning block and restore the saved tuning phase.
911 ret = msm_init_cm_dll(host);
915 /* Set the selected phase in delay line hw block */
916 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
920 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
921 config |= CORE_CMD_DAT_TRACK_SEL;
922 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
924 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
925 config &= ~CORE_CDC_T4_DLY_SEL;
926 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
928 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
929 config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
930 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
932 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
933 config |= CORE_CDC_SWITCH_RC_EN;
934 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
936 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
937 config &= ~CORE_START_CDC_TRAFFIC;
938 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
940 /* Perform CDC Register Initialization Sequence */
942 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
943 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
944 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
945 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
946 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
947 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
948 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
949 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
950 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
952 /* CDC HW Calibration */
954 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
955 config |= CORE_SW_TRIG_FULL_CALIB;
956 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
958 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
959 config &= ~CORE_SW_TRIG_FULL_CALIB;
960 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
962 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
963 config |= CORE_HW_AUTOCAL_ENA;
964 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
966 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
967 config |= CORE_TIMER_ENA;
968 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
970 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
972 (calib_done & CORE_CALIBRATION_DONE),
975 if (ret == -ETIMEDOUT) {
976 pr_err("%s: %s: CDC calibration was not completed\n",
977 mmc_hostname(host->mmc), __func__);
981 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
982 & CORE_CDC_ERROR_CODE_MASK;
984 pr_err("%s: %s: CDC error code %d\n",
985 mmc_hostname(host->mmc), __func__, ret);
990 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
991 config |= CORE_START_CDC_TRAFFIC;
992 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
994 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
999 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
1001 struct mmc_host *mmc = host->mmc;
1002 u32 dll_status, config, ddr_cfg_offset;
1004 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1005 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1006 const struct sdhci_msm_offset *msm_offset =
1007 sdhci_priv_msm_offset(host);
1009 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1012 * Currently the core_ddr_config register defaults to desired
1013 * configuration on reset. Currently reprogramming the power on
1014 * reset (POR) value in case it might have been modified by
1015 * bootloaders. In the future, if this changes, then the desired
1016 * values will need to be programmed appropriately.
1018 if (msm_host->updated_ddr_cfg)
1019 ddr_cfg_offset = msm_offset->core_ddr_config;
1021 ddr_cfg_offset = msm_offset->core_ddr_config_old;
1022 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
1024 if (mmc->ios.enhanced_strobe) {
1025 config = readl_relaxed(host->ioaddr +
1026 msm_offset->core_ddr_200_cfg);
1027 config |= CORE_CMDIN_RCLK_EN;
1028 writel_relaxed(config, host->ioaddr +
1029 msm_offset->core_ddr_200_cfg);
1032 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
1033 config |= CORE_DDR_CAL_EN;
1034 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
1036 ret = readl_relaxed_poll_timeout(host->ioaddr +
1037 msm_offset->core_dll_status,
1039 (dll_status & CORE_DDR_DLL_LOCK),
1042 if (ret == -ETIMEDOUT) {
1043 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
1044 mmc_hostname(host->mmc), __func__);
1049 * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
1050 * When MCLK is gated OFF, it is not gated for less than 0.5us
1051 * and MCLK must be switched on for at-least 1us before DATA
1052 * starts coming. Controllers with 14lpp and later tech DLL cannot
1053 * guarantee above requirement. So PWRSAVE_DLL should not be
1054 * turned on for host controllers using this DLL.
1056 if (!msm_host->use_14lpp_dll_reset) {
1057 config = readl_relaxed(host->ioaddr +
1058 msm_offset->core_vendor_spec3);
1059 config |= CORE_PWRSAVE_DLL;
1060 writel_relaxed(config, host->ioaddr +
1061 msm_offset->core_vendor_spec3);
1065 * Drain writebuffer to ensure above DLL calibration
1066 * and PWRSAVE DLL is enabled.
1070 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1075 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
1077 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1078 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1079 struct mmc_host *mmc = host->mmc;
1082 const struct sdhci_msm_offset *msm_offset =
1085 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1088 * Retuning in HS400 (DDR mode) will fail, just reset the
1089 * tuning block and restore the saved tuning phase.
1091 ret = msm_init_cm_dll(host);
1095 if (!mmc->ios.enhanced_strobe) {
1096 /* Set the selected phase in delay line hw block */
1097 ret = msm_config_cm_dll_phase(host,
1098 msm_host->saved_tuning_phase);
1101 config = readl_relaxed(host->ioaddr +
1102 msm_offset->core_dll_config);
1103 config |= CORE_CMD_DAT_TRACK_SEL;
1104 writel_relaxed(config, host->ioaddr +
1105 msm_offset->core_dll_config);
1108 if (msm_host->use_cdclp533)
1109 ret = sdhci_msm_cdclp533_calibration(host);
1111 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1113 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1118 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1120 struct mmc_ios *ios = &host->mmc->ios;
1123 * Tuning is required for SDR104, HS200 and HS400 cards and
1124 * if clock frequency is greater than 100MHz in these modes.
1126 if (host->clock <= CORE_FREQ_100MHZ ||
1127 !(ios->timing == MMC_TIMING_MMC_HS400 ||
1128 ios->timing == MMC_TIMING_MMC_HS200 ||
1129 ios->timing == MMC_TIMING_UHS_SDR104) ||
1130 ios->enhanced_strobe)
1136 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1138 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1139 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1143 * SDR DLL comes into picture only for timing modes which needs
1146 if (!sdhci_msm_is_tuning_needed(host))
1149 /* Reset the tuning block */
1150 ret = msm_init_cm_dll(host);
1154 /* Restore the tuning block */
1155 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1160 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1162 const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1163 u32 config, oldconfig = readl_relaxed(host->ioaddr +
1164 msm_offset->core_dll_config);
1168 config |= CORE_CDR_EN;
1169 config &= ~CORE_CDR_EXT_EN;
1171 config &= ~CORE_CDR_EN;
1172 config |= CORE_CDR_EXT_EN;
1175 if (config != oldconfig) {
1176 writel_relaxed(config, host->ioaddr +
1177 msm_offset->core_dll_config);
1181 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1183 struct sdhci_host *host = mmc_priv(mmc);
1184 int tuning_seq_cnt = 10;
1185 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1187 struct mmc_ios ios = host->mmc->ios;
1188 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1189 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1191 if (!sdhci_msm_is_tuning_needed(host)) {
1192 msm_host->use_cdr = false;
1193 sdhci_msm_set_cdr(host, false);
1197 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1198 msm_host->use_cdr = true;
1201 * Clear tuning_done flag before tuning to ensure proper
1204 msm_host->tuning_done = 0;
1207 * For HS400 tuning in HS200 timing requires:
1208 * - select MCLK/2 in VENDOR_SPEC
1209 * - program MCLK to 400MHz (or nearest supported) in GCC
1211 if (host->flags & SDHCI_HS400_TUNING) {
1212 sdhci_msm_hc_select_mode(host);
1213 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1214 host->flags &= ~SDHCI_HS400_TUNING;
1218 /* First of all reset the tuning block */
1219 rc = msm_init_cm_dll(host);
1225 /* Set the phase in delay line hw block */
1226 rc = msm_config_cm_dll_phase(host, phase);
1230 rc = mmc_send_tuning(mmc, opcode, NULL);
1232 /* Tuning is successful at this tuning point */
1233 tuned_phases[tuned_phase_cnt++] = phase;
1234 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1235 mmc_hostname(mmc), phase);
1237 } while (++phase < ARRAY_SIZE(tuned_phases));
1239 if (tuned_phase_cnt) {
1240 if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) {
1242 * All phases valid is _almost_ as bad as no phases
1243 * valid. Probably all phases are not really reliable
1244 * but we didn't detect where the unreliable place is.
1245 * That means we'll essentially be guessing and hoping
1246 * we get a good phase. Better to try a few times.
1248 dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n",
1250 if (--tuning_seq_cnt) {
1251 tuned_phase_cnt = 0;
1256 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1264 * Finally set the selected phase in delay
1267 rc = msm_config_cm_dll_phase(host, phase);
1270 msm_host->saved_tuning_phase = phase;
1271 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1272 mmc_hostname(mmc), phase);
1274 if (--tuning_seq_cnt)
1277 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1283 msm_host->tuning_done = true;
1288 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1289 * This needs to be done for both tuning and enhanced_strobe mode.
1290 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1291 * fixed feedback clock is used.
1293 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1295 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1296 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1299 if (host->clock > CORE_FREQ_100MHZ &&
1300 (msm_host->tuning_done || ios->enhanced_strobe) &&
1301 !msm_host->calibration_done) {
1302 ret = sdhci_msm_hs400_dll_calibration(host);
1304 msm_host->calibration_done = true;
1306 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1307 mmc_hostname(host->mmc), ret);
1311 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1314 struct mmc_host *mmc = host->mmc;
1315 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1316 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1319 const struct sdhci_msm_offset *msm_offset =
1322 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1323 /* Select Bus Speed Mode for host */
1324 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1326 case MMC_TIMING_UHS_SDR12:
1327 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1329 case MMC_TIMING_UHS_SDR25:
1330 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1332 case MMC_TIMING_UHS_SDR50:
1333 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1335 case MMC_TIMING_MMC_HS400:
1336 case MMC_TIMING_MMC_HS200:
1337 case MMC_TIMING_UHS_SDR104:
1338 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1340 case MMC_TIMING_UHS_DDR50:
1341 case MMC_TIMING_MMC_DDR52:
1342 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1347 * When clock frequency is less than 100MHz, the feedback clock must be
1348 * provided and DLL must not be used so that tuning can be skipped. To
1349 * provide feedback clock, the mode selection can be any value less
1350 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1352 if (host->clock <= CORE_FREQ_100MHZ) {
1353 if (uhs == MMC_TIMING_MMC_HS400 ||
1354 uhs == MMC_TIMING_MMC_HS200 ||
1355 uhs == MMC_TIMING_UHS_SDR104)
1356 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1358 * DLL is not required for clock <= 100MHz
1359 * Thus, make sure DLL it is disabled when not required
1361 config = readl_relaxed(host->ioaddr +
1362 msm_offset->core_dll_config);
1363 config |= CORE_DLL_RST;
1364 writel_relaxed(config, host->ioaddr +
1365 msm_offset->core_dll_config);
1367 config = readl_relaxed(host->ioaddr +
1368 msm_offset->core_dll_config);
1369 config |= CORE_DLL_PDN;
1370 writel_relaxed(config, host->ioaddr +
1371 msm_offset->core_dll_config);
1374 * The DLL needs to be restored and CDCLP533 recalibrated
1375 * when the clock frequency is set back to 400MHz.
1377 msm_host->calibration_done = false;
1380 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1381 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1382 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1384 if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1385 sdhci_msm_hs400(host, &mmc->ios);
1388 static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
1390 struct platform_device *pdev = msm_host->pdev;
1394 ret = pinctrl_pm_select_default_state(&pdev->dev);
1396 ret = pinctrl_pm_select_sleep_state(&pdev->dev);
1401 static int sdhci_msm_set_vmmc(struct mmc_host *mmc)
1403 if (IS_ERR(mmc->supply.vmmc))
1406 return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd);
1409 static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,
1410 struct mmc_host *mmc, bool level)
1415 if (msm_host->vqmmc_enabled == level)
1419 /* Set the IO voltage regulator to default voltage level */
1420 if (msm_host->caps_0 & CORE_3_0V_SUPPORT)
1421 ios.signal_voltage = MMC_SIGNAL_VOLTAGE_330;
1422 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)
1423 ios.signal_voltage = MMC_SIGNAL_VOLTAGE_180;
1425 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1426 ret = mmc_regulator_set_vqmmc(mmc, &ios);
1428 dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n",
1429 mmc_hostname(mmc), ret);
1433 ret = regulator_enable(mmc->supply.vqmmc);
1435 ret = regulator_disable(mmc->supply.vqmmc);
1439 dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n",
1440 mmc_hostname(mmc), level ? "en":"dis", ret);
1442 msm_host->vqmmc_enabled = level;
1447 static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,
1448 struct mmc_host *mmc, bool hpm)
1452 load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0;
1453 ret = regulator_set_load(mmc->supply.vqmmc, load);
1455 dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n",
1456 mmc_hostname(mmc), ret);
1460 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,
1461 struct mmc_host *mmc, bool level)
1466 if (IS_ERR(mmc->supply.vqmmc) ||
1467 (mmc->ios.power_mode == MMC_POWER_UNDEFINED))
1470 * For eMMC don't turn off Vqmmc, Instead just configure it in LPM
1471 * and HPM modes by setting the corresponding load.
1473 * Till eMMC is initialized (i.e. always_on == 0), just turn on/off
1474 * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off
1475 * gets invoked. Once eMMC is initialized (i.e. always_on == 1),
1476 * Vqmmc should remain ON, So just set the load instead of turning it
1479 always_on = !mmc_card_is_removable(mmc) &&
1480 mmc->card && mmc_card_mmc(mmc->card);
1483 ret = msm_config_vqmmc_mode(msm_host, mmc, level);
1485 ret = msm_toggle_vqmmc(msm_host, mmc, level);
1490 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1492 init_waitqueue_head(&msm_host->pwr_irq_wait);
1495 static inline void sdhci_msm_complete_pwr_irq_wait(
1496 struct sdhci_msm_host *msm_host)
1498 wake_up(&msm_host->pwr_irq_wait);
1502 * sdhci_msm_check_power_status API should be called when registers writes
1503 * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1504 * To what state the register writes will change the IO lines should be passed
1505 * as the argument req_type. This API will check whether the IO line's state
1506 * is already the expected state and will wait for power irq only if
1507 * power irq is expected to be triggered based on the current IO line state
1508 * and expected IO line state.
1510 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1512 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1513 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1515 u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1516 const struct sdhci_msm_offset *msm_offset =
1519 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1520 mmc_hostname(host->mmc), __func__, req_type,
1521 msm_host->curr_pwr_state, msm_host->curr_io_level);
1524 * The power interrupt will not be generated for signal voltage
1525 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1526 * Since sdhci-msm-v5, this bit has been removed and SW must consider
1529 if (!msm_host->mci_removed)
1530 val = msm_host_readl(msm_host, host,
1531 msm_offset->core_generics);
1532 if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1533 !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1538 * The IRQ for request type IO High/LOW will be generated when -
1539 * there is a state change in 1.8V enable bit (bit 3) of
1540 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1541 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1542 * to set it to 3.3V before card detection happens, the
1543 * IRQ doesn't get triggered as there is no state change in this bit.
1544 * The driver already handles this case by changing the IO voltage
1545 * level to high as part of controller power up sequence. Hence, check
1546 * for host->pwr to handle a case where IO voltage high request is
1547 * issued even before controller power up.
1549 if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1550 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1551 mmc_hostname(host->mmc), req_type);
1554 if ((req_type & msm_host->curr_pwr_state) ||
1555 (req_type & msm_host->curr_io_level))
1558 * This is needed here to handle cases where register writes will
1559 * not change the current bus state or io level of the controller.
1560 * In this case, no power irq will be triggerred and we should
1564 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1565 msm_host->pwr_irq_flag,
1566 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1567 dev_warn(&msm_host->pdev->dev,
1568 "%s: pwr_irq for req: (%d) timed out\n",
1569 mmc_hostname(host->mmc), req_type);
1571 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1572 __func__, req_type);
1575 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1577 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1578 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1579 const struct sdhci_msm_offset *msm_offset =
1582 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1583 mmc_hostname(host->mmc),
1584 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1585 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1586 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1589 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1591 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1592 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1593 struct mmc_host *mmc = host->mmc;
1594 u32 irq_status, irq_ack = 0;
1595 int retry = 10, ret;
1596 u32 pwr_state = 0, io_level = 0;
1598 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1600 irq_status = msm_host_readl(msm_host, host,
1601 msm_offset->core_pwrctl_status);
1602 irq_status &= INT_MASK;
1604 msm_host_writel(msm_host, irq_status, host,
1605 msm_offset->core_pwrctl_clear);
1608 * There is a rare HW scenario where the first clear pulse could be
1609 * lost when actual reset and clear/read of status register is
1610 * happening at a time. Hence, retry for at least 10 times to make
1611 * sure status register is cleared. Otherwise, this will result in
1612 * a spurious power IRQ resulting in system instability.
1614 while (irq_status & msm_host_readl(msm_host, host,
1615 msm_offset->core_pwrctl_status)) {
1617 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1618 mmc_hostname(host->mmc), irq_status);
1619 sdhci_msm_dump_pwr_ctrl_regs(host);
1623 msm_host_writel(msm_host, irq_status, host,
1624 msm_offset->core_pwrctl_clear);
1629 /* Handle BUS ON/OFF*/
1630 if (irq_status & CORE_PWRCTL_BUS_ON) {
1631 pwr_state = REQ_BUS_ON;
1632 io_level = REQ_IO_HIGH;
1634 if (irq_status & CORE_PWRCTL_BUS_OFF) {
1635 pwr_state = REQ_BUS_OFF;
1636 io_level = REQ_IO_LOW;
1640 ret = sdhci_msm_set_vmmc(mmc);
1642 ret = sdhci_msm_set_vqmmc(msm_host, mmc,
1643 pwr_state & REQ_BUS_ON);
1645 ret = sdhci_msm_set_pincfg(msm_host,
1646 pwr_state & REQ_BUS_ON);
1648 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1650 irq_ack |= CORE_PWRCTL_BUS_FAIL;
1653 /* Handle IO LOW/HIGH */
1654 if (irq_status & CORE_PWRCTL_IO_LOW)
1655 io_level = REQ_IO_LOW;
1657 if (irq_status & CORE_PWRCTL_IO_HIGH)
1658 io_level = REQ_IO_HIGH;
1661 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1663 if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) {
1664 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
1666 dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",
1667 mmc_hostname(mmc), ret,
1668 mmc->ios.signal_voltage, mmc->ios.vdd,
1670 irq_ack |= CORE_PWRCTL_IO_FAIL;
1675 * The driver has to acknowledge the interrupt, switch voltages and
1676 * report back if it succeded or not to this register. The voltage
1677 * switches are handled by the sdhci core, so just report success.
1679 msm_host_writel(msm_host, irq_ack, host,
1680 msm_offset->core_pwrctl_ctl);
1683 * If we don't have info regarding the voltage levels supported by
1684 * regulators, don't change the IO PAD PWR SWITCH.
1686 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1689 * We should unset IO PAD PWR switch only if the register write
1690 * can set IO lines high and the regulator also switches to 3 V.
1691 * Else, we should keep the IO PAD PWR switch set.
1692 * This is applicable to certain targets where eMMC vccq supply
1693 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1694 * IO PAD PWR switch must be kept set to reflect actual
1695 * regulator voltage. This way, during initialization of
1696 * controllers with only 1.8V, we will set the IO PAD bit
1697 * without waiting for a REQ_IO_LOW.
1699 config = readl_relaxed(host->ioaddr +
1700 msm_offset->core_vendor_spec);
1701 new_config = config;
1703 if ((io_level & REQ_IO_HIGH) &&
1704 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1705 new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1706 else if ((io_level & REQ_IO_LOW) ||
1707 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1708 new_config |= CORE_IO_PAD_PWR_SWITCH;
1710 if (config ^ new_config)
1711 writel_relaxed(new_config, host->ioaddr +
1712 msm_offset->core_vendor_spec);
1716 msm_host->curr_pwr_state = pwr_state;
1718 msm_host->curr_io_level = io_level;
1720 dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1721 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1725 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1727 struct sdhci_host *host = (struct sdhci_host *)data;
1728 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1729 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1731 sdhci_msm_handle_pwr_irq(host, irq);
1732 msm_host->pwr_irq_flag = 1;
1733 sdhci_msm_complete_pwr_irq_wait(msm_host);
1739 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1741 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1742 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1743 struct clk *core_clk = msm_host->bulk_clks[0].clk;
1745 return clk_round_rate(core_clk, ULONG_MAX);
1748 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1750 return SDHCI_MSM_MIN_CLOCK;
1754 * __sdhci_msm_set_clock - sdhci_msm clock control.
1757 * MSM controller does not use internal divider and
1758 * instead directly control the GCC clock as per
1759 * HW recommendation.
1761 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1765 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1771 * MSM controller do not use clock divider.
1772 * Thus read SDHCI_CLOCK_CONTROL and only enable
1773 * clock with no divider value programmed.
1775 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1776 sdhci_enable_clk(host, clk);
1779 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1780 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1782 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1783 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1786 host->mmc->actual_clock = msm_host->clk_rate = 0;
1790 sdhci_msm_hc_select_mode(host);
1792 msm_set_clock_rate_for_bus_mode(host, clock);
1794 __sdhci_msm_set_clock(host, clock);
1797 /*****************************************************************************\
1799 * Inline Crypto Engine (ICE) support *
1801 \*****************************************************************************/
1803 #ifdef CONFIG_MMC_CRYPTO
1805 #define AES_256_XTS_KEY_SIZE 64
1807 /* QCOM ICE registers */
1809 #define QCOM_ICE_REG_VERSION 0x0008
1811 #define QCOM_ICE_REG_FUSE_SETTING 0x0010
1812 #define QCOM_ICE_FUSE_SETTING_MASK 0x1
1813 #define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2
1814 #define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4
1816 #define QCOM_ICE_REG_BIST_STATUS 0x0070
1817 #define QCOM_ICE_BIST_STATUS_MASK 0xF0000000
1819 #define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000
1821 #define sdhci_msm_ice_writel(host, val, reg) \
1822 writel((val), (host)->ice_mem + (reg))
1823 #define sdhci_msm_ice_readl(host, reg) \
1824 readl((host)->ice_mem + (reg))
1826 static bool sdhci_msm_ice_supported(struct sdhci_msm_host *msm_host)
1828 struct device *dev = mmc_dev(msm_host->mmc);
1829 u32 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_VERSION);
1830 int major = regval >> 24;
1831 int minor = (regval >> 16) & 0xFF;
1832 int step = regval & 0xFFFF;
1834 /* For now this driver only supports ICE version 3. */
1836 dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n",
1837 major, minor, step);
1841 dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n",
1842 major, minor, step);
1844 /* If fuses are blown, ICE might not work in the standard way. */
1845 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_FUSE_SETTING);
1846 if (regval & (QCOM_ICE_FUSE_SETTING_MASK |
1847 QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK |
1848 QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) {
1849 dev_warn(dev, "Fuses are blown; ICE is unusable!\n");
1855 static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev)
1857 return devm_clk_get(dev, "ice");
1860 static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
1861 struct cqhci_host *cq_host)
1863 struct mmc_host *mmc = msm_host->mmc;
1864 struct device *dev = mmc_dev(mmc);
1865 struct resource *res;
1868 if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
1871 res = platform_get_resource_byname(msm_host->pdev, IORESOURCE_MEM,
1874 dev_warn(dev, "ICE registers not found\n");
1878 if (!qcom_scm_ice_available()) {
1879 dev_warn(dev, "ICE SCM interface not found\n");
1883 msm_host->ice_mem = devm_ioremap_resource(dev, res);
1884 if (IS_ERR(msm_host->ice_mem)) {
1885 err = PTR_ERR(msm_host->ice_mem);
1886 dev_err(dev, "Failed to map ICE registers; err=%d\n", err);
1890 if (!sdhci_msm_ice_supported(msm_host))
1893 mmc->caps2 |= MMC_CAP2_CRYPTO;
1897 dev_warn(dev, "Disabling inline encryption support\n");
1901 static void sdhci_msm_ice_low_power_mode_enable(struct sdhci_msm_host *msm_host)
1905 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL);
1907 * Enable low power mode sequence
1908 * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0
1911 sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
1914 static void sdhci_msm_ice_optimization_enable(struct sdhci_msm_host *msm_host)
1918 /* ICE Optimizations Enable Sequence */
1919 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL);
1920 regval |= 0xD807100;
1921 /* ICE HPG requires delay before writing */
1923 sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
1928 * Wait until the ICE BIST (built-in self-test) has completed.
1930 * This may be necessary before ICE can be used.
1932 * Note that we don't really care whether the BIST passed or failed; we really
1933 * just want to make sure that it isn't still running. This is because (a) the
1934 * BIST is a FIPS compliance thing that never fails in practice, (b) ICE is
1935 * documented to reject crypto requests if the BIST fails, so we needn't do it
1936 * in software too, and (c) properly testing storage encryption requires testing
1937 * the full storage stack anyway, and not relying on hardware-level self-tests.
1939 static int sdhci_msm_ice_wait_bist_status(struct sdhci_msm_host *msm_host)
1944 err = readl_poll_timeout(msm_host->ice_mem + QCOM_ICE_REG_BIST_STATUS,
1945 regval, !(regval & QCOM_ICE_BIST_STATUS_MASK),
1948 dev_err(mmc_dev(msm_host->mmc),
1949 "Timed out waiting for ICE self-test to complete\n");
1953 static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
1955 if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO))
1957 sdhci_msm_ice_low_power_mode_enable(msm_host);
1958 sdhci_msm_ice_optimization_enable(msm_host);
1959 sdhci_msm_ice_wait_bist_status(msm_host);
1962 static int __maybe_unused sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
1964 if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO))
1966 return sdhci_msm_ice_wait_bist_status(msm_host);
1970 * Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires
1971 * vendor-specific SCM calls for this; it doesn't support the standard way.
1973 static int sdhci_msm_program_key(struct cqhci_host *cq_host,
1974 const union cqhci_crypto_cfg_entry *cfg,
1977 struct device *dev = mmc_dev(cq_host->mmc);
1978 union cqhci_crypto_cap_entry cap;
1980 u8 bytes[AES_256_XTS_KEY_SIZE];
1981 u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)];
1986 if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE))
1987 return qcom_scm_ice_invalidate_key(slot);
1989 /* Only AES-256-XTS has been tested so far. */
1990 cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx];
1991 if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS ||
1992 cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256) {
1993 dev_err_ratelimited(dev,
1994 "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
1995 cap.algorithm_id, cap.key_size);
1999 memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE);
2002 * The SCM call byte-swaps the 32-bit words of the key. So we have to
2003 * do the same, in order for the final key be correct.
2005 for (i = 0; i < ARRAY_SIZE(key.words); i++)
2006 __cpu_to_be32s(&key.words[i]);
2008 err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE,
2009 QCOM_SCM_ICE_CIPHER_AES_256_XTS,
2010 cfg->data_unit_size);
2011 memzero_explicit(&key, sizeof(key));
2014 #else /* CONFIG_MMC_CRYPTO */
2015 static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev)
2020 static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
2021 struct cqhci_host *cq_host)
2026 static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
2030 static inline int __maybe_unused
2031 sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
2035 #endif /* !CONFIG_MMC_CRYPTO */
2037 /*****************************************************************************\
2039 * MSM Command Queue Engine (CQE) *
2041 \*****************************************************************************/
2043 static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
2048 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
2051 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
2055 static void sdhci_msm_cqe_enable(struct mmc_host *mmc)
2057 struct sdhci_host *host = mmc_priv(mmc);
2058 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2059 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2061 sdhci_cqe_enable(mmc);
2062 sdhci_msm_ice_enable(msm_host);
2065 static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
2067 struct sdhci_host *host = mmc_priv(mmc);
2068 unsigned long flags;
2072 * When CQE is halted, the legacy SDHCI path operates only
2073 * on 16-byte descriptors in 64bit mode.
2075 if (host->flags & SDHCI_USE_64_BIT_DMA)
2078 spin_lock_irqsave(&host->lock, flags);
2081 * During CQE command transfers, command complete bit gets latched.
2082 * So s/w should clear command complete interrupt status when CQE is
2083 * either halted or disabled. Otherwise unexpected SDCHI legacy
2084 * interrupt gets triggered when CQE is halted/disabled.
2086 ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
2087 ctrl |= SDHCI_INT_RESPONSE;
2088 sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
2089 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
2091 spin_unlock_irqrestore(&host->lock, flags);
2093 sdhci_cqe_disable(mmc, recovery);
2096 static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
2097 .enable = sdhci_msm_cqe_enable,
2098 .disable = sdhci_msm_cqe_disable,
2099 #ifdef CONFIG_MMC_CRYPTO
2100 .program_key = sdhci_msm_program_key,
2104 static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
2105 struct platform_device *pdev)
2107 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2108 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2109 struct cqhci_host *cq_host;
2115 * When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
2116 * So ensure ADMA table is allocated for 16byte descriptors.
2118 if (host->caps & SDHCI_CAN_64BIT)
2119 host->alloc_desc_sz = 16;
2121 ret = sdhci_setup_host(host);
2125 cq_host = cqhci_pltfm_init(pdev);
2126 if (IS_ERR(cq_host)) {
2127 ret = PTR_ERR(cq_host);
2128 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
2132 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2133 cq_host->ops = &sdhci_msm_cqhci_ops;
2135 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
2137 ret = sdhci_msm_ice_init(msm_host, cq_host);
2141 ret = cqhci_init(cq_host, host->mmc, dma64);
2143 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
2144 mmc_hostname(host->mmc), ret);
2148 /* Disable cqe reset due to cqe enable signal */
2149 cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
2150 cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
2151 cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);
2154 * SDHC expects 12byte ADMA descriptors till CQE is enabled.
2155 * So limit desc_sz to 12 so that the data commands that are sent
2156 * during card initialization (before CQE gets enabled) would
2157 * get executed without any issues.
2159 if (host->flags & SDHCI_USE_64_BIT_DMA)
2162 ret = __sdhci_add_host(host);
2166 dev_info(&pdev->dev, "%s: CQE init: success\n",
2167 mmc_hostname(host->mmc));
2171 sdhci_cleanup_host(host);
2176 * Platform specific register write functions. This is so that, if any
2177 * register write needs to be followed up by platform specific actions,
2178 * they can be added here. These functions can go to sleep when writes
2179 * to certain registers are done.
2180 * These functions are relying on sdhci_set_ios not using spinlock.
2182 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
2184 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2185 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2189 case SDHCI_HOST_CONTROL2:
2190 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
2193 case SDHCI_SOFTWARE_RESET:
2194 if (host->pwr && (val & SDHCI_RESET_ALL))
2195 req_type = REQ_BUS_OFF;
2197 case SDHCI_POWER_CONTROL:
2198 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
2200 case SDHCI_TRANSFER_MODE:
2201 msm_host->transfer_mode = val;
2204 if (!msm_host->use_cdr)
2206 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
2207 SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
2208 SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
2209 sdhci_msm_set_cdr(host, true);
2211 sdhci_msm_set_cdr(host, false);
2216 msm_host->pwr_irq_flag = 0;
2218 * Since this register write may trigger a power irq, ensure
2219 * all previous register writes are complete by this point.
2226 /* This function may sleep*/
2227 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
2231 req_type = __sdhci_msm_check_write(host, val, reg);
2232 writew_relaxed(val, host->ioaddr + reg);
2235 sdhci_msm_check_power_status(host, req_type);
2238 /* This function may sleep*/
2239 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
2243 req_type = __sdhci_msm_check_write(host, val, reg);
2245 writeb_relaxed(val, host->ioaddr + reg);
2248 sdhci_msm_check_power_status(host, req_type);
2251 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
2253 struct mmc_host *mmc = msm_host->mmc;
2254 struct regulator *supply = mmc->supply.vqmmc;
2255 u32 caps = 0, config;
2256 struct sdhci_host *host = mmc_priv(mmc);
2257 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2259 if (!IS_ERR(mmc->supply.vqmmc)) {
2260 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
2261 caps |= CORE_1_8V_SUPPORT;
2262 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
2263 caps |= CORE_3_0V_SUPPORT;
2266 pr_warn("%s: 1.8/3V not supported for vqmmc\n",
2272 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
2273 * bit can be used as required later on.
2275 u32 io_level = msm_host->curr_io_level;
2277 config = readl_relaxed(host->ioaddr +
2278 msm_offset->core_vendor_spec);
2279 config |= CORE_IO_PAD_PWR_SWITCH_EN;
2281 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
2282 config &= ~CORE_IO_PAD_PWR_SWITCH;
2283 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
2284 config |= CORE_IO_PAD_PWR_SWITCH;
2286 writel_relaxed(config,
2287 host->ioaddr + msm_offset->core_vendor_spec);
2289 msm_host->caps_0 |= caps;
2290 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
2293 static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
2295 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL))
2296 cqhci_deactivate(host->mmc);
2297 sdhci_reset(host, mask);
2300 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)
2304 ret = mmc_regulator_get_supply(msm_host->mmc);
2308 sdhci_msm_set_regulator_caps(msm_host);
2313 static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc,
2314 struct mmc_ios *ios)
2316 struct sdhci_host *host = mmc_priv(mmc);
2320 * Signal Voltage Switching is only applicable for Host Controllers
2323 if (host->version < SDHCI_SPEC_300)
2326 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2328 switch (ios->signal_voltage) {
2329 case MMC_SIGNAL_VOLTAGE_330:
2330 if (!(host->flags & SDHCI_SIGNALING_330))
2333 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2334 ctrl &= ~SDHCI_CTRL_VDD_180;
2336 case MMC_SIGNAL_VOLTAGE_180:
2337 if (!(host->flags & SDHCI_SIGNALING_180))
2340 /* Enable 1.8V Signal Enable in the Host Control2 register */
2341 ctrl |= SDHCI_CTRL_VDD_180;
2348 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2351 usleep_range(5000, 5500);
2353 /* regulator output should be stable within 5 ms */
2354 status = ctrl & SDHCI_CTRL_VDD_180;
2355 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2356 if ((ctrl & SDHCI_CTRL_VDD_180) == status)
2359 dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n",
2365 #define DRIVER_NAME "sdhci_msm"
2366 #define SDHCI_MSM_DUMP(f, x...) \
2367 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2369 static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
2371 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2372 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2373 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2375 SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n");
2378 "DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n",
2379 readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
2380 readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
2381 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
2383 "DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n",
2384 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
2385 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
2386 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
2388 "Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
2389 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
2390 readl_relaxed(host->ioaddr +
2391 msm_offset->core_vendor_spec_func2),
2392 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
2395 static const struct sdhci_msm_variant_ops mci_var_ops = {
2396 .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
2397 .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
2400 static const struct sdhci_msm_variant_ops v5_var_ops = {
2401 .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
2402 .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
2405 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
2406 .var_ops = &mci_var_ops,
2407 .offset = &sdhci_msm_mci_offset,
2410 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
2411 .mci_removed = true,
2412 .var_ops = &v5_var_ops,
2413 .offset = &sdhci_msm_v5_offset,
2416 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
2417 .mci_removed = true,
2418 .restore_dll_config = true,
2419 .var_ops = &v5_var_ops,
2420 .offset = &sdhci_msm_v5_offset,
2423 static const struct of_device_id sdhci_msm_dt_match[] = {
2424 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2425 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2426 {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2427 {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2431 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
2433 static const struct sdhci_ops sdhci_msm_ops = {
2434 .reset = sdhci_msm_reset,
2435 .set_clock = sdhci_msm_set_clock,
2436 .get_min_clock = sdhci_msm_get_min_clock,
2437 .get_max_clock = sdhci_msm_get_max_clock,
2438 .set_bus_width = sdhci_set_bus_width,
2439 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
2440 .write_w = sdhci_msm_writew,
2441 .write_b = sdhci_msm_writeb,
2442 .irq = sdhci_msm_cqe_irq,
2443 .dump_vendor_regs = sdhci_msm_dump_vendor_regs,
2444 .set_power = sdhci_set_power_noreg,
2447 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
2448 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
2449 SDHCI_QUIRK_SINGLE_POWER_WRITE |
2450 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
2451 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
2453 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
2454 .ops = &sdhci_msm_ops,
2457 static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
2458 struct sdhci_host *host)
2460 struct device_node *node = pdev->dev.of_node;
2461 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2462 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2464 if (of_property_read_u32(node, "qcom,ddr-config",
2465 &msm_host->ddr_config))
2466 msm_host->ddr_config = DDR_CONFIG_POR_VAL;
2468 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
2472 static int sdhci_msm_probe(struct platform_device *pdev)
2474 struct sdhci_host *host;
2475 struct sdhci_pltfm_host *pltfm_host;
2476 struct sdhci_msm_host *msm_host;
2479 u16 host_version, core_minor;
2480 u32 core_version, config;
2482 const struct sdhci_msm_offset *msm_offset;
2483 const struct sdhci_msm_variant_info *var_info;
2484 struct device_node *node = pdev->dev.of_node;
2486 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
2488 return PTR_ERR(host);
2490 host->sdma_boundary = 0;
2491 pltfm_host = sdhci_priv(host);
2492 msm_host = sdhci_pltfm_priv(pltfm_host);
2493 msm_host->mmc = host->mmc;
2494 msm_host->pdev = pdev;
2496 ret = mmc_of_parse(host->mmc);
2501 * Based on the compatible string, load the required msm host info from
2502 * the data associated with the version info.
2504 var_info = of_device_get_match_data(&pdev->dev);
2506 msm_host->mci_removed = var_info->mci_removed;
2507 msm_host->restore_dll_config = var_info->restore_dll_config;
2508 msm_host->var_ops = var_info->var_ops;
2509 msm_host->offset = var_info->offset;
2511 msm_offset = msm_host->offset;
2513 sdhci_get_of_property(pdev);
2514 sdhci_msm_get_of_property(pdev, host);
2516 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
2518 /* Setup SDCC bus voter clock. */
2519 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
2520 if (!IS_ERR(msm_host->bus_clk)) {
2521 /* Vote for max. clk rate for max. performance */
2522 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
2525 ret = clk_prepare_enable(msm_host->bus_clk);
2530 /* Setup main peripheral bus clock */
2531 clk = devm_clk_get(&pdev->dev, "iface");
2534 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
2535 goto bus_clk_disable;
2537 msm_host->bulk_clks[1].clk = clk;
2539 /* Setup SDC MMC clock */
2540 clk = devm_clk_get(&pdev->dev, "core");
2543 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
2544 goto bus_clk_disable;
2546 msm_host->bulk_clks[0].clk = clk;
2548 /* Check for optional interconnect paths */
2549 ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL);
2551 goto bus_clk_disable;
2553 ret = devm_pm_opp_set_clkname(&pdev->dev, "core");
2555 goto bus_clk_disable;
2557 /* OPP table is optional */
2558 ret = devm_pm_opp_of_add_table(&pdev->dev);
2559 if (ret && ret != -ENODEV) {
2560 dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
2561 goto bus_clk_disable;
2564 /* Vote for maximum clock rate for maximum performance */
2565 ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX);
2567 dev_warn(&pdev->dev, "core clock boost failed\n");
2569 clk = devm_clk_get(&pdev->dev, "cal");
2572 msm_host->bulk_clks[2].clk = clk;
2574 clk = devm_clk_get(&pdev->dev, "sleep");
2577 msm_host->bulk_clks[3].clk = clk;
2579 clk = sdhci_msm_ice_get_clk(&pdev->dev);
2582 msm_host->bulk_clks[4].clk = clk;
2584 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2585 msm_host->bulk_clks);
2587 goto bus_clk_disable;
2590 * xo clock is needed for FLL feature of cm_dll.
2591 * In case if xo clock is not mentioned in DT, warn and proceed.
2593 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
2594 if (IS_ERR(msm_host->xo_clk)) {
2595 ret = PTR_ERR(msm_host->xo_clk);
2596 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
2599 if (!msm_host->mci_removed) {
2600 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
2601 if (IS_ERR(msm_host->core_mem)) {
2602 ret = PTR_ERR(msm_host->core_mem);
2607 /* Reset the vendor spec register to power on reset state */
2608 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
2609 host->ioaddr + msm_offset->core_vendor_spec);
2611 if (!msm_host->mci_removed) {
2612 /* Set HC_MODE_EN bit in HC_MODE register */
2613 msm_host_writel(msm_host, HC_MODE_EN, host,
2614 msm_offset->core_hc_mode);
2615 config = msm_host_readl(msm_host, host,
2616 msm_offset->core_hc_mode);
2617 config |= FF_CLK_SW_RST_DIS;
2618 msm_host_writel(msm_host, config, host,
2619 msm_offset->core_hc_mode);
2622 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
2623 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
2624 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
2625 SDHCI_VENDOR_VER_SHIFT));
2627 core_version = msm_host_readl(msm_host, host,
2628 msm_offset->core_mci_version);
2629 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
2630 CORE_VERSION_MAJOR_SHIFT;
2631 core_minor = core_version & CORE_VERSION_MINOR_MASK;
2632 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
2633 core_version, core_major, core_minor);
2635 if (core_major == 1 && core_minor >= 0x42)
2636 msm_host->use_14lpp_dll_reset = true;
2639 * SDCC 5 controller with major version 1, minor version 0x34 and later
2640 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
2642 if (core_major == 1 && core_minor < 0x34)
2643 msm_host->use_cdclp533 = true;
2646 * Support for some capabilities is not advertised by newer
2647 * controller versions and must be explicitly enabled.
2649 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
2650 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
2651 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
2652 writel_relaxed(config, host->ioaddr +
2653 msm_offset->core_vendor_spec_capabilities0);
2656 if (core_major == 1 && core_minor >= 0x49)
2657 msm_host->updated_ddr_cfg = true;
2659 if (core_major == 1 && core_minor >= 0x71)
2660 msm_host->uses_tassadar_dll = true;
2662 ret = sdhci_msm_register_vreg(msm_host);
2667 * Power on reset state may trigger power irq if previous status of
2668 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
2669 * interrupt in GIC, any pending power irq interrupt should be
2670 * acknowledged. Otherwise power irq interrupt handler would be
2671 * fired prematurely.
2673 sdhci_msm_handle_pwr_irq(host, 0);
2676 * Ensure that above writes are propogated before interrupt enablement
2681 /* Setup IRQ for handling power/voltage tasks with PMIC */
2682 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
2683 if (msm_host->pwr_irq < 0) {
2684 ret = msm_host->pwr_irq;
2688 sdhci_msm_init_pwr_irq_wait(msm_host);
2689 /* Enable pwr irq interrupts */
2690 msm_host_writel(msm_host, INT_MASK, host,
2691 msm_offset->core_pwrctl_mask);
2693 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
2694 sdhci_msm_pwr_irq, IRQF_ONESHOT,
2695 dev_name(&pdev->dev), host);
2697 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
2701 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
2703 pm_runtime_get_noresume(&pdev->dev);
2704 pm_runtime_set_active(&pdev->dev);
2705 pm_runtime_enable(&pdev->dev);
2706 pm_runtime_set_autosuspend_delay(&pdev->dev,
2707 MSM_MMC_AUTOSUSPEND_DELAY_MS);
2708 pm_runtime_use_autosuspend(&pdev->dev);
2710 host->mmc_host_ops.start_signal_voltage_switch =
2711 sdhci_msm_start_signal_voltage_switch;
2712 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
2713 if (of_property_read_bool(node, "supports-cqe"))
2714 ret = sdhci_msm_cqe_add_host(host, pdev);
2716 ret = sdhci_add_host(host);
2718 goto pm_runtime_disable;
2720 pm_runtime_mark_last_busy(&pdev->dev);
2721 pm_runtime_put_autosuspend(&pdev->dev);
2726 pm_runtime_disable(&pdev->dev);
2727 pm_runtime_set_suspended(&pdev->dev);
2728 pm_runtime_put_noidle(&pdev->dev);
2730 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2731 msm_host->bulk_clks);
2733 if (!IS_ERR(msm_host->bus_clk))
2734 clk_disable_unprepare(msm_host->bus_clk);
2736 sdhci_pltfm_free(pdev);
2740 static int sdhci_msm_remove(struct platform_device *pdev)
2742 struct sdhci_host *host = platform_get_drvdata(pdev);
2743 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2744 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2745 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
2748 sdhci_remove_host(host, dead);
2750 pm_runtime_get_sync(&pdev->dev);
2751 pm_runtime_disable(&pdev->dev);
2752 pm_runtime_put_noidle(&pdev->dev);
2754 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2755 msm_host->bulk_clks);
2756 if (!IS_ERR(msm_host->bus_clk))
2757 clk_disable_unprepare(msm_host->bus_clk);
2758 sdhci_pltfm_free(pdev);
2762 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
2764 struct sdhci_host *host = dev_get_drvdata(dev);
2765 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2766 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2768 /* Drop the performance vote */
2769 dev_pm_opp_set_rate(dev, 0);
2770 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2771 msm_host->bulk_clks);
2776 static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
2778 struct sdhci_host *host = dev_get_drvdata(dev);
2779 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2780 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2783 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2784 msm_host->bulk_clks);
2788 * Whenever core-clock is gated dynamically, it's needed to
2789 * restore the SDR DLL settings when the clock is ungated.
2791 if (msm_host->restore_dll_config && msm_host->clk_rate) {
2792 ret = sdhci_msm_restore_sdr_dll_config(host);
2797 dev_pm_opp_set_rate(dev, msm_host->clk_rate);
2799 return sdhci_msm_ice_resume(msm_host);
2802 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2803 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2804 pm_runtime_force_resume)
2805 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2806 sdhci_msm_runtime_resume,
2810 static struct platform_driver sdhci_msm_driver = {
2811 .probe = sdhci_msm_probe,
2812 .remove = sdhci_msm_remove,
2814 .name = "sdhci_msm",
2815 .of_match_table = sdhci_msm_dt_match,
2816 .pm = &sdhci_msm_pm_ops,
2817 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2821 module_platform_driver(sdhci_msm_driver);
2823 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2824 MODULE_LICENSE("GPL v2");