drivers/mmc/host/sdhci-msm.c

   1 /*
   2  * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
   3  *
   4  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/of_device.h>
  19 #include <linux/delay.h>
  20 #include <linux/mmc/mmc.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/regulator/consumer.h>
  25
  26 #include "sdhci-pltfm.h"
  27
  28 #define CORE_MCI_VERSION                0x50
  29 #define CORE_VERSION_MAJOR_SHIFT        28
  30 #define CORE_VERSION_MAJOR_MASK         (0xf << CORE_VERSION_MAJOR_SHIFT)
  31 #define CORE_VERSION_MINOR_MASK         0xff
  32
  33 #define CORE_MCI_GENERICS               0x70
  34 #define SWITCHABLE_SIGNALING_VOLTAGE    BIT(29)
  35
  36 #define HC_MODE_EN              0x1
  37 #define CORE_POWER              0x0
  38 #define CORE_SW_RST             BIT(7)
  39 #define FF_CLK_SW_RST_DIS       BIT(13)
  40
  41 #define CORE_PWRCTL_BUS_OFF     BIT(0)
  42 #define CORE_PWRCTL_BUS_ON      BIT(1)
  43 #define CORE_PWRCTL_IO_LOW      BIT(2)
  44 #define CORE_PWRCTL_IO_HIGH     BIT(3)
  45 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
  46 #define CORE_PWRCTL_IO_SUCCESS  BIT(2)
  47 #define REQ_BUS_OFF             BIT(0)
  48 #define REQ_BUS_ON              BIT(1)
  49 #define REQ_IO_LOW              BIT(2)
  50 #define REQ_IO_HIGH             BIT(3)
  51 #define INT_MASK                0xf
  52 #define MAX_PHASES              16
  53 #define CORE_DLL_LOCK           BIT(7)
  54 #define CORE_DDR_DLL_LOCK       BIT(11)
  55 #define CORE_DLL_EN             BIT(16)
  56 #define CORE_CDR_EN             BIT(17)
  57 #define CORE_CK_OUT_EN          BIT(18)
  58 #define CORE_CDR_EXT_EN         BIT(19)
  59 #define CORE_DLL_PDN            BIT(29)
  60 #define CORE_DLL_RST            BIT(30)
  61 #define CORE_CMD_DAT_TRACK_SEL  BIT(0)
  62
  63 #define CORE_DDR_CAL_EN         BIT(0)
  64 #define CORE_FLL_CYCLE_CNT      BIT(18)
  65 #define CORE_DLL_CLOCK_DISABLE  BIT(21)
  66
  67 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
  68 #define CORE_CLK_PWRSAVE        BIT(1)
  69 #define CORE_HC_MCLK_SEL_DFLT   (2 << 8)
  70 #define CORE_HC_MCLK_SEL_HS400  (3 << 8)
  71 #define CORE_HC_MCLK_SEL_MASK   (3 << 8)
  72 #define CORE_IO_PAD_PWR_SWITCH_EN       (1 << 15)
  73 #define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
  74 #define CORE_HC_SELECT_IN_EN    BIT(18)
  75 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
  76 #define CORE_HC_SELECT_IN_MASK  (7 << 19)
  77
  78 #define CORE_3_0V_SUPPORT       (1 << 25)
  79 #define CORE_1_8V_SUPPORT       (1 << 26)
  80 #define CORE_VOLT_SUPPORT       (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
  81
  82 #define CORE_CSR_CDC_CTLR_CFG0          0x130
  83 #define CORE_SW_TRIG_FULL_CALIB         BIT(16)
  84 #define CORE_HW_AUTOCAL_ENA             BIT(17)
  85
  86 #define CORE_CSR_CDC_CTLR_CFG1          0x134
  87 #define CORE_CSR_CDC_CAL_TIMER_CFG0     0x138
  88 #define CORE_TIMER_ENA                  BIT(16)
  89
  90 #define CORE_CSR_CDC_CAL_TIMER_CFG1     0x13C
  91 #define CORE_CSR_CDC_REFCOUNT_CFG       0x140
  92 #define CORE_CSR_CDC_COARSE_CAL_CFG     0x144
  93 #define CORE_CDC_OFFSET_CFG             0x14C
  94 #define CORE_CSR_CDC_DELAY_CFG          0x150
  95 #define CORE_CDC_SLAVE_DDA_CFG          0x160
  96 #define CORE_CSR_CDC_STATUS0            0x164
  97 #define CORE_CALIBRATION_DONE           BIT(0)
  98
  99 #define CORE_CDC_ERROR_CODE_MASK        0x7000000
 100
 101 #define CORE_CSR_CDC_GEN_CFG            0x178
 102 #define CORE_CDC_SWITCH_BYPASS_OFF      BIT(0)
 103 #define CORE_CDC_SWITCH_RC_EN           BIT(1)
 104
 105 #define CORE_CDC_T4_DLY_SEL             BIT(0)
 106 #define CORE_CMDIN_RCLK_EN              BIT(1)
 107 #define CORE_START_CDC_TRAFFIC          BIT(6)
 108
 109 #define CORE_PWRSAVE_DLL        BIT(3)
 110
 111 #define DDR_CONFIG_POR_VAL      0x80040853
 112
 113
 114 #define INVALID_TUNING_PHASE    -1
 115 #define SDHCI_MSM_MIN_CLOCK     400000
 116 #define CORE_FREQ_100MHZ        (100 * 1000 * 1000)
 117
 118 #define CDR_SELEXT_SHIFT        20
 119 #define CDR_SELEXT_MASK         (0xf << CDR_SELEXT_SHIFT)
 120 #define CMUX_SHIFT_PHASE_SHIFT  24
 121 #define CMUX_SHIFT_PHASE_MASK   (7 << CMUX_SHIFT_PHASE_SHIFT)
 122
 123 #define MSM_MMC_AUTOSUSPEND_DELAY_MS    50
 124
 125 /* Timeout value to avoid infinite waiting for pwr_irq */
 126 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
 127
 128 #define msm_host_readl(msm_host, host, offset) \
 129         msm_host->var_ops->msm_readl_relaxed(host, offset)
 130
 131 #define msm_host_writel(msm_host, val, host, offset) \
 132         msm_host->var_ops->msm_writel_relaxed(val, host, offset)
 133
 134 struct sdhci_msm_offset {
 135         u32 core_hc_mode;
 136         u32 core_mci_data_cnt;
 137         u32 core_mci_status;
 138         u32 core_mci_fifo_cnt;
 139         u32 core_mci_version;
 140         u32 core_generics;
 141         u32 core_testbus_config;
 142         u32 core_testbus_sel2_bit;
 143         u32 core_testbus_ena;
 144         u32 core_testbus_sel2;
 145         u32 core_pwrctl_status;
 146         u32 core_pwrctl_mask;
 147         u32 core_pwrctl_clear;
 148         u32 core_pwrctl_ctl;
 149         u32 core_sdcc_debug_reg;
 150         u32 core_dll_config;
 151         u32 core_dll_status;
 152         u32 core_vendor_spec;
 153         u32 core_vendor_spec_adma_err_addr0;
 154         u32 core_vendor_spec_adma_err_addr1;
 155         u32 core_vendor_spec_func2;
 156         u32 core_vendor_spec_capabilities0;
 157         u32 core_ddr_200_cfg;
 158         u32 core_vendor_spec3;
 159         u32 core_dll_config_2;
 160         u32 core_ddr_config;
 161         u32 core_ddr_config_2;
 162 };
 163
 164 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
 165         .core_mci_data_cnt = 0x35c,
 166         .core_mci_status = 0x324,
 167         .core_mci_fifo_cnt = 0x308,
 168         .core_mci_version = 0x318,
 169         .core_generics = 0x320,
 170         .core_testbus_config = 0x32c,
 171         .core_testbus_sel2_bit = 3,
 172         .core_testbus_ena = (1 << 31),
 173         .core_testbus_sel2 = (1 << 3),
 174         .core_pwrctl_status = 0x240,
 175         .core_pwrctl_mask = 0x244,
 176         .core_pwrctl_clear = 0x248,
 177         .core_pwrctl_ctl = 0x24c,
 178         .core_sdcc_debug_reg = 0x358,
 179         .core_dll_config = 0x200,
 180         .core_dll_status = 0x208,
 181         .core_vendor_spec = 0x20c,
 182         .core_vendor_spec_adma_err_addr0 = 0x214,
 183         .core_vendor_spec_adma_err_addr1 = 0x218,
 184         .core_vendor_spec_func2 = 0x210,
 185         .core_vendor_spec_capabilities0 = 0x21c,
 186         .core_ddr_200_cfg = 0x224,
 187         .core_vendor_spec3 = 0x250,
 188         .core_dll_config_2 = 0x254,
 189         .core_ddr_config = 0x258,
 190         .core_ddr_config_2 = 0x25c,
 191 };
 192
 193 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
 194         .core_hc_mode = 0x78,
 195         .core_mci_data_cnt = 0x30,
 196         .core_mci_status = 0x34,
 197         .core_mci_fifo_cnt = 0x44,
 198         .core_mci_version = 0x050,
 199         .core_generics = 0x70,
 200         .core_testbus_config = 0x0cc,
 201         .core_testbus_sel2_bit = 4,
 202         .core_testbus_ena = (1 << 3),
 203         .core_testbus_sel2 = (1 << 4),
 204         .core_pwrctl_status = 0xdc,
 205         .core_pwrctl_mask = 0xe0,
 206         .core_pwrctl_clear = 0xe4,
 207         .core_pwrctl_ctl = 0xe8,
 208         .core_sdcc_debug_reg = 0x124,
 209         .core_dll_config = 0x100,
 210         .core_dll_status = 0x108,
 211         .core_vendor_spec = 0x10c,
 212         .core_vendor_spec_adma_err_addr0 = 0x114,
 213         .core_vendor_spec_adma_err_addr1 = 0x118,
 214         .core_vendor_spec_func2 = 0x110,
 215         .core_vendor_spec_capabilities0 = 0x11c,
 216         .core_ddr_200_cfg = 0x184,
 217         .core_vendor_spec3 = 0x1b0,
 218         .core_dll_config_2 = 0x1b4,
 219         .core_ddr_config = 0x1b8,
 220         .core_ddr_config_2 = 0x1bc,
 221 };
 222
 223 struct sdhci_msm_variant_ops {
 224         u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
 225         void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
 226                         u32 offset);
 227 };
 228
 229 /*
 230  * From V5, register spaces have changed. Wrap this info in a structure
 231  * and choose the data_structure based on version info mentioned in DT.
 232  */
 233 struct sdhci_msm_variant_info {
 234         bool mci_removed;
 235         bool restore_dll_config;
 236         const struct sdhci_msm_variant_ops *var_ops;
 237         const struct sdhci_msm_offset *offset;
 238 };
 239
 240 struct sdhci_msm_host {
 241         struct platform_device *pdev;
 242         void __iomem *core_mem; /* MSM SDCC mapped address */
 243         int pwr_irq;            /* power irq */
 244         struct clk *bus_clk;    /* SDHC bus voter clock */
 245         struct clk *xo_clk;     /* TCXO clk needed for FLL feature of cm_dll*/
 246         struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
 247         unsigned long clk_rate;
 248         struct mmc_host *mmc;
 249         bool use_14lpp_dll_reset;
 250         bool tuning_done;
 251         bool calibration_done;
 252         u8 saved_tuning_phase;
 253         bool use_cdclp533;
 254         u32 curr_pwr_state;
 255         u32 curr_io_level;
 256         wait_queue_head_t pwr_irq_wait;
 257         bool pwr_irq_flag;
 258         u32 caps_0;
 259         bool mci_removed;
 260         bool restore_dll_config;
 261         const struct sdhci_msm_variant_ops *var_ops;
 262         const struct sdhci_msm_offset *offset;
 263         bool use_cdr;
 264         u32 transfer_mode;
 265 };
 266
 267 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
 268 {
 269         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 270         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 271
 272         return msm_host->offset;
 273 }
 274
 275 /*
 276  * APIs to read/write to vendor specific registers which were there in the
 277  * core_mem region before MCI was removed.
 278  */
 279 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
 280                 u32 offset)
 281 {
 282         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 283         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 284
 285         return readl_relaxed(msm_host->core_mem + offset);
 286 }
 287
 288 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
 289                 u32 offset)
 290 {
 291         return readl_relaxed(host->ioaddr + offset);
 292 }
 293
 294 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
 295                 struct sdhci_host *host, u32 offset)
 296 {
 297         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 298         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 299
 300         writel_relaxed(val, msm_host->core_mem + offset);
 301 }
 302
 303 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
 304                 struct sdhci_host *host, u32 offset)
 305 {
 306         writel_relaxed(val, host->ioaddr + offset);
 307 }
 308
 309 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
 310                                                     unsigned int clock)
 311 {
 312         struct mmc_ios ios = host->mmc->ios;
 313         /*
 314          * The SDHC requires internal clock frequency to be double the
 315          * actual clock that will be set for DDR mode. The controller
 316          * uses the faster clock(100/400MHz) for some of its parts and
 317          * send the actual required clock (50/200MHz) to the card.
 318          */
 319         if (ios.timing == MMC_TIMING_UHS_DDR50 ||
 320             ios.timing == MMC_TIMING_MMC_DDR52 ||
 321             ios.timing == MMC_TIMING_MMC_HS400 ||
 322             host->flags & SDHCI_HS400_TUNING)
 323                 clock *= 2;
 324         return clock;
 325 }
 326
 327 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
 328                                             unsigned int clock)
 329 {
 330         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 331         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 332         struct mmc_ios curr_ios = host->mmc->ios;
 333         struct clk *core_clk = msm_host->bulk_clks[0].clk;
 334         int rc;
 335
 336         clock = msm_get_clock_rate_for_bus_mode(host, clock);
 337         rc = clk_set_rate(core_clk, clock);
 338         if (rc) {
 339                 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
 340                        mmc_hostname(host->mmc), clock,
 341                        curr_ios.timing);
 342                 return;
 343         }
 344         msm_host->clk_rate = clock;
 345         pr_debug("%s: Setting clock at rate %lu at timing %d\n",
 346                  mmc_hostname(host->mmc), clk_get_rate(core_clk),
 347                  curr_ios.timing);
 348 }
 349
 350 /* Platform specific tuning */
 351 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
 352 {
 353         u32 wait_cnt = 50;
 354         u8 ck_out_en;
 355         struct mmc_host *mmc = host->mmc;
 356         const struct sdhci_msm_offset *msm_offset =
 357                                         sdhci_priv_msm_offset(host);
 358
 359         /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
 360         ck_out_en = !!(readl_relaxed(host->ioaddr +
 361                         msm_offset->core_dll_config) & CORE_CK_OUT_EN);
 362
 363         while (ck_out_en != poll) {
 364                 if (--wait_cnt == 0) {
 365                         dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
 366                                mmc_hostname(mmc), poll);
 367                         return -ETIMEDOUT;
 368                 }
 369                 udelay(1);
 370
 371                 ck_out_en = !!(readl_relaxed(host->ioaddr +
 372                         msm_offset->core_dll_config) & CORE_CK_OUT_EN);
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 379 {
 380         int rc;
 381         static const u8 grey_coded_phase_table[] = {
 382                 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
 383                 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
 384         };
 385         unsigned long flags;
 386         u32 config;
 387         struct mmc_host *mmc = host->mmc;
 388         const struct sdhci_msm_offset *msm_offset =
 389                                         sdhci_priv_msm_offset(host);
 390
 391         if (phase > 0xf)
 392                 return -EINVAL;
 393
 394         spin_lock_irqsave(&host->lock, flags);
 395
 396         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 397         config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
 398         config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
 399         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 400
 401         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
 402         rc = msm_dll_poll_ck_out_en(host, 0);
 403         if (rc)
 404                 goto err_out;
 405
 406         /*
 407          * Write the selected DLL clock output phase (0 ... 15)
 408          * to CDR_SELEXT bit field of DLL_CONFIG register.
 409          */
 410         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 411         config &= ~CDR_SELEXT_MASK;
 412         config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
 413         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 414
 415         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 416         config |= CORE_CK_OUT_EN;
 417         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 418
 419         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
 420         rc = msm_dll_poll_ck_out_en(host, 1);
 421         if (rc)
 422                 goto err_out;
 423
 424         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 425         config |= CORE_CDR_EN;
 426         config &= ~CORE_CDR_EXT_EN;
 427         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 428         goto out;
 429
 430 err_out:
 431         dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
 432                mmc_hostname(mmc), phase);
 433 out:
 434         spin_unlock_irqrestore(&host->lock, flags);
 435         return rc;
 436 }
 437
 438 /*
 439  * Find out the greatest range of consecuitive selected
 440  * DLL clock output phases that can be used as sampling
 441  * setting for SD3.0 UHS-I card read operation (in SDR104
 442  * timing mode) or for eMMC4.5 card read operation (in
 443  * HS400/HS200 timing mode).
 444  * Select the 3/4 of the range and configure the DLL with the
 445  * selected DLL clock output phase.
 446  */
 447
 448 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
 449                                            u8 *phase_table, u8 total_phases)
 450 {
 451         int ret;
 452         u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
 453         u8 phases_per_row[MAX_PHASES] = { 0 };
 454         int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
 455         int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
 456         bool phase_0_found = false, phase_15_found = false;
 457         struct mmc_host *mmc = host->mmc;
 458
 459         if (!total_phases || (total_phases > MAX_PHASES)) {
 460                 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
 461                        mmc_hostname(mmc), total_phases);
 462                 return -EINVAL;
 463         }
 464
 465         for (cnt = 0; cnt < total_phases; cnt++) {
 466                 ranges[row_index][col_index] = phase_table[cnt];
 467                 phases_per_row[row_index] += 1;
 468                 col_index++;
 469
 470                 if ((cnt + 1) == total_phases) {
 471                         continue;
 472                 /* check if next phase in phase_table is consecutive or not */
 473                 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
 474                         row_index++;
 475                         col_index = 0;
 476                 }
 477         }
 478
 479         if (row_index >= MAX_PHASES)
 480                 return -EINVAL;
 481
 482         /* Check if phase-0 is present in first valid window? */
 483         if (!ranges[0][0]) {
 484                 phase_0_found = true;
 485                 phase_0_raw_index = 0;
 486                 /* Check if cycle exist between 2 valid windows */
 487                 for (cnt = 1; cnt <= row_index; cnt++) {
 488                         if (phases_per_row[cnt]) {
 489                                 for (i = 0; i < phases_per_row[cnt]; i++) {
 490                                         if (ranges[cnt][i] == 15) {
 491                                                 phase_15_found = true;
 492                                                 phase_15_raw_index = cnt;
 493                                                 break;
 494                                         }
 495                                 }
 496                         }
 497                 }
 498         }
 499
 500         /* If 2 valid windows form cycle then merge them as single window */
 501         if (phase_0_found && phase_15_found) {
 502                 /* number of phases in raw where phase 0 is present */
 503                 u8 phases_0 = phases_per_row[phase_0_raw_index];
 504                 /* number of phases in raw where phase 15 is present */
 505                 u8 phases_15 = phases_per_row[phase_15_raw_index];
 506
 507                 if (phases_0 + phases_15 >= MAX_PHASES)
 508                         /*
 509                          * If there are more than 1 phase windows then total
 510                          * number of phases in both the windows should not be
 511                          * more than or equal to MAX_PHASES.
 512                          */
 513                         return -EINVAL;
 514
 515                 /* Merge 2 cyclic windows */
 516                 i = phases_15;
 517                 for (cnt = 0; cnt < phases_0; cnt++) {
 518                         ranges[phase_15_raw_index][i] =
 519                             ranges[phase_0_raw_index][cnt];
 520                         if (++i >= MAX_PHASES)
 521                                 break;
 522                 }
 523
 524                 phases_per_row[phase_0_raw_index] = 0;
 525                 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
 526         }
 527
 528         for (cnt = 0; cnt <= row_index; cnt++) {
 529                 if (phases_per_row[cnt] > curr_max) {
 530                         curr_max = phases_per_row[cnt];
 531                         selected_row_index = cnt;
 532                 }
 533         }
 534
 535         i = (curr_max * 3) / 4;
 536         if (i)
 537                 i--;
 538
 539         ret = ranges[selected_row_index][i];
 540
 541         if (ret >= MAX_PHASES) {
 542                 ret = -EINVAL;
 543                 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
 544                        mmc_hostname(mmc), ret);
 545         }
 546
 547         return ret;
 548 }
 549
 550 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
 551 {
 552         u32 mclk_freq = 0, config;
 553         const struct sdhci_msm_offset *msm_offset =
 554                                         sdhci_priv_msm_offset(host);
 555
 556         /* Program the MCLK value to MCLK_FREQ bit field */
 557         if (host->clock <= 112000000)
 558                 mclk_freq = 0;
 559         else if (host->clock <= 125000000)
 560                 mclk_freq = 1;
 561         else if (host->clock <= 137000000)
 562                 mclk_freq = 2;
 563         else if (host->clock <= 150000000)
 564                 mclk_freq = 3;
 565         else if (host->clock <= 162000000)
 566                 mclk_freq = 4;
 567         else if (host->clock <= 175000000)
 568                 mclk_freq = 5;
 569         else if (host->clock <= 187000000)
 570                 mclk_freq = 6;
 571         else if (host->clock <= 200000000)
 572                 mclk_freq = 7;
 573
 574         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 575         config &= ~CMUX_SHIFT_PHASE_MASK;
 576         config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
 577         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 578 }
 579
 580 /* Initialize the DLL (Programmable Delay Line) */
 581 static int msm_init_cm_dll(struct sdhci_host *host)
 582 {
 583         struct mmc_host *mmc = host->mmc;
 584         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 585         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 586         int wait_cnt = 50;
 587         unsigned long flags;
 588         u32 config;
 589         const struct sdhci_msm_offset *msm_offset =
 590                                         msm_host->offset;
 591
 592         spin_lock_irqsave(&host->lock, flags);
 593
 594         /*
 595          * Make sure that clock is always enabled when DLL
 596          * tuning is in progress. Keeping PWRSAVE ON may
 597          * turn off the clock.
 598          */
 599         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 600         config &= ~CORE_CLK_PWRSAVE;
 601         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 602
 603         if (msm_host->use_14lpp_dll_reset) {
 604                 config = readl_relaxed(host->ioaddr +
 605                                 msm_offset->core_dll_config);
 606                 config &= ~CORE_CK_OUT_EN;
 607                 writel_relaxed(config, host->ioaddr +
 608                                 msm_offset->core_dll_config);
 609
 610                 config = readl_relaxed(host->ioaddr +
 611                                 msm_offset->core_dll_config_2);
 612                 config |= CORE_DLL_CLOCK_DISABLE;
 613                 writel_relaxed(config, host->ioaddr +
 614                                 msm_offset->core_dll_config_2);
 615         }
 616
 617         config = readl_relaxed(host->ioaddr +
 618                         msm_offset->core_dll_config);
 619         config |= CORE_DLL_RST;
 620         writel_relaxed(config, host->ioaddr +
 621                         msm_offset->core_dll_config);
 622
 623         config = readl_relaxed(host->ioaddr +
 624                         msm_offset->core_dll_config);
 625         config |= CORE_DLL_PDN;
 626         writel_relaxed(config, host->ioaddr +
 627                         msm_offset->core_dll_config);
 628         msm_cm_dll_set_freq(host);
 629
 630         if (msm_host->use_14lpp_dll_reset &&
 631             !IS_ERR_OR_NULL(msm_host->xo_clk)) {
 632                 u32 mclk_freq = 0;
 633
 634                 config = readl_relaxed(host->ioaddr +
 635                                 msm_offset->core_dll_config_2);
 636                 config &= CORE_FLL_CYCLE_CNT;
 637                 if (config)
 638                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
 639                                         clk_get_rate(msm_host->xo_clk));
 640                 else
 641                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
 642                                         clk_get_rate(msm_host->xo_clk));
 643
 644                 config = readl_relaxed(host->ioaddr +
 645                                 msm_offset->core_dll_config_2);
 646                 config &= ~(0xFF << 10);
 647                 config |= mclk_freq << 10;
 648
 649                 writel_relaxed(config, host->ioaddr +
 650                                 msm_offset->core_dll_config_2);
 651                 /* wait for 5us before enabling DLL clock */
 652                 udelay(5);
 653         }
 654
 655         config = readl_relaxed(host->ioaddr +
 656                         msm_offset->core_dll_config);
 657         config &= ~CORE_DLL_RST;
 658         writel_relaxed(config, host->ioaddr +
 659                         msm_offset->core_dll_config);
 660
 661         config = readl_relaxed(host->ioaddr +
 662                         msm_offset->core_dll_config);
 663         config &= ~CORE_DLL_PDN;
 664         writel_relaxed(config, host->ioaddr +
 665                         msm_offset->core_dll_config);
 666
 667         if (msm_host->use_14lpp_dll_reset) {
 668                 msm_cm_dll_set_freq(host);
 669                 config = readl_relaxed(host->ioaddr +
 670                                 msm_offset->core_dll_config_2);
 671                 config &= ~CORE_DLL_CLOCK_DISABLE;
 672                 writel_relaxed(config, host->ioaddr +
 673                                 msm_offset->core_dll_config_2);
 674         }
 675
 676         config = readl_relaxed(host->ioaddr +
 677                         msm_offset->core_dll_config);
 678         config |= CORE_DLL_EN;
 679         writel_relaxed(config, host->ioaddr +
 680                         msm_offset->core_dll_config);
 681
 682         config = readl_relaxed(host->ioaddr +
 683                         msm_offset->core_dll_config);
 684         config |= CORE_CK_OUT_EN;
 685         writel_relaxed(config, host->ioaddr +
 686                         msm_offset->core_dll_config);
 687
 688         /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
 689         while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
 690                  CORE_DLL_LOCK)) {
 691                 /* max. wait for 50us sec for LOCK bit to be set */
 692                 if (--wait_cnt == 0) {
 693                         dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
 694                                mmc_hostname(mmc));
 695                         spin_unlock_irqrestore(&host->lock, flags);
 696                         return -ETIMEDOUT;
 697                 }
 698                 udelay(1);
 699         }
 700
 701         spin_unlock_irqrestore(&host->lock, flags);
 702         return 0;
 703 }
 704
 705 static void msm_hc_select_default(struct sdhci_host *host)
 706 {
 707         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 708         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 709         u32 config;
 710         const struct sdhci_msm_offset *msm_offset =
 711                                         msm_host->offset;
 712
 713         if (!msm_host->use_cdclp533) {
 714                 config = readl_relaxed(host->ioaddr +
 715                                 msm_offset->core_vendor_spec3);
 716                 config &= ~CORE_PWRSAVE_DLL;
 717                 writel_relaxed(config, host->ioaddr +
 718                                 msm_offset->core_vendor_spec3);
 719         }
 720
 721         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 722         config &= ~CORE_HC_MCLK_SEL_MASK;
 723         config |= CORE_HC_MCLK_SEL_DFLT;
 724         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 725
 726         /*
 727          * Disable HC_SELECT_IN to be able to use the UHS mode select
 728          * configuration from Host Control2 register for all other
 729          * modes.
 730          * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
 731          * in VENDOR_SPEC_FUNC
 732          */
 733         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 734         config &= ~CORE_HC_SELECT_IN_EN;
 735         config &= ~CORE_HC_SELECT_IN_MASK;
 736         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 737
 738         /*
 739          * Make sure above writes impacting free running MCLK are completed
 740          * before changing the clk_rate at GCC.
 741          */
 742         wmb();
 743 }
 744
 745 static void msm_hc_select_hs400(struct sdhci_host *host)
 746 {
 747         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 748         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 749         struct mmc_ios ios = host->mmc->ios;
 750         u32 config, dll_lock;
 751         int rc;
 752         const struct sdhci_msm_offset *msm_offset =
 753                                         msm_host->offset;
 754
 755         /* Select the divided clock (free running MCLK/2) */
 756         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 757         config &= ~CORE_HC_MCLK_SEL_MASK;
 758         config |= CORE_HC_MCLK_SEL_HS400;
 759
 760         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 761         /*
 762          * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
 763          * register
 764          */
 765         if ((msm_host->tuning_done || ios.enhanced_strobe) &&
 766             !msm_host->calibration_done) {
 767                 config = readl_relaxed(host->ioaddr +
 768                                 msm_offset->core_vendor_spec);
 769                 config |= CORE_HC_SELECT_IN_HS400;
 770                 config |= CORE_HC_SELECT_IN_EN;
 771                 writel_relaxed(config, host->ioaddr +
 772                                 msm_offset->core_vendor_spec);
 773         }
 774         if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
 775                 /*
 776                  * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
 777                  * core_dll_status to be set. This should get set
 778                  * within 15 us at 200 MHz.
 779                  */
 780                 rc = readl_relaxed_poll_timeout(host->ioaddr +
 781                                                 msm_offset->core_dll_status,
 782                                                 dll_lock,
 783                                                 (dll_lock &
 784                                                 (CORE_DLL_LOCK |
 785                                                 CORE_DDR_DLL_LOCK)), 10,
 786                                                 1000);
 787                 if (rc == -ETIMEDOUT)
 788                         pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
 789                                mmc_hostname(host->mmc), dll_lock);
 790         }
 791         /*
 792          * Make sure above writes impacting free running MCLK are completed
 793          * before changing the clk_rate at GCC.
 794          */
 795         wmb();
 796 }
 797
 798 /*
 799  * sdhci_msm_hc_select_mode :- In general all timing modes are
 800  * controlled via UHS mode select in Host Control2 register.
 801  * eMMC specific HS200/HS400 doesn't have their respective modes
 802  * defined here, hence we use these values.
 803  *
 804  * HS200 - SDR104 (Since they both are equivalent in functionality)
 805  * HS400 - This involves multiple configurations
 806  *              Initially SDR104 - when tuning is required as HS200
 807  *              Then when switching to DDR @ 400MHz (HS400) we use
 808  *              the vendor specific HC_SELECT_IN to control the mode.
 809  *
 810  * In addition to controlling the modes we also need to select the
 811  * correct input clock for DLL depending on the mode.
 812  *
 813  * HS400 - divided clock (free running MCLK/2)
 814  * All other modes - default (free running MCLK)
 815  */
 816 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
 817 {
 818         struct mmc_ios ios = host->mmc->ios;
 819
 820         if (ios.timing == MMC_TIMING_MMC_HS400 ||
 821             host->flags & SDHCI_HS400_TUNING)
 822                 msm_hc_select_hs400(host);
 823         else
 824                 msm_hc_select_default(host);
 825 }
 826
 827 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
 828 {
 829         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 830         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 831         u32 config, calib_done;
 832         int ret;
 833         const struct sdhci_msm_offset *msm_offset =
 834                                         msm_host->offset;
 835
 836         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 837
 838         /*
 839          * Retuning in HS400 (DDR mode) will fail, just reset the
 840          * tuning block and restore the saved tuning phase.
 841          */
 842         ret = msm_init_cm_dll(host);
 843         if (ret)
 844                 goto out;
 845
 846         /* Set the selected phase in delay line hw block */
 847         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
 848         if (ret)
 849                 goto out;
 850
 851         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 852         config |= CORE_CMD_DAT_TRACK_SEL;
 853         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 854
 855         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 856         config &= ~CORE_CDC_T4_DLY_SEL;
 857         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 858
 859         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 860         config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
 861         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 862
 863         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 864         config |= CORE_CDC_SWITCH_RC_EN;
 865         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 866
 867         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 868         config &= ~CORE_START_CDC_TRAFFIC;
 869         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 870
 871         /* Perform CDC Register Initialization Sequence */
 872
 873         writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 874         writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
 875         writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 876         writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
 877         writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
 878         writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
 879         writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
 880         writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
 881         writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
 882
 883         /* CDC HW Calibration */
 884
 885         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 886         config |= CORE_SW_TRIG_FULL_CALIB;
 887         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 888
 889         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 890         config &= ~CORE_SW_TRIG_FULL_CALIB;
 891         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 892
 893         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 894         config |= CORE_HW_AUTOCAL_ENA;
 895         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 896
 897         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 898         config |= CORE_TIMER_ENA;
 899         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 900
 901         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
 902                                          calib_done,
 903                                          (calib_done & CORE_CALIBRATION_DONE),
 904                                          1, 50);
 905
 906         if (ret == -ETIMEDOUT) {
 907                 pr_err("%s: %s: CDC calibration was not completed\n",
 908                        mmc_hostname(host->mmc), __func__);
 909                 goto out;
 910         }
 911
 912         ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
 913                         & CORE_CDC_ERROR_CODE_MASK;
 914         if (ret) {
 915                 pr_err("%s: %s: CDC error code %d\n",
 916                        mmc_hostname(host->mmc), __func__, ret);
 917                 ret = -EINVAL;
 918                 goto out;
 919         }
 920
 921         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 922         config |= CORE_START_CDC_TRAFFIC;
 923         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 924 out:
 925         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 926                  __func__, ret);
 927         return ret;
 928 }
 929
 930 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
 931 {
 932         struct mmc_host *mmc = host->mmc;
 933         u32 dll_status, config;
 934         int ret;
 935         const struct sdhci_msm_offset *msm_offset =
 936                                         sdhci_priv_msm_offset(host);
 937
 938         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 939
 940         /*
 941          * Currently the core_ddr_config register defaults to desired
 942          * configuration on reset. Currently reprogramming the power on
 943          * reset (POR) value in case it might have been modified by
 944          * bootloaders. In the future, if this changes, then the desired
 945          * values will need to be programmed appropriately.
 946          */
 947         writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr +
 948                         msm_offset->core_ddr_config);
 949
 950         if (mmc->ios.enhanced_strobe) {
 951                 config = readl_relaxed(host->ioaddr +
 952                                 msm_offset->core_ddr_200_cfg);
 953                 config |= CORE_CMDIN_RCLK_EN;
 954                 writel_relaxed(config, host->ioaddr +
 955                                 msm_offset->core_ddr_200_cfg);
 956         }
 957
 958         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
 959         config |= CORE_DDR_CAL_EN;
 960         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
 961
 962         ret = readl_relaxed_poll_timeout(host->ioaddr +
 963                                         msm_offset->core_dll_status,
 964                                         dll_status,
 965                                         (dll_status & CORE_DDR_DLL_LOCK),
 966                                         10, 1000);
 967
 968         if (ret == -ETIMEDOUT) {
 969                 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
 970                        mmc_hostname(host->mmc), __func__);
 971                 goto out;
 972         }
 973
 974         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);
 975         config |= CORE_PWRSAVE_DLL;
 976         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);
 977
 978         /*
 979          * Drain writebuffer to ensure above DLL calibration
 980          * and PWRSAVE DLL is enabled.
 981          */
 982         wmb();
 983 out:
 984         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 985                  __func__, ret);
 986         return ret;
 987 }
 988
 989 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
 990 {
 991         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 992         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 993         struct mmc_host *mmc = host->mmc;
 994         int ret;
 995         u32 config;
 996         const struct sdhci_msm_offset *msm_offset =
 997                                         msm_host->offset;
 998
 999         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1000
1001         /*
1002          * Retuning in HS400 (DDR mode) will fail, just reset the
1003          * tuning block and restore the saved tuning phase.
1004          */
1005         ret = msm_init_cm_dll(host);
1006         if (ret)
1007                 goto out;
1008
1009         if (!mmc->ios.enhanced_strobe) {
1010                 /* Set the selected phase in delay line hw block */
1011                 ret = msm_config_cm_dll_phase(host,
1012                                               msm_host->saved_tuning_phase);
1013                 if (ret)
1014                         goto out;
1015                 config = readl_relaxed(host->ioaddr +
1016                                 msm_offset->core_dll_config);
1017                 config |= CORE_CMD_DAT_TRACK_SEL;
1018                 writel_relaxed(config, host->ioaddr +
1019                                 msm_offset->core_dll_config);
1020         }
1021
1022         if (msm_host->use_cdclp533)
1023                 ret = sdhci_msm_cdclp533_calibration(host);
1024         else
1025                 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1026 out:
1027         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1028                  __func__, ret);
1029         return ret;
1030 }
1031
1032 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1033 {
1034         struct mmc_ios *ios = &host->mmc->ios;
1035
1036         /*
1037          * Tuning is required for SDR104, HS200 and HS400 cards and
1038          * if clock frequency is greater than 100MHz in these modes.
1039          */
1040         if (host->clock <= CORE_FREQ_100MHZ ||
1041             !(ios->timing == MMC_TIMING_MMC_HS400 ||
1042             ios->timing == MMC_TIMING_MMC_HS200 ||
1043             ios->timing == MMC_TIMING_UHS_SDR104) ||
1044             ios->enhanced_strobe)
1045                 return false;
1046
1047         return true;
1048 }
1049
1050 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1051 {
1052         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1053         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1054         int ret;
1055
1056         /*
1057          * SDR DLL comes into picture only for timing modes which needs
1058          * tuning.
1059          */
1060         if (!sdhci_msm_is_tuning_needed(host))
1061                 return 0;
1062
1063         /* Reset the tuning block */
1064         ret = msm_init_cm_dll(host);
1065         if (ret)
1066                 return ret;
1067
1068         /* Restore the tuning block */
1069         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1070
1071         return ret;
1072 }
1073
1074 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1075 {
1076         const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1077         u32 config, oldconfig = readl_relaxed(host->ioaddr +
1078                                               msm_offset->core_dll_config);
1079
1080         config = oldconfig;
1081         if (enable) {
1082                 config |= CORE_CDR_EN;
1083                 config &= ~CORE_CDR_EXT_EN;
1084         } else {
1085                 config &= ~CORE_CDR_EN;
1086                 config |= CORE_CDR_EXT_EN;
1087         }
1088
1089         if (config != oldconfig) {
1090                 writel_relaxed(config, host->ioaddr +
1091                                msm_offset->core_dll_config);
1092         }
1093 }
1094
1095 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1096 {
1097         struct sdhci_host *host = mmc_priv(mmc);
1098         int tuning_seq_cnt = 3;
1099         u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1100         int rc;
1101         struct mmc_ios ios = host->mmc->ios;
1102         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1103         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1104
1105         if (!sdhci_msm_is_tuning_needed(host)) {
1106                 msm_host->use_cdr = false;
1107                 sdhci_msm_set_cdr(host, false);
1108                 return 0;
1109         }
1110
1111         /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1112         msm_host->use_cdr = true;
1113
1114         /*
1115          * For HS400 tuning in HS200 timing requires:
1116          * - select MCLK/2 in VENDOR_SPEC
1117          * - program MCLK to 400MHz (or nearest supported) in GCC
1118          */
1119         if (host->flags & SDHCI_HS400_TUNING) {
1120                 sdhci_msm_hc_select_mode(host);
1121                 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1122                 host->flags &= ~SDHCI_HS400_TUNING;
1123         }
1124
1125 retry:
1126         /* First of all reset the tuning block */
1127         rc = msm_init_cm_dll(host);
1128         if (rc)
1129                 return rc;
1130
1131         phase = 0;
1132         do {
1133                 /* Set the phase in delay line hw block */
1134                 rc = msm_config_cm_dll_phase(host, phase);
1135                 if (rc)
1136                         return rc;
1137
1138                 rc = mmc_send_tuning(mmc, opcode, NULL);
1139                 if (!rc) {
1140                         /* Tuning is successful at this tuning point */
1141                         tuned_phases[tuned_phase_cnt++] = phase;
1142                         dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1143                                  mmc_hostname(mmc), phase);
1144                 }
1145         } while (++phase < ARRAY_SIZE(tuned_phases));
1146
1147         if (tuned_phase_cnt) {
1148                 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1149                                                      tuned_phase_cnt);
1150                 if (rc < 0)
1151                         return rc;
1152                 else
1153                         phase = rc;
1154
1155                 /*
1156                  * Finally set the selected phase in delay
1157                  * line hw block.
1158                  */
1159                 rc = msm_config_cm_dll_phase(host, phase);
1160                 if (rc)
1161                         return rc;
1162                 msm_host->saved_tuning_phase = phase;
1163                 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1164                          mmc_hostname(mmc), phase);
1165         } else {
1166                 if (--tuning_seq_cnt)
1167                         goto retry;
1168                 /* Tuning failed */
1169                 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1170                        mmc_hostname(mmc));
1171                 rc = -EIO;
1172         }
1173
1174         if (!rc)
1175                 msm_host->tuning_done = true;
1176         return rc;
1177 }
1178
1179 /*
1180  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1181  * This needs to be done for both tuning and enhanced_strobe mode.
1182  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1183  * fixed feedback clock is used.
1184  */
1185 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1186 {
1187         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1188         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1189         int ret;
1190
1191         if (host->clock > CORE_FREQ_100MHZ &&
1192             (msm_host->tuning_done || ios->enhanced_strobe) &&
1193             !msm_host->calibration_done) {
1194                 ret = sdhci_msm_hs400_dll_calibration(host);
1195                 if (!ret)
1196                         msm_host->calibration_done = true;
1197                 else
1198                         pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1199                                mmc_hostname(host->mmc), ret);
1200         }
1201 }
1202
1203 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1204                                         unsigned int uhs)
1205 {
1206         struct mmc_host *mmc = host->mmc;
1207         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1208         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1209         u16 ctrl_2;
1210         u32 config;
1211         const struct sdhci_msm_offset *msm_offset =
1212                                         msm_host->offset;
1213
1214         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1215         /* Select Bus Speed Mode for host */
1216         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1217         switch (uhs) {
1218         case MMC_TIMING_UHS_SDR12:
1219                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1220                 break;
1221         case MMC_TIMING_UHS_SDR25:
1222                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1223                 break;
1224         case MMC_TIMING_UHS_SDR50:
1225                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1226                 break;
1227         case MMC_TIMING_MMC_HS400:
1228         case MMC_TIMING_MMC_HS200:
1229         case MMC_TIMING_UHS_SDR104:
1230                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1231                 break;
1232         case MMC_TIMING_UHS_DDR50:
1233         case MMC_TIMING_MMC_DDR52:
1234                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1235                 break;
1236         }
1237
1238         /*
1239          * When clock frequency is less than 100MHz, the feedback clock must be
1240          * provided and DLL must not be used so that tuning can be skipped. To
1241          * provide feedback clock, the mode selection can be any value less
1242          * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1243          */
1244         if (host->clock <= CORE_FREQ_100MHZ) {
1245                 if (uhs == MMC_TIMING_MMC_HS400 ||
1246                     uhs == MMC_TIMING_MMC_HS200 ||
1247                     uhs == MMC_TIMING_UHS_SDR104)
1248                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1249                 /*
1250                  * DLL is not required for clock <= 100MHz
1251                  * Thus, make sure DLL it is disabled when not required
1252                  */
1253                 config = readl_relaxed(host->ioaddr +
1254                                 msm_offset->core_dll_config);
1255                 config |= CORE_DLL_RST;
1256                 writel_relaxed(config, host->ioaddr +
1257                                 msm_offset->core_dll_config);
1258
1259                 config = readl_relaxed(host->ioaddr +
1260                                 msm_offset->core_dll_config);
1261                 config |= CORE_DLL_PDN;
1262                 writel_relaxed(config, host->ioaddr +
1263                                 msm_offset->core_dll_config);
1264
1265                 /*
1266                  * The DLL needs to be restored and CDCLP533 recalibrated
1267                  * when the clock frequency is set back to 400MHz.
1268                  */
1269                 msm_host->calibration_done = false;
1270         }
1271
1272         dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1273                 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1274         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1275
1276         if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1277                 sdhci_msm_hs400(host, &mmc->ios);
1278 }
1279
1280 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1281 {
1282         init_waitqueue_head(&msm_host->pwr_irq_wait);
1283 }
1284
1285 static inline void sdhci_msm_complete_pwr_irq_wait(
1286                 struct sdhci_msm_host *msm_host)
1287 {
1288         wake_up(&msm_host->pwr_irq_wait);
1289 }
1290
1291 /*
1292  * sdhci_msm_check_power_status API should be called when registers writes
1293  * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1294  * To what state the register writes will change the IO lines should be passed
1295  * as the argument req_type. This API will check whether the IO line's state
1296  * is already the expected state and will wait for power irq only if
1297  * power irq is expected to be trigerred based on the current IO line state
1298  * and expected IO line state.
1299  */
1300 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1301 {
1302         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1303         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1304         bool done = false;
1305         u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1306         const struct sdhci_msm_offset *msm_offset =
1307                                         msm_host->offset;
1308
1309         pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1310                         mmc_hostname(host->mmc), __func__, req_type,
1311                         msm_host->curr_pwr_state, msm_host->curr_io_level);
1312
1313         /*
1314          * The power interrupt will not be generated for signal voltage
1315          * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1316          * Since sdhci-msm-v5, this bit has been removed and SW must consider
1317          * it as always set.
1318          */
1319         if (!msm_host->mci_removed)
1320                 val = msm_host_readl(msm_host, host,
1321                                 msm_offset->core_generics);
1322         if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1323             !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1324                 return;
1325         }
1326
1327         /*
1328          * The IRQ for request type IO High/LOW will be generated when -
1329          * there is a state change in 1.8V enable bit (bit 3) of
1330          * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1331          * which indicates 3.3V IO voltage. So, when MMC core layer tries
1332          * to set it to 3.3V before card detection happens, the
1333          * IRQ doesn't get triggered as there is no state change in this bit.
1334          * The driver already handles this case by changing the IO voltage
1335          * level to high as part of controller power up sequence. Hence, check
1336          * for host->pwr to handle a case where IO voltage high request is
1337          * issued even before controller power up.
1338          */
1339         if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1340                 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1341                                 mmc_hostname(host->mmc), req_type);
1342                 return;
1343         }
1344         if ((req_type & msm_host->curr_pwr_state) ||
1345                         (req_type & msm_host->curr_io_level))
1346                 done = true;
1347         /*
1348          * This is needed here to handle cases where register writes will
1349          * not change the current bus state or io level of the controller.
1350          * In this case, no power irq will be triggerred and we should
1351          * not wait.
1352          */
1353         if (!done) {
1354                 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1355                                 msm_host->pwr_irq_flag,
1356                                 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1357                         dev_warn(&msm_host->pdev->dev,
1358                                  "%s: pwr_irq for req: (%d) timed out\n",
1359                                  mmc_hostname(host->mmc), req_type);
1360         }
1361         pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1362                         __func__, req_type);
1363 }
1364
1365 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1366 {
1367         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1368         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1369         const struct sdhci_msm_offset *msm_offset =
1370                                         msm_host->offset;
1371
1372         pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1373                 mmc_hostname(host->mmc),
1374                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1375                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1376                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1377 }
1378
1379 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1380 {
1381         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1382         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1383         u32 irq_status, irq_ack = 0;
1384         int retry = 10;
1385         u32 pwr_state = 0, io_level = 0;
1386         u32 config;
1387         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1388
1389         irq_status = msm_host_readl(msm_host, host,
1390                         msm_offset->core_pwrctl_status);
1391         irq_status &= INT_MASK;
1392
1393         msm_host_writel(msm_host, irq_status, host,
1394                         msm_offset->core_pwrctl_clear);
1395
1396         /*
1397          * There is a rare HW scenario where the first clear pulse could be
1398          * lost when actual reset and clear/read of status register is
1399          * happening at a time. Hence, retry for at least 10 times to make
1400          * sure status register is cleared. Otherwise, this will result in
1401          * a spurious power IRQ resulting in system instability.
1402          */
1403         while (irq_status & msm_host_readl(msm_host, host,
1404                                 msm_offset->core_pwrctl_status)) {
1405                 if (retry == 0) {
1406                         pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1407                                         mmc_hostname(host->mmc), irq_status);
1408                         sdhci_msm_dump_pwr_ctrl_regs(host);
1409                         WARN_ON(1);
1410                         break;
1411                 }
1412                 msm_host_writel(msm_host, irq_status, host,
1413                         msm_offset->core_pwrctl_clear);
1414                 retry--;
1415                 udelay(10);
1416         }
1417
1418         /* Handle BUS ON/OFF*/
1419         if (irq_status & CORE_PWRCTL_BUS_ON) {
1420                 pwr_state = REQ_BUS_ON;
1421                 io_level = REQ_IO_HIGH;
1422                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1423         }
1424         if (irq_status & CORE_PWRCTL_BUS_OFF) {
1425                 pwr_state = REQ_BUS_OFF;
1426                 io_level = REQ_IO_LOW;
1427                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1428         }
1429         /* Handle IO LOW/HIGH */
1430         if (irq_status & CORE_PWRCTL_IO_LOW) {
1431                 io_level = REQ_IO_LOW;
1432                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1433         }
1434         if (irq_status & CORE_PWRCTL_IO_HIGH) {
1435                 io_level = REQ_IO_HIGH;
1436                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1437         }
1438
1439         /*
1440          * The driver has to acknowledge the interrupt, switch voltages and
1441          * report back if it succeded or not to this register. The voltage
1442          * switches are handled by the sdhci core, so just report success.
1443          */
1444         msm_host_writel(msm_host, irq_ack, host,
1445                         msm_offset->core_pwrctl_ctl);
1446
1447         /*
1448          * If we don't have info regarding the voltage levels supported by
1449          * regulators, don't change the IO PAD PWR SWITCH.
1450          */
1451         if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1452                 u32 new_config;
1453                 /*
1454                  * We should unset IO PAD PWR switch only if the register write
1455                  * can set IO lines high and the regulator also switches to 3 V.
1456                  * Else, we should keep the IO PAD PWR switch set.
1457                  * This is applicable to certain targets where eMMC vccq supply
1458                  * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1459                  * IO PAD PWR switch must be kept set to reflect actual
1460                  * regulator voltage. This way, during initialization of
1461                  * controllers with only 1.8V, we will set the IO PAD bit
1462                  * without waiting for a REQ_IO_LOW.
1463                  */
1464                 config = readl_relaxed(host->ioaddr +
1465                                 msm_offset->core_vendor_spec);
1466                 new_config = config;
1467
1468                 if ((io_level & REQ_IO_HIGH) &&
1469                                 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1470                         new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1471                 else if ((io_level & REQ_IO_LOW) ||
1472                                 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1473                         new_config |= CORE_IO_PAD_PWR_SWITCH;
1474
1475                 if (config ^ new_config)
1476                         writel_relaxed(new_config, host->ioaddr +
1477                                         msm_offset->core_vendor_spec);
1478         }
1479
1480         if (pwr_state)
1481                 msm_host->curr_pwr_state = pwr_state;
1482         if (io_level)
1483                 msm_host->curr_io_level = io_level;
1484
1485         pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1486                 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1487                 irq_ack);
1488 }
1489
1490 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1491 {
1492         struct sdhci_host *host = (struct sdhci_host *)data;
1493         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1494         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1495
1496         sdhci_msm_handle_pwr_irq(host, irq);
1497         msm_host->pwr_irq_flag = 1;
1498         sdhci_msm_complete_pwr_irq_wait(msm_host);
1499
1500
1501         return IRQ_HANDLED;
1502 }
1503
1504 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1505 {
1506         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1507         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1508         struct clk *core_clk = msm_host->bulk_clks[0].clk;
1509
1510         return clk_round_rate(core_clk, ULONG_MAX);
1511 }
1512
1513 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1514 {
1515         return SDHCI_MSM_MIN_CLOCK;
1516 }
1517
1518 /**
1519  * __sdhci_msm_set_clock - sdhci_msm clock control.
1520  *
1521  * Description:
1522  * MSM controller does not use internal divider and
1523  * instead directly control the GCC clock as per
1524  * HW recommendation.
1525  **/
1526 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1527 {
1528         u16 clk;
1529         /*
1530          * Keep actual_clock as zero -
1531          * - since there is no divider used so no need of having actual_clock.
1532          * - MSM controller uses SDCLK for data timeout calculation. If
1533          *   actual_clock is zero, host->clock is taken for calculation.
1534          */
1535         host->mmc->actual_clock = 0;
1536
1537         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1538
1539         if (clock == 0)
1540                 return;
1541
1542         /*
1543          * MSM controller do not use clock divider.
1544          * Thus read SDHCI_CLOCK_CONTROL and only enable
1545          * clock with no divider value programmed.
1546          */
1547         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1548         sdhci_enable_clk(host, clk);
1549 }
1550
1551 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1552 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1553 {
1554         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1555         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1556
1557         if (!clock) {
1558                 msm_host->clk_rate = clock;
1559                 goto out;
1560         }
1561
1562         sdhci_msm_hc_select_mode(host);
1563
1564         msm_set_clock_rate_for_bus_mode(host, clock);
1565 out:
1566         __sdhci_msm_set_clock(host, clock);
1567 }
1568
1569 /*
1570  * Platform specific register write functions. This is so that, if any
1571  * register write needs to be followed up by platform specific actions,
1572  * they can be added here. These functions can go to sleep when writes
1573  * to certain registers are done.
1574  * These functions are relying on sdhci_set_ios not using spinlock.
1575  */
1576 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1577 {
1578         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1579         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1580         u32 req_type = 0;
1581
1582         switch (reg) {
1583         case SDHCI_HOST_CONTROL2:
1584                 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1585                         REQ_IO_HIGH;
1586                 break;
1587         case SDHCI_SOFTWARE_RESET:
1588                 if (host->pwr && (val & SDHCI_RESET_ALL))
1589                         req_type = REQ_BUS_OFF;
1590                 break;
1591         case SDHCI_POWER_CONTROL:
1592                 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1593                 break;
1594         case SDHCI_TRANSFER_MODE:
1595                 msm_host->transfer_mode = val;
1596                 break;
1597         case SDHCI_COMMAND:
1598                 if (!msm_host->use_cdr)
1599                         break;
1600                 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
1601                     SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
1602                     SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
1603                         sdhci_msm_set_cdr(host, true);
1604                 else
1605                         sdhci_msm_set_cdr(host, false);
1606                 break;
1607         }
1608
1609         if (req_type) {
1610                 msm_host->pwr_irq_flag = 0;
1611                 /*
1612                  * Since this register write may trigger a power irq, ensure
1613                  * all previous register writes are complete by this point.
1614                  */
1615                 mb();
1616         }
1617         return req_type;
1618 }
1619
1620 /* This function may sleep*/
1621 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1622 {
1623         u32 req_type = 0;
1624
1625         req_type = __sdhci_msm_check_write(host, val, reg);
1626         writew_relaxed(val, host->ioaddr + reg);
1627
1628         if (req_type)
1629                 sdhci_msm_check_power_status(host, req_type);
1630 }
1631
1632 /* This function may sleep*/
1633 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1634 {
1635         u32 req_type = 0;
1636
1637         req_type = __sdhci_msm_check_write(host, val, reg);
1638
1639         writeb_relaxed(val, host->ioaddr + reg);
1640
1641         if (req_type)
1642                 sdhci_msm_check_power_status(host, req_type);
1643 }
1644
1645 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
1646 {
1647         struct mmc_host *mmc = msm_host->mmc;
1648         struct regulator *supply = mmc->supply.vqmmc;
1649         u32 caps = 0, config;
1650         struct sdhci_host *host = mmc_priv(mmc);
1651         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1652
1653         if (!IS_ERR(mmc->supply.vqmmc)) {
1654                 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
1655                         caps |= CORE_1_8V_SUPPORT;
1656                 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
1657                         caps |= CORE_3_0V_SUPPORT;
1658
1659                 if (!caps)
1660                         pr_warn("%s: 1.8/3V not supported for vqmmc\n",
1661                                         mmc_hostname(mmc));
1662         }
1663
1664         if (caps) {
1665                 /*
1666                  * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
1667                  * bit can be used as required later on.
1668                  */
1669                 u32 io_level = msm_host->curr_io_level;
1670
1671                 config = readl_relaxed(host->ioaddr +
1672                                 msm_offset->core_vendor_spec);
1673                 config |= CORE_IO_PAD_PWR_SWITCH_EN;
1674
1675                 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
1676                         config &= ~CORE_IO_PAD_PWR_SWITCH;
1677                 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
1678                         config |= CORE_IO_PAD_PWR_SWITCH;
1679
1680                 writel_relaxed(config,
1681                                 host->ioaddr + msm_offset->core_vendor_spec);
1682         }
1683         msm_host->caps_0 |= caps;
1684         pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
1685 }
1686
1687 static const struct sdhci_msm_variant_ops mci_var_ops = {
1688         .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
1689         .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
1690 };
1691
1692 static const struct sdhci_msm_variant_ops v5_var_ops = {
1693         .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
1694         .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
1695 };
1696
1697 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
1698         .var_ops = &mci_var_ops,
1699         .offset = &sdhci_msm_mci_offset,
1700 };
1701
1702 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
1703         .mci_removed = true,
1704         .var_ops = &v5_var_ops,
1705         .offset = &sdhci_msm_v5_offset,
1706 };
1707
1708 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
1709         .mci_removed = true,
1710         .restore_dll_config = true,
1711         .var_ops = &v5_var_ops,
1712         .offset = &sdhci_msm_v5_offset,
1713 };
1714
1715 static const struct of_device_id sdhci_msm_dt_match[] = {
1716         {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
1717         {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
1718         {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
1719         {},
1720 };
1721
1722 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1723
1724 static const struct sdhci_ops sdhci_msm_ops = {
1725         .reset = sdhci_reset,
1726         .set_clock = sdhci_msm_set_clock,
1727         .get_min_clock = sdhci_msm_get_min_clock,
1728         .get_max_clock = sdhci_msm_get_max_clock,
1729         .set_bus_width = sdhci_set_bus_width,
1730         .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1731         .write_w = sdhci_msm_writew,
1732         .write_b = sdhci_msm_writeb,
1733 };
1734
1735 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1736         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1737                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1738                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1739         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1740         .ops = &sdhci_msm_ops,
1741 };
1742
1743 static int sdhci_msm_probe(struct platform_device *pdev)
1744 {
1745         struct sdhci_host *host;
1746         struct sdhci_pltfm_host *pltfm_host;
1747         struct sdhci_msm_host *msm_host;
1748         struct resource *core_memres;
1749         struct clk *clk;
1750         int ret;
1751         u16 host_version, core_minor;
1752         u32 core_version, config;
1753         u8 core_major;
1754         const struct sdhci_msm_offset *msm_offset;
1755         const struct sdhci_msm_variant_info *var_info;
1756
1757         host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1758         if (IS_ERR(host))
1759                 return PTR_ERR(host);
1760
1761         host->sdma_boundary = 0;
1762         pltfm_host = sdhci_priv(host);
1763         msm_host = sdhci_pltfm_priv(pltfm_host);
1764         msm_host->mmc = host->mmc;
1765         msm_host->pdev = pdev;
1766
1767         ret = mmc_of_parse(host->mmc);
1768         if (ret)
1769                 goto pltfm_free;
1770
1771         /*
1772          * Based on the compatible string, load the required msm host info from
1773          * the data associated with the version info.
1774          */
1775         var_info = of_device_get_match_data(&pdev->dev);
1776
1777         msm_host->mci_removed = var_info->mci_removed;
1778         msm_host->restore_dll_config = var_info->restore_dll_config;
1779         msm_host->var_ops = var_info->var_ops;
1780         msm_host->offset = var_info->offset;
1781
1782         msm_offset = msm_host->offset;
1783
1784         sdhci_get_of_property(pdev);
1785
1786         msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1787
1788         /* Setup SDCC bus voter clock. */
1789         msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1790         if (!IS_ERR(msm_host->bus_clk)) {
1791                 /* Vote for max. clk rate for max. performance */
1792                 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1793                 if (ret)
1794                         goto pltfm_free;
1795                 ret = clk_prepare_enable(msm_host->bus_clk);
1796                 if (ret)
1797                         goto pltfm_free;
1798         }
1799
1800         /* Setup main peripheral bus clock */
1801         clk = devm_clk_get(&pdev->dev, "iface");
1802         if (IS_ERR(clk)) {
1803                 ret = PTR_ERR(clk);
1804                 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1805                 goto bus_clk_disable;
1806         }
1807         msm_host->bulk_clks[1].clk = clk;
1808
1809         /* Setup SDC MMC clock */
1810         clk = devm_clk_get(&pdev->dev, "core");
1811         if (IS_ERR(clk)) {
1812                 ret = PTR_ERR(clk);
1813                 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1814                 goto bus_clk_disable;
1815         }
1816         msm_host->bulk_clks[0].clk = clk;
1817
1818         /* Vote for maximum clock rate for maximum performance */
1819         ret = clk_set_rate(clk, INT_MAX);
1820         if (ret)
1821                 dev_warn(&pdev->dev, "core clock boost failed\n");
1822
1823         clk = devm_clk_get(&pdev->dev, "cal");
1824         if (IS_ERR(clk))
1825                 clk = NULL;
1826         msm_host->bulk_clks[2].clk = clk;
1827
1828         clk = devm_clk_get(&pdev->dev, "sleep");
1829         if (IS_ERR(clk))
1830                 clk = NULL;
1831         msm_host->bulk_clks[3].clk = clk;
1832
1833         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1834                                       msm_host->bulk_clks);
1835         if (ret)
1836                 goto bus_clk_disable;
1837
1838         /*
1839          * xo clock is needed for FLL feature of cm_dll.
1840          * In case if xo clock is not mentioned in DT, warn and proceed.
1841          */
1842         msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1843         if (IS_ERR(msm_host->xo_clk)) {
1844                 ret = PTR_ERR(msm_host->xo_clk);
1845                 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1846         }
1847
1848         if (!msm_host->mci_removed) {
1849                 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1850                 msm_host->core_mem = devm_ioremap_resource(&pdev->dev,
1851                                 core_memres);
1852
1853                 if (IS_ERR(msm_host->core_mem)) {
1854                         ret = PTR_ERR(msm_host->core_mem);
1855                         goto clk_disable;
1856                 }
1857         }
1858
1859         /* Reset the vendor spec register to power on reset state */
1860         writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1861                         host->ioaddr + msm_offset->core_vendor_spec);
1862
1863         if (!msm_host->mci_removed) {
1864                 /* Set HC_MODE_EN bit in HC_MODE register */
1865                 msm_host_writel(msm_host, HC_MODE_EN, host,
1866                                 msm_offset->core_hc_mode);
1867                 config = msm_host_readl(msm_host, host,
1868                                 msm_offset->core_hc_mode);
1869                 config |= FF_CLK_SW_RST_DIS;
1870                 msm_host_writel(msm_host, config, host,
1871                                 msm_offset->core_hc_mode);
1872         }
1873
1874         host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1875         dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1876                 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1877                                SDHCI_VENDOR_VER_SHIFT));
1878
1879         core_version = msm_host_readl(msm_host, host,
1880                         msm_offset->core_mci_version);
1881         core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1882                       CORE_VERSION_MAJOR_SHIFT;
1883         core_minor = core_version & CORE_VERSION_MINOR_MASK;
1884         dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1885                 core_version, core_major, core_minor);
1886
1887         if (core_major == 1 && core_minor >= 0x42)
1888                 msm_host->use_14lpp_dll_reset = true;
1889
1890         /*
1891          * SDCC 5 controller with major version 1, minor version 0x34 and later
1892          * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1893          */
1894         if (core_major == 1 && core_minor < 0x34)
1895                 msm_host->use_cdclp533 = true;
1896
1897         /*
1898          * Support for some capabilities is not advertised by newer
1899          * controller versions and must be explicitly enabled.
1900          */
1901         if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1902                 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1903                 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1904                 writel_relaxed(config, host->ioaddr +
1905                                 msm_offset->core_vendor_spec_capabilities0);
1906         }
1907
1908         /*
1909          * Power on reset state may trigger power irq if previous status of
1910          * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1911          * interrupt in GIC, any pending power irq interrupt should be
1912          * acknowledged. Otherwise power irq interrupt handler would be
1913          * fired prematurely.
1914          */
1915         sdhci_msm_handle_pwr_irq(host, 0);
1916
1917         /*
1918          * Ensure that above writes are propogated before interrupt enablement
1919          * in GIC.
1920          */
1921         mb();
1922
1923         /* Setup IRQ for handling power/voltage tasks with PMIC */
1924         msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1925         if (msm_host->pwr_irq < 0) {
1926                 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1927                         msm_host->pwr_irq);
1928                 ret = msm_host->pwr_irq;
1929                 goto clk_disable;
1930         }
1931
1932         sdhci_msm_init_pwr_irq_wait(msm_host);
1933         /* Enable pwr irq interrupts */
1934         msm_host_writel(msm_host, INT_MASK, host,
1935                 msm_offset->core_pwrctl_mask);
1936
1937         ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1938                                         sdhci_msm_pwr_irq, IRQF_ONESHOT,
1939                                         dev_name(&pdev->dev), host);
1940         if (ret) {
1941                 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1942                 goto clk_disable;
1943         }
1944
1945         pm_runtime_get_noresume(&pdev->dev);
1946         pm_runtime_set_active(&pdev->dev);
1947         pm_runtime_enable(&pdev->dev);
1948         pm_runtime_set_autosuspend_delay(&pdev->dev,
1949                                          MSM_MMC_AUTOSUSPEND_DELAY_MS);
1950         pm_runtime_use_autosuspend(&pdev->dev);
1951
1952         host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1953         ret = sdhci_add_host(host);
1954         if (ret)
1955                 goto pm_runtime_disable;
1956         sdhci_msm_set_regulator_caps(msm_host);
1957
1958         pm_runtime_mark_last_busy(&pdev->dev);
1959         pm_runtime_put_autosuspend(&pdev->dev);
1960
1961         return 0;
1962
1963 pm_runtime_disable:
1964         pm_runtime_disable(&pdev->dev);
1965         pm_runtime_set_suspended(&pdev->dev);
1966         pm_runtime_put_noidle(&pdev->dev);
1967 clk_disable:
1968         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1969                                    msm_host->bulk_clks);
1970 bus_clk_disable:
1971         if (!IS_ERR(msm_host->bus_clk))
1972                 clk_disable_unprepare(msm_host->bus_clk);
1973 pltfm_free:
1974         sdhci_pltfm_free(pdev);
1975         return ret;
1976 }
1977
1978 static int sdhci_msm_remove(struct platform_device *pdev)
1979 {
1980         struct sdhci_host *host = platform_get_drvdata(pdev);
1981         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1982         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1983         int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1984                     0xffffffff);
1985
1986         sdhci_remove_host(host, dead);
1987
1988         pm_runtime_get_sync(&pdev->dev);
1989         pm_runtime_disable(&pdev->dev);
1990         pm_runtime_put_noidle(&pdev->dev);
1991
1992         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1993                                    msm_host->bulk_clks);
1994         if (!IS_ERR(msm_host->bus_clk))
1995                 clk_disable_unprepare(msm_host->bus_clk);
1996         sdhci_pltfm_free(pdev);
1997         return 0;
1998 }
1999
2000 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
2001 {
2002         struct sdhci_host *host = dev_get_drvdata(dev);
2003         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2004         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2005
2006         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2007                                    msm_host->bulk_clks);
2008
2009         return 0;
2010 }
2011
2012 static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
2013 {
2014         struct sdhci_host *host = dev_get_drvdata(dev);
2015         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2016         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2017         int ret;
2018
2019         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2020                                        msm_host->bulk_clks);
2021         if (ret)
2022                 return ret;
2023         /*
2024          * Whenever core-clock is gated dynamically, it's needed to
2025          * restore the SDR DLL settings when the clock is ungated.
2026          */
2027         if (msm_host->restore_dll_config && msm_host->clk_rate)
2028                 return sdhci_msm_restore_sdr_dll_config(host);
2029
2030         return 0;
2031 }
2032
2033 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2034         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2035                                 pm_runtime_force_resume)
2036         SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2037                            sdhci_msm_runtime_resume,
2038                            NULL)
2039 };
2040
2041 static struct platform_driver sdhci_msm_driver = {
2042         .probe = sdhci_msm_probe,
2043         .remove = sdhci_msm_remove,
2044         .driver = {
2045                    .name = "sdhci_msm",
2046                    .of_match_table = sdhci_msm_dt_match,
2047                    .pm = &sdhci_msm_pm_ops,
2048         },
2049 };
2050
2051 module_platform_driver(sdhci_msm_driver);
2052
2053 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2054 MODULE_LICENSE("GPL v2");