drivers/mmc/host/sdhci-msm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
   4  *
   5  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/of_device.h>
  10 #include <linux/delay.h>
  11 #include <linux/mmc/mmc.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/pm_opp.h>
  14 #include <linux/slab.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/qcom_scm.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/interconnect.h>
  19 #include <linux/pinctrl/consumer.h>
  20
  21 #include "sdhci-pltfm.h"
  22 #include "cqhci.h"
  23
  24 #define CORE_MCI_VERSION                0x50
  25 #define CORE_VERSION_MAJOR_SHIFT        28
  26 #define CORE_VERSION_MAJOR_MASK         (0xf << CORE_VERSION_MAJOR_SHIFT)
  27 #define CORE_VERSION_MINOR_MASK         0xff
  28
  29 #define CORE_MCI_GENERICS               0x70
  30 #define SWITCHABLE_SIGNALING_VOLTAGE    BIT(29)
  31
  32 #define HC_MODE_EN              0x1
  33 #define CORE_POWER              0x0
  34 #define CORE_SW_RST             BIT(7)
  35 #define FF_CLK_SW_RST_DIS       BIT(13)
  36
  37 #define CORE_PWRCTL_BUS_OFF     BIT(0)
  38 #define CORE_PWRCTL_BUS_ON      BIT(1)
  39 #define CORE_PWRCTL_IO_LOW      BIT(2)
  40 #define CORE_PWRCTL_IO_HIGH     BIT(3)
  41 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
  42 #define CORE_PWRCTL_BUS_FAIL    BIT(1)
  43 #define CORE_PWRCTL_IO_SUCCESS  BIT(2)
  44 #define CORE_PWRCTL_IO_FAIL     BIT(3)
  45 #define REQ_BUS_OFF             BIT(0)
  46 #define REQ_BUS_ON              BIT(1)
  47 #define REQ_IO_LOW              BIT(2)
  48 #define REQ_IO_HIGH             BIT(3)
  49 #define INT_MASK                0xf
  50 #define MAX_PHASES              16
  51 #define CORE_DLL_LOCK           BIT(7)
  52 #define CORE_DDR_DLL_LOCK       BIT(11)
  53 #define CORE_DLL_EN             BIT(16)
  54 #define CORE_CDR_EN             BIT(17)
  55 #define CORE_CK_OUT_EN          BIT(18)
  56 #define CORE_CDR_EXT_EN         BIT(19)
  57 #define CORE_DLL_PDN            BIT(29)
  58 #define CORE_DLL_RST            BIT(30)
  59 #define CORE_CMD_DAT_TRACK_SEL  BIT(0)
  60
  61 #define CORE_DDR_CAL_EN         BIT(0)
  62 #define CORE_FLL_CYCLE_CNT      BIT(18)
  63 #define CORE_DLL_CLOCK_DISABLE  BIT(21)
  64
  65 #define DLL_USR_CTL_POR_VAL     0x10800
  66 #define ENABLE_DLL_LOCK_STATUS  BIT(26)
  67 #define FINE_TUNE_MODE_EN       BIT(27)
  68 #define BIAS_OK_SIGNAL          BIT(29)
  69
  70 #define DLL_CONFIG_3_LOW_FREQ_VAL       0x08
  71 #define DLL_CONFIG_3_HIGH_FREQ_VAL      0x10
  72
  73 #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
  74 #define CORE_CLK_PWRSAVE        BIT(1)
  75 #define CORE_HC_MCLK_SEL_DFLT   (2 << 8)
  76 #define CORE_HC_MCLK_SEL_HS400  (3 << 8)
  77 #define CORE_HC_MCLK_SEL_MASK   (3 << 8)
  78 #define CORE_IO_PAD_PWR_SWITCH_EN       BIT(15)
  79 #define CORE_IO_PAD_PWR_SWITCH  BIT(16)
  80 #define CORE_HC_SELECT_IN_EN    BIT(18)
  81 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
  82 #define CORE_HC_SELECT_IN_MASK  (7 << 19)
  83
  84 #define CORE_3_0V_SUPPORT       BIT(25)
  85 #define CORE_1_8V_SUPPORT       BIT(26)
  86 #define CORE_VOLT_SUPPORT       (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
  87
  88 #define CORE_CSR_CDC_CTLR_CFG0          0x130
  89 #define CORE_SW_TRIG_FULL_CALIB         BIT(16)
  90 #define CORE_HW_AUTOCAL_ENA             BIT(17)
  91
  92 #define CORE_CSR_CDC_CTLR_CFG1          0x134
  93 #define CORE_CSR_CDC_CAL_TIMER_CFG0     0x138
  94 #define CORE_TIMER_ENA                  BIT(16)
  95
  96 #define CORE_CSR_CDC_CAL_TIMER_CFG1     0x13C
  97 #define CORE_CSR_CDC_REFCOUNT_CFG       0x140
  98 #define CORE_CSR_CDC_COARSE_CAL_CFG     0x144
  99 #define CORE_CDC_OFFSET_CFG             0x14C
 100 #define CORE_CSR_CDC_DELAY_CFG          0x150
 101 #define CORE_CDC_SLAVE_DDA_CFG          0x160
 102 #define CORE_CSR_CDC_STATUS0            0x164
 103 #define CORE_CALIBRATION_DONE           BIT(0)
 104
 105 #define CORE_CDC_ERROR_CODE_MASK        0x7000000
 106
 107 #define CORE_CSR_CDC_GEN_CFG            0x178
 108 #define CORE_CDC_SWITCH_BYPASS_OFF      BIT(0)
 109 #define CORE_CDC_SWITCH_RC_EN           BIT(1)
 110
 111 #define CORE_CDC_T4_DLY_SEL             BIT(0)
 112 #define CORE_CMDIN_RCLK_EN              BIT(1)
 113 #define CORE_START_CDC_TRAFFIC          BIT(6)
 114
 115 #define CORE_PWRSAVE_DLL        BIT(3)
 116
 117 #define DDR_CONFIG_POR_VAL      0x80040873
 118
 119
 120 #define INVALID_TUNING_PHASE    -1
 121 #define SDHCI_MSM_MIN_CLOCK     400000
 122 #define CORE_FREQ_100MHZ        (100 * 1000 * 1000)
 123
 124 #define CDR_SELEXT_SHIFT        20
 125 #define CDR_SELEXT_MASK         (0xf << CDR_SELEXT_SHIFT)
 126 #define CMUX_SHIFT_PHASE_SHIFT  24
 127 #define CMUX_SHIFT_PHASE_MASK   (7 << CMUX_SHIFT_PHASE_SHIFT)
 128
 129 #define MSM_MMC_AUTOSUSPEND_DELAY_MS    50
 130
 131 /* Timeout value to avoid infinite waiting for pwr_irq */
 132 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
 133
 134 /* Max load for eMMC Vdd-io supply */
 135 #define MMC_VQMMC_MAX_LOAD_UA   325000
 136
 137 #define msm_host_readl(msm_host, host, offset) \
 138         msm_host->var_ops->msm_readl_relaxed(host, offset)
 139
 140 #define msm_host_writel(msm_host, val, host, offset) \
 141         msm_host->var_ops->msm_writel_relaxed(val, host, offset)
 142
 143 /* CQHCI vendor specific registers */
 144 #define CQHCI_VENDOR_CFG1       0xA00
 145 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN   (0x3 << 13)
 146
 147 struct sdhci_msm_offset {
 148         u32 core_hc_mode;
 149         u32 core_mci_data_cnt;
 150         u32 core_mci_status;
 151         u32 core_mci_fifo_cnt;
 152         u32 core_mci_version;
 153         u32 core_generics;
 154         u32 core_testbus_config;
 155         u32 core_testbus_sel2_bit;
 156         u32 core_testbus_ena;
 157         u32 core_testbus_sel2;
 158         u32 core_pwrctl_status;
 159         u32 core_pwrctl_mask;
 160         u32 core_pwrctl_clear;
 161         u32 core_pwrctl_ctl;
 162         u32 core_sdcc_debug_reg;
 163         u32 core_dll_config;
 164         u32 core_dll_status;
 165         u32 core_vendor_spec;
 166         u32 core_vendor_spec_adma_err_addr0;
 167         u32 core_vendor_spec_adma_err_addr1;
 168         u32 core_vendor_spec_func2;
 169         u32 core_vendor_spec_capabilities0;
 170         u32 core_ddr_200_cfg;
 171         u32 core_vendor_spec3;
 172         u32 core_dll_config_2;
 173         u32 core_dll_config_3;
 174         u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
 175         u32 core_ddr_config;
 176         u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */
 177 };
 178
 179 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
 180         .core_mci_data_cnt = 0x35c,
 181         .core_mci_status = 0x324,
 182         .core_mci_fifo_cnt = 0x308,
 183         .core_mci_version = 0x318,
 184         .core_generics = 0x320,
 185         .core_testbus_config = 0x32c,
 186         .core_testbus_sel2_bit = 3,
 187         .core_testbus_ena = (1 << 31),
 188         .core_testbus_sel2 = (1 << 3),
 189         .core_pwrctl_status = 0x240,
 190         .core_pwrctl_mask = 0x244,
 191         .core_pwrctl_clear = 0x248,
 192         .core_pwrctl_ctl = 0x24c,
 193         .core_sdcc_debug_reg = 0x358,
 194         .core_dll_config = 0x200,
 195         .core_dll_status = 0x208,
 196         .core_vendor_spec = 0x20c,
 197         .core_vendor_spec_adma_err_addr0 = 0x214,
 198         .core_vendor_spec_adma_err_addr1 = 0x218,
 199         .core_vendor_spec_func2 = 0x210,
 200         .core_vendor_spec_capabilities0 = 0x21c,
 201         .core_ddr_200_cfg = 0x224,
 202         .core_vendor_spec3 = 0x250,
 203         .core_dll_config_2 = 0x254,
 204         .core_dll_config_3 = 0x258,
 205         .core_ddr_config = 0x25c,
 206         .core_dll_usr_ctl = 0x388,
 207 };
 208
 209 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
 210         .core_hc_mode = 0x78,
 211         .core_mci_data_cnt = 0x30,
 212         .core_mci_status = 0x34,
 213         .core_mci_fifo_cnt = 0x44,
 214         .core_mci_version = 0x050,
 215         .core_generics = 0x70,
 216         .core_testbus_config = 0x0cc,
 217         .core_testbus_sel2_bit = 4,
 218         .core_testbus_ena = (1 << 3),
 219         .core_testbus_sel2 = (1 << 4),
 220         .core_pwrctl_status = 0xdc,
 221         .core_pwrctl_mask = 0xe0,
 222         .core_pwrctl_clear = 0xe4,
 223         .core_pwrctl_ctl = 0xe8,
 224         .core_sdcc_debug_reg = 0x124,
 225         .core_dll_config = 0x100,
 226         .core_dll_status = 0x108,
 227         .core_vendor_spec = 0x10c,
 228         .core_vendor_spec_adma_err_addr0 = 0x114,
 229         .core_vendor_spec_adma_err_addr1 = 0x118,
 230         .core_vendor_spec_func2 = 0x110,
 231         .core_vendor_spec_capabilities0 = 0x11c,
 232         .core_ddr_200_cfg = 0x184,
 233         .core_vendor_spec3 = 0x1b0,
 234         .core_dll_config_2 = 0x1b4,
 235         .core_ddr_config_old = 0x1b8,
 236         .core_ddr_config = 0x1bc,
 237 };
 238
 239 struct sdhci_msm_variant_ops {
 240         u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
 241         void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
 242                         u32 offset);
 243 };
 244
 245 /*
 246  * From V5, register spaces have changed. Wrap this info in a structure
 247  * and choose the data_structure based on version info mentioned in DT.
 248  */
 249 struct sdhci_msm_variant_info {
 250         bool mci_removed;
 251         bool restore_dll_config;
 252         const struct sdhci_msm_variant_ops *var_ops;
 253         const struct sdhci_msm_offset *offset;
 254 };
 255
 256 struct sdhci_msm_host {
 257         struct platform_device *pdev;
 258         void __iomem *core_mem; /* MSM SDCC mapped address */
 259         void __iomem *ice_mem;  /* MSM ICE mapped address (if available) */
 260         int pwr_irq;            /* power irq */
 261         struct clk *bus_clk;    /* SDHC bus voter clock */
 262         struct clk *xo_clk;     /* TCXO clk needed for FLL feature of cm_dll*/
 263         /* core, iface, cal, sleep, and ice clocks */
 264         struct clk_bulk_data bulk_clks[5];
 265         unsigned long clk_rate;
 266         struct mmc_host *mmc;
 267         struct opp_table *opp_table;
 268         bool use_14lpp_dll_reset;
 269         bool tuning_done;
 270         bool calibration_done;
 271         u8 saved_tuning_phase;
 272         bool use_cdclp533;
 273         u32 curr_pwr_state;
 274         u32 curr_io_level;
 275         wait_queue_head_t pwr_irq_wait;
 276         bool pwr_irq_flag;
 277         u32 caps_0;
 278         bool mci_removed;
 279         bool restore_dll_config;
 280         const struct sdhci_msm_variant_ops *var_ops;
 281         const struct sdhci_msm_offset *offset;
 282         bool use_cdr;
 283         u32 transfer_mode;
 284         bool updated_ddr_cfg;
 285         bool uses_tassadar_dll;
 286         u32 dll_config;
 287         u32 ddr_config;
 288         bool vqmmc_enabled;
 289 };
 290
 291 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
 292 {
 293         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 294         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 295
 296         return msm_host->offset;
 297 }
 298
 299 /*
 300  * APIs to read/write to vendor specific registers which were there in the
 301  * core_mem region before MCI was removed.
 302  */
 303 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
 304                 u32 offset)
 305 {
 306         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 307         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 308
 309         return readl_relaxed(msm_host->core_mem + offset);
 310 }
 311
 312 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
 313                 u32 offset)
 314 {
 315         return readl_relaxed(host->ioaddr + offset);
 316 }
 317
 318 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
 319                 struct sdhci_host *host, u32 offset)
 320 {
 321         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 322         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 323
 324         writel_relaxed(val, msm_host->core_mem + offset);
 325 }
 326
 327 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
 328                 struct sdhci_host *host, u32 offset)
 329 {
 330         writel_relaxed(val, host->ioaddr + offset);
 331 }
 332
 333 static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host)
 334 {
 335         struct mmc_ios ios = host->mmc->ios;
 336         /*
 337          * The SDHC requires internal clock frequency to be double the
 338          * actual clock that will be set for DDR mode. The controller
 339          * uses the faster clock(100/400MHz) for some of its parts and
 340          * send the actual required clock (50/200MHz) to the card.
 341          */
 342         if (ios.timing == MMC_TIMING_UHS_DDR50 ||
 343             ios.timing == MMC_TIMING_MMC_DDR52 ||
 344             ios.timing == MMC_TIMING_MMC_HS400 ||
 345             host->flags & SDHCI_HS400_TUNING)
 346                 return 2;
 347         return 1;
 348 }
 349
 350 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
 351                                             unsigned int clock)
 352 {
 353         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 354         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 355         struct mmc_ios curr_ios = host->mmc->ios;
 356         struct clk *core_clk = msm_host->bulk_clks[0].clk;
 357         unsigned long achieved_rate;
 358         unsigned int desired_rate;
 359         unsigned int mult;
 360         int rc;
 361
 362         mult = msm_get_clock_mult_for_bus_mode(host);
 363         desired_rate = clock * mult;
 364         rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate);
 365         if (rc) {
 366                 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
 367                        mmc_hostname(host->mmc), desired_rate, curr_ios.timing);
 368                 return;
 369         }
 370
 371         /*
 372          * Qualcomm clock drivers by default round clock _up_ if they can't
 373          * make the requested rate.  This is not good for SD.  Yell if we
 374          * encounter it.
 375          */
 376         achieved_rate = clk_get_rate(core_clk);
 377         if (achieved_rate > desired_rate)
 378                 pr_warn("%s: Card appears overclocked; req %u Hz, actual %lu Hz\n",
 379                         mmc_hostname(host->mmc), desired_rate, achieved_rate);
 380         host->mmc->actual_clock = achieved_rate / mult;
 381
 382         /* Stash the rate we requested to use in sdhci_msm_runtime_resume() */
 383         msm_host->clk_rate = desired_rate;
 384
 385         pr_debug("%s: Setting clock at rate %lu at timing %d\n",
 386                  mmc_hostname(host->mmc), achieved_rate, curr_ios.timing);
 387 }
 388
 389 /* Platform specific tuning */
 390 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
 391 {
 392         u32 wait_cnt = 50;
 393         u8 ck_out_en;
 394         struct mmc_host *mmc = host->mmc;
 395         const struct sdhci_msm_offset *msm_offset =
 396                                         sdhci_priv_msm_offset(host);
 397
 398         /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
 399         ck_out_en = !!(readl_relaxed(host->ioaddr +
 400                         msm_offset->core_dll_config) & CORE_CK_OUT_EN);
 401
 402         while (ck_out_en != poll) {
 403                 if (--wait_cnt == 0) {
 404                         dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
 405                                mmc_hostname(mmc), poll);
 406                         return -ETIMEDOUT;
 407                 }
 408                 udelay(1);
 409
 410                 ck_out_en = !!(readl_relaxed(host->ioaddr +
 411                         msm_offset->core_dll_config) & CORE_CK_OUT_EN);
 412         }
 413
 414         return 0;
 415 }
 416
 417 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 418 {
 419         int rc;
 420         static const u8 grey_coded_phase_table[] = {
 421                 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
 422                 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
 423         };
 424         unsigned long flags;
 425         u32 config;
 426         struct mmc_host *mmc = host->mmc;
 427         const struct sdhci_msm_offset *msm_offset =
 428                                         sdhci_priv_msm_offset(host);
 429
 430         if (phase > 0xf)
 431                 return -EINVAL;
 432
 433         spin_lock_irqsave(&host->lock, flags);
 434
 435         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 436         config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
 437         config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
 438         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 439
 440         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
 441         rc = msm_dll_poll_ck_out_en(host, 0);
 442         if (rc)
 443                 goto err_out;
 444
 445         /*
 446          * Write the selected DLL clock output phase (0 ... 15)
 447          * to CDR_SELEXT bit field of DLL_CONFIG register.
 448          */
 449         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 450         config &= ~CDR_SELEXT_MASK;
 451         config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
 452         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 453
 454         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 455         config |= CORE_CK_OUT_EN;
 456         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 457
 458         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
 459         rc = msm_dll_poll_ck_out_en(host, 1);
 460         if (rc)
 461                 goto err_out;
 462
 463         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 464         config |= CORE_CDR_EN;
 465         config &= ~CORE_CDR_EXT_EN;
 466         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 467         goto out;
 468
 469 err_out:
 470         dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
 471                mmc_hostname(mmc), phase);
 472 out:
 473         spin_unlock_irqrestore(&host->lock, flags);
 474         return rc;
 475 }
 476
 477 /*
 478  * Find out the greatest range of consecuitive selected
 479  * DLL clock output phases that can be used as sampling
 480  * setting for SD3.0 UHS-I card read operation (in SDR104
 481  * timing mode) or for eMMC4.5 card read operation (in
 482  * HS400/HS200 timing mode).
 483  * Select the 3/4 of the range and configure the DLL with the
 484  * selected DLL clock output phase.
 485  */
 486
 487 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
 488                                            u8 *phase_table, u8 total_phases)
 489 {
 490         int ret;
 491         u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
 492         u8 phases_per_row[MAX_PHASES] = { 0 };
 493         int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
 494         int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
 495         bool phase_0_found = false, phase_15_found = false;
 496         struct mmc_host *mmc = host->mmc;
 497
 498         if (!total_phases || (total_phases > MAX_PHASES)) {
 499                 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
 500                        mmc_hostname(mmc), total_phases);
 501                 return -EINVAL;
 502         }
 503
 504         for (cnt = 0; cnt < total_phases; cnt++) {
 505                 ranges[row_index][col_index] = phase_table[cnt];
 506                 phases_per_row[row_index] += 1;
 507                 col_index++;
 508
 509                 if ((cnt + 1) == total_phases) {
 510                         continue;
 511                 /* check if next phase in phase_table is consecutive or not */
 512                 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
 513                         row_index++;
 514                         col_index = 0;
 515                 }
 516         }
 517
 518         if (row_index >= MAX_PHASES)
 519                 return -EINVAL;
 520
 521         /* Check if phase-0 is present in first valid window? */
 522         if (!ranges[0][0]) {
 523                 phase_0_found = true;
 524                 phase_0_raw_index = 0;
 525                 /* Check if cycle exist between 2 valid windows */
 526                 for (cnt = 1; cnt <= row_index; cnt++) {
 527                         if (phases_per_row[cnt]) {
 528                                 for (i = 0; i < phases_per_row[cnt]; i++) {
 529                                         if (ranges[cnt][i] == 15) {
 530                                                 phase_15_found = true;
 531                                                 phase_15_raw_index = cnt;
 532                                                 break;
 533                                         }
 534                                 }
 535                         }
 536                 }
 537         }
 538
 539         /* If 2 valid windows form cycle then merge them as single window */
 540         if (phase_0_found && phase_15_found) {
 541                 /* number of phases in raw where phase 0 is present */
 542                 u8 phases_0 = phases_per_row[phase_0_raw_index];
 543                 /* number of phases in raw where phase 15 is present */
 544                 u8 phases_15 = phases_per_row[phase_15_raw_index];
 545
 546                 if (phases_0 + phases_15 >= MAX_PHASES)
 547                         /*
 548                          * If there are more than 1 phase windows then total
 549                          * number of phases in both the windows should not be
 550                          * more than or equal to MAX_PHASES.
 551                          */
 552                         return -EINVAL;
 553
 554                 /* Merge 2 cyclic windows */
 555                 i = phases_15;
 556                 for (cnt = 0; cnt < phases_0; cnt++) {
 557                         ranges[phase_15_raw_index][i] =
 558                             ranges[phase_0_raw_index][cnt];
 559                         if (++i >= MAX_PHASES)
 560                                 break;
 561                 }
 562
 563                 phases_per_row[phase_0_raw_index] = 0;
 564                 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
 565         }
 566
 567         for (cnt = 0; cnt <= row_index; cnt++) {
 568                 if (phases_per_row[cnt] > curr_max) {
 569                         curr_max = phases_per_row[cnt];
 570                         selected_row_index = cnt;
 571                 }
 572         }
 573
 574         i = (curr_max * 3) / 4;
 575         if (i)
 576                 i--;
 577
 578         ret = ranges[selected_row_index][i];
 579
 580         if (ret >= MAX_PHASES) {
 581                 ret = -EINVAL;
 582                 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
 583                        mmc_hostname(mmc), ret);
 584         }
 585
 586         return ret;
 587 }
 588
 589 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
 590 {
 591         u32 mclk_freq = 0, config;
 592         const struct sdhci_msm_offset *msm_offset =
 593                                         sdhci_priv_msm_offset(host);
 594
 595         /* Program the MCLK value to MCLK_FREQ bit field */
 596         if (host->clock <= 112000000)
 597                 mclk_freq = 0;
 598         else if (host->clock <= 125000000)
 599                 mclk_freq = 1;
 600         else if (host->clock <= 137000000)
 601                 mclk_freq = 2;
 602         else if (host->clock <= 150000000)
 603                 mclk_freq = 3;
 604         else if (host->clock <= 162000000)
 605                 mclk_freq = 4;
 606         else if (host->clock <= 175000000)
 607                 mclk_freq = 5;
 608         else if (host->clock <= 187000000)
 609                 mclk_freq = 6;
 610         else if (host->clock <= 200000000)
 611                 mclk_freq = 7;
 612
 613         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 614         config &= ~CMUX_SHIFT_PHASE_MASK;
 615         config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
 616         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 617 }
 618
 619 /* Initialize the DLL (Programmable Delay Line) */
 620 static int msm_init_cm_dll(struct sdhci_host *host)
 621 {
 622         struct mmc_host *mmc = host->mmc;
 623         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 624         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 625         int wait_cnt = 50;
 626         unsigned long flags, xo_clk = 0;
 627         u32 config;
 628         const struct sdhci_msm_offset *msm_offset =
 629                                         msm_host->offset;
 630
 631         if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
 632                 xo_clk = clk_get_rate(msm_host->xo_clk);
 633
 634         spin_lock_irqsave(&host->lock, flags);
 635
 636         /*
 637          * Make sure that clock is always enabled when DLL
 638          * tuning is in progress. Keeping PWRSAVE ON may
 639          * turn off the clock.
 640          */
 641         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 642         config &= ~CORE_CLK_PWRSAVE;
 643         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 644
 645         if (msm_host->dll_config)
 646                 writel_relaxed(msm_host->dll_config,
 647                                 host->ioaddr + msm_offset->core_dll_config);
 648
 649         if (msm_host->use_14lpp_dll_reset) {
 650                 config = readl_relaxed(host->ioaddr +
 651                                 msm_offset->core_dll_config);
 652                 config &= ~CORE_CK_OUT_EN;
 653                 writel_relaxed(config, host->ioaddr +
 654                                 msm_offset->core_dll_config);
 655
 656                 config = readl_relaxed(host->ioaddr +
 657                                 msm_offset->core_dll_config_2);
 658                 config |= CORE_DLL_CLOCK_DISABLE;
 659                 writel_relaxed(config, host->ioaddr +
 660                                 msm_offset->core_dll_config_2);
 661         }
 662
 663         config = readl_relaxed(host->ioaddr +
 664                         msm_offset->core_dll_config);
 665         config |= CORE_DLL_RST;
 666         writel_relaxed(config, host->ioaddr +
 667                         msm_offset->core_dll_config);
 668
 669         config = readl_relaxed(host->ioaddr +
 670                         msm_offset->core_dll_config);
 671         config |= CORE_DLL_PDN;
 672         writel_relaxed(config, host->ioaddr +
 673                         msm_offset->core_dll_config);
 674
 675         if (!msm_host->dll_config)
 676                 msm_cm_dll_set_freq(host);
 677
 678         if (msm_host->use_14lpp_dll_reset &&
 679             !IS_ERR_OR_NULL(msm_host->xo_clk)) {
 680                 u32 mclk_freq = 0;
 681
 682                 config = readl_relaxed(host->ioaddr +
 683                                 msm_offset->core_dll_config_2);
 684                 config &= CORE_FLL_CYCLE_CNT;
 685                 if (config)
 686                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
 687                                         xo_clk);
 688                 else
 689                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
 690                                         xo_clk);
 691
 692                 config = readl_relaxed(host->ioaddr +
 693                                 msm_offset->core_dll_config_2);
 694                 config &= ~(0xFF << 10);
 695                 config |= mclk_freq << 10;
 696
 697                 writel_relaxed(config, host->ioaddr +
 698                                 msm_offset->core_dll_config_2);
 699                 /* wait for 5us before enabling DLL clock */
 700                 udelay(5);
 701         }
 702
 703         config = readl_relaxed(host->ioaddr +
 704                         msm_offset->core_dll_config);
 705         config &= ~CORE_DLL_RST;
 706         writel_relaxed(config, host->ioaddr +
 707                         msm_offset->core_dll_config);
 708
 709         config = readl_relaxed(host->ioaddr +
 710                         msm_offset->core_dll_config);
 711         config &= ~CORE_DLL_PDN;
 712         writel_relaxed(config, host->ioaddr +
 713                         msm_offset->core_dll_config);
 714
 715         if (msm_host->use_14lpp_dll_reset) {
 716                 if (!msm_host->dll_config)
 717                         msm_cm_dll_set_freq(host);
 718                 config = readl_relaxed(host->ioaddr +
 719                                 msm_offset->core_dll_config_2);
 720                 config &= ~CORE_DLL_CLOCK_DISABLE;
 721                 writel_relaxed(config, host->ioaddr +
 722                                 msm_offset->core_dll_config_2);
 723         }
 724
 725         /*
 726          * Configure DLL user control register to enable DLL status.
 727          * This setting is applicable to SDCC v5.1 onwards only.
 728          */
 729         if (msm_host->uses_tassadar_dll) {
 730                 config = DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN |
 731                         ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL;
 732                 writel_relaxed(config, host->ioaddr +
 733                                 msm_offset->core_dll_usr_ctl);
 734
 735                 config = readl_relaxed(host->ioaddr +
 736                                 msm_offset->core_dll_config_3);
 737                 config &= ~0xFF;
 738                 if (msm_host->clk_rate < 150000000)
 739                         config |= DLL_CONFIG_3_LOW_FREQ_VAL;
 740                 else
 741                         config |= DLL_CONFIG_3_HIGH_FREQ_VAL;
 742                 writel_relaxed(config, host->ioaddr +
 743                         msm_offset->core_dll_config_3);
 744         }
 745
 746         config = readl_relaxed(host->ioaddr +
 747                         msm_offset->core_dll_config);
 748         config |= CORE_DLL_EN;
 749         writel_relaxed(config, host->ioaddr +
 750                         msm_offset->core_dll_config);
 751
 752         config = readl_relaxed(host->ioaddr +
 753                         msm_offset->core_dll_config);
 754         config |= CORE_CK_OUT_EN;
 755         writel_relaxed(config, host->ioaddr +
 756                         msm_offset->core_dll_config);
 757
 758         /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
 759         while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
 760                  CORE_DLL_LOCK)) {
 761                 /* max. wait for 50us sec for LOCK bit to be set */
 762                 if (--wait_cnt == 0) {
 763                         dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
 764                                mmc_hostname(mmc));
 765                         spin_unlock_irqrestore(&host->lock, flags);
 766                         return -ETIMEDOUT;
 767                 }
 768                 udelay(1);
 769         }
 770
 771         spin_unlock_irqrestore(&host->lock, flags);
 772         return 0;
 773 }
 774
 775 static void msm_hc_select_default(struct sdhci_host *host)
 776 {
 777         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 778         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 779         u32 config;
 780         const struct sdhci_msm_offset *msm_offset =
 781                                         msm_host->offset;
 782
 783         if (!msm_host->use_cdclp533) {
 784                 config = readl_relaxed(host->ioaddr +
 785                                 msm_offset->core_vendor_spec3);
 786                 config &= ~CORE_PWRSAVE_DLL;
 787                 writel_relaxed(config, host->ioaddr +
 788                                 msm_offset->core_vendor_spec3);
 789         }
 790
 791         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 792         config &= ~CORE_HC_MCLK_SEL_MASK;
 793         config |= CORE_HC_MCLK_SEL_DFLT;
 794         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 795
 796         /*
 797          * Disable HC_SELECT_IN to be able to use the UHS mode select
 798          * configuration from Host Control2 register for all other
 799          * modes.
 800          * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
 801          * in VENDOR_SPEC_FUNC
 802          */
 803         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 804         config &= ~CORE_HC_SELECT_IN_EN;
 805         config &= ~CORE_HC_SELECT_IN_MASK;
 806         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 807
 808         /*
 809          * Make sure above writes impacting free running MCLK are completed
 810          * before changing the clk_rate at GCC.
 811          */
 812         wmb();
 813 }
 814
 815 static void msm_hc_select_hs400(struct sdhci_host *host)
 816 {
 817         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 818         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 819         struct mmc_ios ios = host->mmc->ios;
 820         u32 config, dll_lock;
 821         int rc;
 822         const struct sdhci_msm_offset *msm_offset =
 823                                         msm_host->offset;
 824
 825         /* Select the divided clock (free running MCLK/2) */
 826         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 827         config &= ~CORE_HC_MCLK_SEL_MASK;
 828         config |= CORE_HC_MCLK_SEL_HS400;
 829
 830         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 831         /*
 832          * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
 833          * register
 834          */
 835         if ((msm_host->tuning_done || ios.enhanced_strobe) &&
 836             !msm_host->calibration_done) {
 837                 config = readl_relaxed(host->ioaddr +
 838                                 msm_offset->core_vendor_spec);
 839                 config |= CORE_HC_SELECT_IN_HS400;
 840                 config |= CORE_HC_SELECT_IN_EN;
 841                 writel_relaxed(config, host->ioaddr +
 842                                 msm_offset->core_vendor_spec);
 843         }
 844         if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
 845                 /*
 846                  * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
 847                  * core_dll_status to be set. This should get set
 848                  * within 15 us at 200 MHz.
 849                  */
 850                 rc = readl_relaxed_poll_timeout(host->ioaddr +
 851                                                 msm_offset->core_dll_status,
 852                                                 dll_lock,
 853                                                 (dll_lock &
 854                                                 (CORE_DLL_LOCK |
 855                                                 CORE_DDR_DLL_LOCK)), 10,
 856                                                 1000);
 857                 if (rc == -ETIMEDOUT)
 858                         pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
 859                                mmc_hostname(host->mmc), dll_lock);
 860         }
 861         /*
 862          * Make sure above writes impacting free running MCLK are completed
 863          * before changing the clk_rate at GCC.
 864          */
 865         wmb();
 866 }
 867
 868 /*
 869  * sdhci_msm_hc_select_mode :- In general all timing modes are
 870  * controlled via UHS mode select in Host Control2 register.
 871  * eMMC specific HS200/HS400 doesn't have their respective modes
 872  * defined here, hence we use these values.
 873  *
 874  * HS200 - SDR104 (Since they both are equivalent in functionality)
 875  * HS400 - This involves multiple configurations
 876  *              Initially SDR104 - when tuning is required as HS200
 877  *              Then when switching to DDR @ 400MHz (HS400) we use
 878  *              the vendor specific HC_SELECT_IN to control the mode.
 879  *
 880  * In addition to controlling the modes we also need to select the
 881  * correct input clock for DLL depending on the mode.
 882  *
 883  * HS400 - divided clock (free running MCLK/2)
 884  * All other modes - default (free running MCLK)
 885  */
 886 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
 887 {
 888         struct mmc_ios ios = host->mmc->ios;
 889
 890         if (ios.timing == MMC_TIMING_MMC_HS400 ||
 891             host->flags & SDHCI_HS400_TUNING)
 892                 msm_hc_select_hs400(host);
 893         else
 894                 msm_hc_select_default(host);
 895 }
 896
 897 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
 898 {
 899         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 900         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 901         u32 config, calib_done;
 902         int ret;
 903         const struct sdhci_msm_offset *msm_offset =
 904                                         msm_host->offset;
 905
 906         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 907
 908         /*
 909          * Retuning in HS400 (DDR mode) will fail, just reset the
 910          * tuning block and restore the saved tuning phase.
 911          */
 912         ret = msm_init_cm_dll(host);
 913         if (ret)
 914                 goto out;
 915
 916         /* Set the selected phase in delay line hw block */
 917         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
 918         if (ret)
 919                 goto out;
 920
 921         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 922         config |= CORE_CMD_DAT_TRACK_SEL;
 923         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 924
 925         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 926         config &= ~CORE_CDC_T4_DLY_SEL;
 927         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 928
 929         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 930         config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
 931         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 932
 933         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 934         config |= CORE_CDC_SWITCH_RC_EN;
 935         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 936
 937         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 938         config &= ~CORE_START_CDC_TRAFFIC;
 939         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 940
 941         /* Perform CDC Register Initialization Sequence */
 942
 943         writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 944         writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
 945         writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 946         writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
 947         writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
 948         writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
 949         writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
 950         writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
 951         writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
 952
 953         /* CDC HW Calibration */
 954
 955         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 956         config |= CORE_SW_TRIG_FULL_CALIB;
 957         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 958
 959         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 960         config &= ~CORE_SW_TRIG_FULL_CALIB;
 961         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 962
 963         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 964         config |= CORE_HW_AUTOCAL_ENA;
 965         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 966
 967         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 968         config |= CORE_TIMER_ENA;
 969         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 970
 971         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
 972                                          calib_done,
 973                                          (calib_done & CORE_CALIBRATION_DONE),
 974                                          1, 50);
 975
 976         if (ret == -ETIMEDOUT) {
 977                 pr_err("%s: %s: CDC calibration was not completed\n",
 978                        mmc_hostname(host->mmc), __func__);
 979                 goto out;
 980         }
 981
 982         ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
 983                         & CORE_CDC_ERROR_CODE_MASK;
 984         if (ret) {
 985                 pr_err("%s: %s: CDC error code %d\n",
 986                        mmc_hostname(host->mmc), __func__, ret);
 987                 ret = -EINVAL;
 988                 goto out;
 989         }
 990
 991         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 992         config |= CORE_START_CDC_TRAFFIC;
 993         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 994 out:
 995         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 996                  __func__, ret);
 997         return ret;
 998 }
 999
1000 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
1001 {
1002         struct mmc_host *mmc = host->mmc;
1003         u32 dll_status, config, ddr_cfg_offset;
1004         int ret;
1005         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1006         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1007         const struct sdhci_msm_offset *msm_offset =
1008                                         sdhci_priv_msm_offset(host);
1009
1010         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1011
1012         /*
1013          * Currently the core_ddr_config register defaults to desired
1014          * configuration on reset. Currently reprogramming the power on
1015          * reset (POR) value in case it might have been modified by
1016          * bootloaders. In the future, if this changes, then the desired
1017          * values will need to be programmed appropriately.
1018          */
1019         if (msm_host->updated_ddr_cfg)
1020                 ddr_cfg_offset = msm_offset->core_ddr_config;
1021         else
1022                 ddr_cfg_offset = msm_offset->core_ddr_config_old;
1023         writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
1024
1025         if (mmc->ios.enhanced_strobe) {
1026                 config = readl_relaxed(host->ioaddr +
1027                                 msm_offset->core_ddr_200_cfg);
1028                 config |= CORE_CMDIN_RCLK_EN;
1029                 writel_relaxed(config, host->ioaddr +
1030                                 msm_offset->core_ddr_200_cfg);
1031         }
1032
1033         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
1034         config |= CORE_DDR_CAL_EN;
1035         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
1036
1037         ret = readl_relaxed_poll_timeout(host->ioaddr +
1038                                         msm_offset->core_dll_status,
1039                                         dll_status,
1040                                         (dll_status & CORE_DDR_DLL_LOCK),
1041                                         10, 1000);
1042
1043         if (ret == -ETIMEDOUT) {
1044                 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
1045                        mmc_hostname(host->mmc), __func__);
1046                 goto out;
1047         }
1048
1049         /*
1050          * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
1051          * When MCLK is gated OFF, it is not gated for less than 0.5us
1052          * and MCLK must be switched on for at-least 1us before DATA
1053          * starts coming. Controllers with 14lpp and later tech DLL cannot
1054          * guarantee above requirement. So PWRSAVE_DLL should not be
1055          * turned on for host controllers using this DLL.
1056          */
1057         if (!msm_host->use_14lpp_dll_reset) {
1058                 config = readl_relaxed(host->ioaddr +
1059                                 msm_offset->core_vendor_spec3);
1060                 config |= CORE_PWRSAVE_DLL;
1061                 writel_relaxed(config, host->ioaddr +
1062                                 msm_offset->core_vendor_spec3);
1063         }
1064
1065         /*
1066          * Drain writebuffer to ensure above DLL calibration
1067          * and PWRSAVE DLL is enabled.
1068          */
1069         wmb();
1070 out:
1071         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1072                  __func__, ret);
1073         return ret;
1074 }
1075
1076 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
1077 {
1078         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1079         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1080         struct mmc_host *mmc = host->mmc;
1081         int ret;
1082         u32 config;
1083         const struct sdhci_msm_offset *msm_offset =
1084                                         msm_host->offset;
1085
1086         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1087
1088         /*
1089          * Retuning in HS400 (DDR mode) will fail, just reset the
1090          * tuning block and restore the saved tuning phase.
1091          */
1092         ret = msm_init_cm_dll(host);
1093         if (ret)
1094                 goto out;
1095
1096         if (!mmc->ios.enhanced_strobe) {
1097                 /* Set the selected phase in delay line hw block */
1098                 ret = msm_config_cm_dll_phase(host,
1099                                               msm_host->saved_tuning_phase);
1100                 if (ret)
1101                         goto out;
1102                 config = readl_relaxed(host->ioaddr +
1103                                 msm_offset->core_dll_config);
1104                 config |= CORE_CMD_DAT_TRACK_SEL;
1105                 writel_relaxed(config, host->ioaddr +
1106                                 msm_offset->core_dll_config);
1107         }
1108
1109         if (msm_host->use_cdclp533)
1110                 ret = sdhci_msm_cdclp533_calibration(host);
1111         else
1112                 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1113 out:
1114         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1115                  __func__, ret);
1116         return ret;
1117 }
1118
1119 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1120 {
1121         struct mmc_ios *ios = &host->mmc->ios;
1122
1123         /*
1124          * Tuning is required for SDR104, HS200 and HS400 cards and
1125          * if clock frequency is greater than 100MHz in these modes.
1126          */
1127         if (host->clock <= CORE_FREQ_100MHZ ||
1128             !(ios->timing == MMC_TIMING_MMC_HS400 ||
1129             ios->timing == MMC_TIMING_MMC_HS200 ||
1130             ios->timing == MMC_TIMING_UHS_SDR104) ||
1131             ios->enhanced_strobe)
1132                 return false;
1133
1134         return true;
1135 }
1136
1137 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1138 {
1139         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1140         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1141         int ret;
1142
1143         /*
1144          * SDR DLL comes into picture only for timing modes which needs
1145          * tuning.
1146          */
1147         if (!sdhci_msm_is_tuning_needed(host))
1148                 return 0;
1149
1150         /* Reset the tuning block */
1151         ret = msm_init_cm_dll(host);
1152         if (ret)
1153                 return ret;
1154
1155         /* Restore the tuning block */
1156         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1157
1158         return ret;
1159 }
1160
1161 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1162 {
1163         const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1164         u32 config, oldconfig = readl_relaxed(host->ioaddr +
1165                                               msm_offset->core_dll_config);
1166
1167         config = oldconfig;
1168         if (enable) {
1169                 config |= CORE_CDR_EN;
1170                 config &= ~CORE_CDR_EXT_EN;
1171         } else {
1172                 config &= ~CORE_CDR_EN;
1173                 config |= CORE_CDR_EXT_EN;
1174         }
1175
1176         if (config != oldconfig) {
1177                 writel_relaxed(config, host->ioaddr +
1178                                msm_offset->core_dll_config);
1179         }
1180 }
1181
1182 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1183 {
1184         struct sdhci_host *host = mmc_priv(mmc);
1185         int tuning_seq_cnt = 10;
1186         u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1187         int rc;
1188         struct mmc_ios ios = host->mmc->ios;
1189         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1190         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1191
1192         if (!sdhci_msm_is_tuning_needed(host)) {
1193                 msm_host->use_cdr = false;
1194                 sdhci_msm_set_cdr(host, false);
1195                 return 0;
1196         }
1197
1198         /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1199         msm_host->use_cdr = true;
1200
1201         /*
1202          * Clear tuning_done flag before tuning to ensure proper
1203          * HS400 settings.
1204          */
1205         msm_host->tuning_done = 0;
1206
1207         /*
1208          * For HS400 tuning in HS200 timing requires:
1209          * - select MCLK/2 in VENDOR_SPEC
1210          * - program MCLK to 400MHz (or nearest supported) in GCC
1211          */
1212         if (host->flags & SDHCI_HS400_TUNING) {
1213                 sdhci_msm_hc_select_mode(host);
1214                 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1215                 host->flags &= ~SDHCI_HS400_TUNING;
1216         }
1217
1218 retry:
1219         /* First of all reset the tuning block */
1220         rc = msm_init_cm_dll(host);
1221         if (rc)
1222                 return rc;
1223
1224         phase = 0;
1225         do {
1226                 /* Set the phase in delay line hw block */
1227                 rc = msm_config_cm_dll_phase(host, phase);
1228                 if (rc)
1229                         return rc;
1230
1231                 rc = mmc_send_tuning(mmc, opcode, NULL);
1232                 if (!rc) {
1233                         /* Tuning is successful at this tuning point */
1234                         tuned_phases[tuned_phase_cnt++] = phase;
1235                         dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1236                                  mmc_hostname(mmc), phase);
1237                 }
1238         } while (++phase < ARRAY_SIZE(tuned_phases));
1239
1240         if (tuned_phase_cnt) {
1241                 if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) {
1242                         /*
1243                          * All phases valid is _almost_ as bad as no phases
1244                          * valid.  Probably all phases are not really reliable
1245                          * but we didn't detect where the unreliable place is.
1246                          * That means we'll essentially be guessing and hoping
1247                          * we get a good phase.  Better to try a few times.
1248                          */
1249                         dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n",
1250                                 mmc_hostname(mmc));
1251                         if (--tuning_seq_cnt) {
1252                                 tuned_phase_cnt = 0;
1253                                 goto retry;
1254                         }
1255                 }
1256
1257                 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1258                                                      tuned_phase_cnt);
1259                 if (rc < 0)
1260                         return rc;
1261                 else
1262                         phase = rc;
1263
1264                 /*
1265                  * Finally set the selected phase in delay
1266                  * line hw block.
1267                  */
1268                 rc = msm_config_cm_dll_phase(host, phase);
1269                 if (rc)
1270                         return rc;
1271                 msm_host->saved_tuning_phase = phase;
1272                 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1273                          mmc_hostname(mmc), phase);
1274         } else {
1275                 if (--tuning_seq_cnt)
1276                         goto retry;
1277                 /* Tuning failed */
1278                 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1279                        mmc_hostname(mmc));
1280                 rc = -EIO;
1281         }
1282
1283         if (!rc)
1284                 msm_host->tuning_done = true;
1285         return rc;
1286 }
1287
1288 /*
1289  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1290  * This needs to be done for both tuning and enhanced_strobe mode.
1291  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1292  * fixed feedback clock is used.
1293  */
1294 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1295 {
1296         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1297         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1298         int ret;
1299
1300         if (host->clock > CORE_FREQ_100MHZ &&
1301             (msm_host->tuning_done || ios->enhanced_strobe) &&
1302             !msm_host->calibration_done) {
1303                 ret = sdhci_msm_hs400_dll_calibration(host);
1304                 if (!ret)
1305                         msm_host->calibration_done = true;
1306                 else
1307                         pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1308                                mmc_hostname(host->mmc), ret);
1309         }
1310 }
1311
1312 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1313                                         unsigned int uhs)
1314 {
1315         struct mmc_host *mmc = host->mmc;
1316         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1317         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1318         u16 ctrl_2;
1319         u32 config;
1320         const struct sdhci_msm_offset *msm_offset =
1321                                         msm_host->offset;
1322
1323         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1324         /* Select Bus Speed Mode for host */
1325         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1326         switch (uhs) {
1327         case MMC_TIMING_UHS_SDR12:
1328                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1329                 break;
1330         case MMC_TIMING_UHS_SDR25:
1331                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1332                 break;
1333         case MMC_TIMING_UHS_SDR50:
1334                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1335                 break;
1336         case MMC_TIMING_MMC_HS400:
1337         case MMC_TIMING_MMC_HS200:
1338         case MMC_TIMING_UHS_SDR104:
1339                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1340                 break;
1341         case MMC_TIMING_UHS_DDR50:
1342         case MMC_TIMING_MMC_DDR52:
1343                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1344                 break;
1345         }
1346
1347         /*
1348          * When clock frequency is less than 100MHz, the feedback clock must be
1349          * provided and DLL must not be used so that tuning can be skipped. To
1350          * provide feedback clock, the mode selection can be any value less
1351          * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1352          */
1353         if (host->clock <= CORE_FREQ_100MHZ) {
1354                 if (uhs == MMC_TIMING_MMC_HS400 ||
1355                     uhs == MMC_TIMING_MMC_HS200 ||
1356                     uhs == MMC_TIMING_UHS_SDR104)
1357                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1358                 /*
1359                  * DLL is not required for clock <= 100MHz
1360                  * Thus, make sure DLL it is disabled when not required
1361                  */
1362                 config = readl_relaxed(host->ioaddr +
1363                                 msm_offset->core_dll_config);
1364                 config |= CORE_DLL_RST;
1365                 writel_relaxed(config, host->ioaddr +
1366                                 msm_offset->core_dll_config);
1367
1368                 config = readl_relaxed(host->ioaddr +
1369                                 msm_offset->core_dll_config);
1370                 config |= CORE_DLL_PDN;
1371                 writel_relaxed(config, host->ioaddr +
1372                                 msm_offset->core_dll_config);
1373
1374                 /*
1375                  * The DLL needs to be restored and CDCLP533 recalibrated
1376                  * when the clock frequency is set back to 400MHz.
1377                  */
1378                 msm_host->calibration_done = false;
1379         }
1380
1381         dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1382                 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1383         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1384
1385         if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1386                 sdhci_msm_hs400(host, &mmc->ios);
1387 }
1388
1389 static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
1390 {
1391         struct platform_device *pdev = msm_host->pdev;
1392         int ret;
1393
1394         if (level)
1395                 ret = pinctrl_pm_select_default_state(&pdev->dev);
1396         else
1397                 ret = pinctrl_pm_select_sleep_state(&pdev->dev);
1398
1399         return ret;
1400 }
1401
1402 static int sdhci_msm_set_vmmc(struct mmc_host *mmc)
1403 {
1404         if (IS_ERR(mmc->supply.vmmc))
1405                 return 0;
1406
1407         return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd);
1408 }
1409
1410 static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,
1411                               struct mmc_host *mmc, bool level)
1412 {
1413         int ret;
1414         struct mmc_ios ios;
1415
1416         if (msm_host->vqmmc_enabled == level)
1417                 return 0;
1418
1419         if (level) {
1420                 /* Set the IO voltage regulator to default voltage level */
1421                 if (msm_host->caps_0 & CORE_3_0V_SUPPORT)
1422                         ios.signal_voltage = MMC_SIGNAL_VOLTAGE_330;
1423                 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)
1424                         ios.signal_voltage = MMC_SIGNAL_VOLTAGE_180;
1425
1426                 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1427                         ret = mmc_regulator_set_vqmmc(mmc, &ios);
1428                         if (ret < 0) {
1429                                 dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n",
1430                                         mmc_hostname(mmc), ret);
1431                                 goto out;
1432                         }
1433                 }
1434                 ret = regulator_enable(mmc->supply.vqmmc);
1435         } else {
1436                 ret = regulator_disable(mmc->supply.vqmmc);
1437         }
1438
1439         if (ret)
1440                 dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n",
1441                         mmc_hostname(mmc), level ? "en":"dis", ret);
1442         else
1443                 msm_host->vqmmc_enabled = level;
1444 out:
1445         return ret;
1446 }
1447
1448 static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,
1449                               struct mmc_host *mmc, bool hpm)
1450 {
1451         int load, ret;
1452
1453         load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0;
1454         ret = regulator_set_load(mmc->supply.vqmmc, load);
1455         if (ret)
1456                 dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n",
1457                         mmc_hostname(mmc), ret);
1458         return ret;
1459 }
1460
1461 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,
1462                               struct mmc_host *mmc, bool level)
1463 {
1464         int ret;
1465         bool always_on;
1466
1467         if (IS_ERR(mmc->supply.vqmmc) ||
1468                         (mmc->ios.power_mode == MMC_POWER_UNDEFINED))
1469                 return 0;
1470         /*
1471          * For eMMC don't turn off Vqmmc, Instead just configure it in LPM
1472          * and HPM modes by setting the corresponding load.
1473          *
1474          * Till eMMC is initialized (i.e. always_on == 0), just turn on/off
1475          * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off
1476          * gets invoked. Once eMMC is initialized (i.e. always_on == 1),
1477          * Vqmmc should remain ON, So just set the load instead of turning it
1478          * off/on.
1479          */
1480         always_on = !mmc_card_is_removable(mmc) &&
1481                         mmc->card && mmc_card_mmc(mmc->card);
1482
1483         if (always_on)
1484                 ret = msm_config_vqmmc_mode(msm_host, mmc, level);
1485         else
1486                 ret = msm_toggle_vqmmc(msm_host, mmc, level);
1487
1488         return ret;
1489 }
1490
1491 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1492 {
1493         init_waitqueue_head(&msm_host->pwr_irq_wait);
1494 }
1495
1496 static inline void sdhci_msm_complete_pwr_irq_wait(
1497                 struct sdhci_msm_host *msm_host)
1498 {
1499         wake_up(&msm_host->pwr_irq_wait);
1500 }
1501
1502 /*
1503  * sdhci_msm_check_power_status API should be called when registers writes
1504  * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1505  * To what state the register writes will change the IO lines should be passed
1506  * as the argument req_type. This API will check whether the IO line's state
1507  * is already the expected state and will wait for power irq only if
1508  * power irq is expected to be triggered based on the current IO line state
1509  * and expected IO line state.
1510  */
1511 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1512 {
1513         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1514         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1515         bool done = false;
1516         u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1517         const struct sdhci_msm_offset *msm_offset =
1518                                         msm_host->offset;
1519
1520         pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1521                         mmc_hostname(host->mmc), __func__, req_type,
1522                         msm_host->curr_pwr_state, msm_host->curr_io_level);
1523
1524         /*
1525          * The power interrupt will not be generated for signal voltage
1526          * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1527          * Since sdhci-msm-v5, this bit has been removed and SW must consider
1528          * it as always set.
1529          */
1530         if (!msm_host->mci_removed)
1531                 val = msm_host_readl(msm_host, host,
1532                                 msm_offset->core_generics);
1533         if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1534             !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1535                 return;
1536         }
1537
1538         /*
1539          * The IRQ for request type IO High/LOW will be generated when -
1540          * there is a state change in 1.8V enable bit (bit 3) of
1541          * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1542          * which indicates 3.3V IO voltage. So, when MMC core layer tries
1543          * to set it to 3.3V before card detection happens, the
1544          * IRQ doesn't get triggered as there is no state change in this bit.
1545          * The driver already handles this case by changing the IO voltage
1546          * level to high as part of controller power up sequence. Hence, check
1547          * for host->pwr to handle a case where IO voltage high request is
1548          * issued even before controller power up.
1549          */
1550         if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1551                 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1552                                 mmc_hostname(host->mmc), req_type);
1553                 return;
1554         }
1555         if ((req_type & msm_host->curr_pwr_state) ||
1556                         (req_type & msm_host->curr_io_level))
1557                 done = true;
1558         /*
1559          * This is needed here to handle cases where register writes will
1560          * not change the current bus state or io level of the controller.
1561          * In this case, no power irq will be triggerred and we should
1562          * not wait.
1563          */
1564         if (!done) {
1565                 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1566                                 msm_host->pwr_irq_flag,
1567                                 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1568                         dev_warn(&msm_host->pdev->dev,
1569                                  "%s: pwr_irq for req: (%d) timed out\n",
1570                                  mmc_hostname(host->mmc), req_type);
1571         }
1572         pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1573                         __func__, req_type);
1574 }
1575
1576 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1577 {
1578         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1579         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1580         const struct sdhci_msm_offset *msm_offset =
1581                                         msm_host->offset;
1582
1583         pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1584                 mmc_hostname(host->mmc),
1585                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1586                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1587                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1588 }
1589
1590 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1591 {
1592         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1593         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1594         struct mmc_host *mmc = host->mmc;
1595         u32 irq_status, irq_ack = 0;
1596         int retry = 10, ret;
1597         u32 pwr_state = 0, io_level = 0;
1598         u32 config;
1599         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1600
1601         irq_status = msm_host_readl(msm_host, host,
1602                         msm_offset->core_pwrctl_status);
1603         irq_status &= INT_MASK;
1604
1605         msm_host_writel(msm_host, irq_status, host,
1606                         msm_offset->core_pwrctl_clear);
1607
1608         /*
1609          * There is a rare HW scenario where the first clear pulse could be
1610          * lost when actual reset and clear/read of status register is
1611          * happening at a time. Hence, retry for at least 10 times to make
1612          * sure status register is cleared. Otherwise, this will result in
1613          * a spurious power IRQ resulting in system instability.
1614          */
1615         while (irq_status & msm_host_readl(msm_host, host,
1616                                 msm_offset->core_pwrctl_status)) {
1617                 if (retry == 0) {
1618                         pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1619                                         mmc_hostname(host->mmc), irq_status);
1620                         sdhci_msm_dump_pwr_ctrl_regs(host);
1621                         WARN_ON(1);
1622                         break;
1623                 }
1624                 msm_host_writel(msm_host, irq_status, host,
1625                         msm_offset->core_pwrctl_clear);
1626                 retry--;
1627                 udelay(10);
1628         }
1629
1630         /* Handle BUS ON/OFF*/
1631         if (irq_status & CORE_PWRCTL_BUS_ON) {
1632                 pwr_state = REQ_BUS_ON;
1633                 io_level = REQ_IO_HIGH;
1634         }
1635         if (irq_status & CORE_PWRCTL_BUS_OFF) {
1636                 pwr_state = REQ_BUS_OFF;
1637                 io_level = REQ_IO_LOW;
1638         }
1639
1640         if (pwr_state) {
1641                 ret = sdhci_msm_set_vmmc(mmc);
1642                 if (!ret)
1643                         ret = sdhci_msm_set_vqmmc(msm_host, mmc,
1644                                         pwr_state & REQ_BUS_ON);
1645                 if (!ret)
1646                         ret = sdhci_msm_set_pincfg(msm_host,
1647                                         pwr_state & REQ_BUS_ON);
1648                 if (!ret)
1649                         irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1650                 else
1651                         irq_ack |= CORE_PWRCTL_BUS_FAIL;
1652         }
1653
1654         /* Handle IO LOW/HIGH */
1655         if (irq_status & CORE_PWRCTL_IO_LOW)
1656                 io_level = REQ_IO_LOW;
1657
1658         if (irq_status & CORE_PWRCTL_IO_HIGH)
1659                 io_level = REQ_IO_HIGH;
1660
1661         if (io_level)
1662                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1663
1664         if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) {
1665                 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
1666                 if (ret < 0) {
1667                         dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",
1668                                         mmc_hostname(mmc), ret,
1669                                         mmc->ios.signal_voltage, mmc->ios.vdd,
1670                                         irq_status);
1671                         irq_ack |= CORE_PWRCTL_IO_FAIL;
1672                 }
1673         }
1674
1675         /*
1676          * The driver has to acknowledge the interrupt, switch voltages and
1677          * report back if it succeded or not to this register. The voltage
1678          * switches are handled by the sdhci core, so just report success.
1679          */
1680         msm_host_writel(msm_host, irq_ack, host,
1681                         msm_offset->core_pwrctl_ctl);
1682
1683         /*
1684          * If we don't have info regarding the voltage levels supported by
1685          * regulators, don't change the IO PAD PWR SWITCH.
1686          */
1687         if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1688                 u32 new_config;
1689                 /*
1690                  * We should unset IO PAD PWR switch only if the register write
1691                  * can set IO lines high and the regulator also switches to 3 V.
1692                  * Else, we should keep the IO PAD PWR switch set.
1693                  * This is applicable to certain targets where eMMC vccq supply
1694                  * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1695                  * IO PAD PWR switch must be kept set to reflect actual
1696                  * regulator voltage. This way, during initialization of
1697                  * controllers with only 1.8V, we will set the IO PAD bit
1698                  * without waiting for a REQ_IO_LOW.
1699                  */
1700                 config = readl_relaxed(host->ioaddr +
1701                                 msm_offset->core_vendor_spec);
1702                 new_config = config;
1703
1704                 if ((io_level & REQ_IO_HIGH) &&
1705                                 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1706                         new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1707                 else if ((io_level & REQ_IO_LOW) ||
1708                                 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1709                         new_config |= CORE_IO_PAD_PWR_SWITCH;
1710
1711                 if (config ^ new_config)
1712                         writel_relaxed(new_config, host->ioaddr +
1713                                         msm_offset->core_vendor_spec);
1714         }
1715
1716         if (pwr_state)
1717                 msm_host->curr_pwr_state = pwr_state;
1718         if (io_level)
1719                 msm_host->curr_io_level = io_level;
1720
1721         dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1722                 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1723                 irq_ack);
1724 }
1725
1726 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1727 {
1728         struct sdhci_host *host = (struct sdhci_host *)data;
1729         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1730         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1731
1732         sdhci_msm_handle_pwr_irq(host, irq);
1733         msm_host->pwr_irq_flag = 1;
1734         sdhci_msm_complete_pwr_irq_wait(msm_host);
1735
1736
1737         return IRQ_HANDLED;
1738 }
1739
1740 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1741 {
1742         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1743         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1744         struct clk *core_clk = msm_host->bulk_clks[0].clk;
1745
1746         return clk_round_rate(core_clk, ULONG_MAX);
1747 }
1748
1749 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1750 {
1751         return SDHCI_MSM_MIN_CLOCK;
1752 }
1753
1754 /*
1755  * __sdhci_msm_set_clock - sdhci_msm clock control.
1756  *
1757  * Description:
1758  * MSM controller does not use internal divider and
1759  * instead directly control the GCC clock as per
1760  * HW recommendation.
1761  **/
1762 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1763 {
1764         u16 clk;
1765
1766         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1767
1768         if (clock == 0)
1769                 return;
1770
1771         /*
1772          * MSM controller do not use clock divider.
1773          * Thus read SDHCI_CLOCK_CONTROL and only enable
1774          * clock with no divider value programmed.
1775          */
1776         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1777         sdhci_enable_clk(host, clk);
1778 }
1779
1780 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1781 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1782 {
1783         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1784         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1785
1786         if (!clock) {
1787                 host->mmc->actual_clock = msm_host->clk_rate = 0;
1788                 goto out;
1789         }
1790
1791         sdhci_msm_hc_select_mode(host);
1792
1793         msm_set_clock_rate_for_bus_mode(host, clock);
1794 out:
1795         __sdhci_msm_set_clock(host, clock);
1796 }
1797
1798 /*****************************************************************************\
1799  *                                                                           *
1800  * Inline Crypto Engine (ICE) support                                        *
1801  *                                                                           *
1802 \*****************************************************************************/
1803
1804 #ifdef CONFIG_MMC_CRYPTO
1805
1806 #define AES_256_XTS_KEY_SIZE                    64
1807
1808 /* QCOM ICE registers */
1809
1810 #define QCOM_ICE_REG_VERSION                    0x0008
1811
1812 #define QCOM_ICE_REG_FUSE_SETTING               0x0010
1813 #define QCOM_ICE_FUSE_SETTING_MASK              0x1
1814 #define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK     0x2
1815 #define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK     0x4
1816
1817 #define QCOM_ICE_REG_BIST_STATUS                0x0070
1818 #define QCOM_ICE_BIST_STATUS_MASK               0xF0000000
1819
1820 #define QCOM_ICE_REG_ADVANCED_CONTROL           0x1000
1821
1822 #define sdhci_msm_ice_writel(host, val, reg)    \
1823         writel((val), (host)->ice_mem + (reg))
1824 #define sdhci_msm_ice_readl(host, reg)  \
1825         readl((host)->ice_mem + (reg))
1826
1827 static bool sdhci_msm_ice_supported(struct sdhci_msm_host *msm_host)
1828 {
1829         struct device *dev = mmc_dev(msm_host->mmc);
1830         u32 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_VERSION);
1831         int major = regval >> 24;
1832         int minor = (regval >> 16) & 0xFF;
1833         int step = regval & 0xFFFF;
1834
1835         /* For now this driver only supports ICE version 3. */
1836         if (major != 3) {
1837                 dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n",
1838                          major, minor, step);
1839                 return false;
1840         }
1841
1842         dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n",
1843                  major, minor, step);
1844
1845         /* If fuses are blown, ICE might not work in the standard way. */
1846         regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_FUSE_SETTING);
1847         if (regval & (QCOM_ICE_FUSE_SETTING_MASK |
1848                       QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK |
1849                       QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) {
1850                 dev_warn(dev, "Fuses are blown; ICE is unusable!\n");
1851                 return false;
1852         }
1853         return true;
1854 }
1855
1856 static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev)
1857 {
1858         return devm_clk_get(dev, "ice");
1859 }
1860
1861 static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
1862                               struct cqhci_host *cq_host)
1863 {
1864         struct mmc_host *mmc = msm_host->mmc;
1865         struct device *dev = mmc_dev(mmc);
1866         struct resource *res;
1867         int err;
1868
1869         if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
1870                 return 0;
1871
1872         res = platform_get_resource_byname(msm_host->pdev, IORESOURCE_MEM,
1873                                            "ice");
1874         if (!res) {
1875                 dev_warn(dev, "ICE registers not found\n");
1876                 goto disable;
1877         }
1878
1879         if (!qcom_scm_ice_available()) {
1880                 dev_warn(dev, "ICE SCM interface not found\n");
1881                 goto disable;
1882         }
1883
1884         msm_host->ice_mem = devm_ioremap_resource(dev, res);
1885         if (IS_ERR(msm_host->ice_mem)) {
1886                 err = PTR_ERR(msm_host->ice_mem);
1887                 dev_err(dev, "Failed to map ICE registers; err=%d\n", err);
1888                 return err;
1889         }
1890
1891         if (!sdhci_msm_ice_supported(msm_host))
1892                 goto disable;
1893
1894         mmc->caps2 |= MMC_CAP2_CRYPTO;
1895         return 0;
1896
1897 disable:
1898         dev_warn(dev, "Disabling inline encryption support\n");
1899         return 0;
1900 }
1901
1902 static void sdhci_msm_ice_low_power_mode_enable(struct sdhci_msm_host *msm_host)
1903 {
1904         u32 regval;
1905
1906         regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL);
1907         /*
1908          * Enable low power mode sequence
1909          * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0
1910          */
1911         regval |= 0x7000;
1912         sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
1913 }
1914
1915 static void sdhci_msm_ice_optimization_enable(struct sdhci_msm_host *msm_host)
1916 {
1917         u32 regval;
1918
1919         /* ICE Optimizations Enable Sequence */
1920         regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL);
1921         regval |= 0xD807100;
1922         /* ICE HPG requires delay before writing */
1923         udelay(5);
1924         sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
1925         udelay(5);
1926 }
1927
1928 /*
1929  * Wait until the ICE BIST (built-in self-test) has completed.
1930  *
1931  * This may be necessary before ICE can be used.
1932  *
1933  * Note that we don't really care whether the BIST passed or failed; we really
1934  * just want to make sure that it isn't still running.  This is because (a) the
1935  * BIST is a FIPS compliance thing that never fails in practice, (b) ICE is
1936  * documented to reject crypto requests if the BIST fails, so we needn't do it
1937  * in software too, and (c) properly testing storage encryption requires testing
1938  * the full storage stack anyway, and not relying on hardware-level self-tests.
1939  */
1940 static int sdhci_msm_ice_wait_bist_status(struct sdhci_msm_host *msm_host)
1941 {
1942         u32 regval;
1943         int err;
1944
1945         err = readl_poll_timeout(msm_host->ice_mem + QCOM_ICE_REG_BIST_STATUS,
1946                                  regval, !(regval & QCOM_ICE_BIST_STATUS_MASK),
1947                                  50, 5000);
1948         if (err)
1949                 dev_err(mmc_dev(msm_host->mmc),
1950                         "Timed out waiting for ICE self-test to complete\n");
1951         return err;
1952 }
1953
1954 static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
1955 {
1956         if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO))
1957                 return;
1958         sdhci_msm_ice_low_power_mode_enable(msm_host);
1959         sdhci_msm_ice_optimization_enable(msm_host);
1960         sdhci_msm_ice_wait_bist_status(msm_host);
1961 }
1962
1963 static int __maybe_unused sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
1964 {
1965         if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO))
1966                 return 0;
1967         return sdhci_msm_ice_wait_bist_status(msm_host);
1968 }
1969
1970 /*
1971  * Program a key into a QC ICE keyslot, or evict a keyslot.  QC ICE requires
1972  * vendor-specific SCM calls for this; it doesn't support the standard way.
1973  */
1974 static int sdhci_msm_program_key(struct cqhci_host *cq_host,
1975                                  const union cqhci_crypto_cfg_entry *cfg,
1976                                  int slot)
1977 {
1978         struct device *dev = mmc_dev(cq_host->mmc);
1979         union cqhci_crypto_cap_entry cap;
1980         union {
1981                 u8 bytes[AES_256_XTS_KEY_SIZE];
1982                 u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)];
1983         } key;
1984         int i;
1985         int err;
1986
1987         if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE))
1988                 return qcom_scm_ice_invalidate_key(slot);
1989
1990         /* Only AES-256-XTS has been tested so far. */
1991         cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx];
1992         if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS ||
1993             cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256) {
1994                 dev_err_ratelimited(dev,
1995                                     "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
1996                                     cap.algorithm_id, cap.key_size);
1997                 return -EINVAL;
1998         }
1999
2000         memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE);
2001
2002         /*
2003          * The SCM call byte-swaps the 32-bit words of the key.  So we have to
2004          * do the same, in order for the final key be correct.
2005          */
2006         for (i = 0; i < ARRAY_SIZE(key.words); i++)
2007                 __cpu_to_be32s(&key.words[i]);
2008
2009         err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE,
2010                                    QCOM_SCM_ICE_CIPHER_AES_256_XTS,
2011                                    cfg->data_unit_size);
2012         memzero_explicit(&key, sizeof(key));
2013         return err;
2014 }
2015 #else /* CONFIG_MMC_CRYPTO */
2016 static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev)
2017 {
2018         return NULL;
2019 }
2020
2021 static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
2022                                      struct cqhci_host *cq_host)
2023 {
2024         return 0;
2025 }
2026
2027 static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
2028 {
2029 }
2030
2031 static inline int __maybe_unused
2032 sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
2033 {
2034         return 0;
2035 }
2036 #endif /* !CONFIG_MMC_CRYPTO */
2037
2038 /*****************************************************************************\
2039  *                                                                           *
2040  * MSM Command Queue Engine (CQE)                                            *
2041  *                                                                           *
2042 \*****************************************************************************/
2043
2044 static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
2045 {
2046         int cmd_error = 0;
2047         int data_error = 0;
2048
2049         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
2050                 return intmask;
2051
2052         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
2053         return 0;
2054 }
2055
2056 static void sdhci_msm_cqe_enable(struct mmc_host *mmc)
2057 {
2058         struct sdhci_host *host = mmc_priv(mmc);
2059         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2060         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2061
2062         sdhci_cqe_enable(mmc);
2063         sdhci_msm_ice_enable(msm_host);
2064 }
2065
2066 static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
2067 {
2068         struct sdhci_host *host = mmc_priv(mmc);
2069         unsigned long flags;
2070         u32 ctrl;
2071
2072         /*
2073          * When CQE is halted, the legacy SDHCI path operates only
2074          * on 16-byte descriptors in 64bit mode.
2075          */
2076         if (host->flags & SDHCI_USE_64_BIT_DMA)
2077                 host->desc_sz = 16;
2078
2079         spin_lock_irqsave(&host->lock, flags);
2080
2081         /*
2082          * During CQE command transfers, command complete bit gets latched.
2083          * So s/w should clear command complete interrupt status when CQE is
2084          * either halted or disabled. Otherwise unexpected SDCHI legacy
2085          * interrupt gets triggered when CQE is halted/disabled.
2086          */
2087         ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
2088         ctrl |= SDHCI_INT_RESPONSE;
2089         sdhci_writel(host,  ctrl, SDHCI_INT_ENABLE);
2090         sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
2091
2092         spin_unlock_irqrestore(&host->lock, flags);
2093
2094         sdhci_cqe_disable(mmc, recovery);
2095 }
2096
2097 static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
2098         .enable         = sdhci_msm_cqe_enable,
2099         .disable        = sdhci_msm_cqe_disable,
2100 #ifdef CONFIG_MMC_CRYPTO
2101         .program_key    = sdhci_msm_program_key,
2102 #endif
2103 };
2104
2105 static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
2106                                 struct platform_device *pdev)
2107 {
2108         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2109         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2110         struct cqhci_host *cq_host;
2111         bool dma64;
2112         u32 cqcfg;
2113         int ret;
2114
2115         /*
2116          * When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
2117          * So ensure ADMA table is allocated for 16byte descriptors.
2118          */
2119         if (host->caps & SDHCI_CAN_64BIT)
2120                 host->alloc_desc_sz = 16;
2121
2122         ret = sdhci_setup_host(host);
2123         if (ret)
2124                 return ret;
2125
2126         cq_host = cqhci_pltfm_init(pdev);
2127         if (IS_ERR(cq_host)) {
2128                 ret = PTR_ERR(cq_host);
2129                 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
2130                 goto cleanup;
2131         }
2132
2133         msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2134         cq_host->ops = &sdhci_msm_cqhci_ops;
2135
2136         dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
2137
2138         ret = sdhci_msm_ice_init(msm_host, cq_host);
2139         if (ret)
2140                 goto cleanup;
2141
2142         ret = cqhci_init(cq_host, host->mmc, dma64);
2143         if (ret) {
2144                 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
2145                                 mmc_hostname(host->mmc), ret);
2146                 goto cleanup;
2147         }
2148
2149         /* Disable cqe reset due to cqe enable signal */
2150         cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
2151         cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
2152         cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);
2153
2154         /*
2155          * SDHC expects 12byte ADMA descriptors till CQE is enabled.
2156          * So limit desc_sz to 12 so that the data commands that are sent
2157          * during card initialization (before CQE gets enabled) would
2158          * get executed without any issues.
2159          */
2160         if (host->flags & SDHCI_USE_64_BIT_DMA)
2161                 host->desc_sz = 12;
2162
2163         ret = __sdhci_add_host(host);
2164         if (ret)
2165                 goto cleanup;
2166
2167         dev_info(&pdev->dev, "%s: CQE init: success\n",
2168                         mmc_hostname(host->mmc));
2169         return ret;
2170
2171 cleanup:
2172         sdhci_cleanup_host(host);
2173         return ret;
2174 }
2175
2176 /*
2177  * Platform specific register write functions. This is so that, if any
2178  * register write needs to be followed up by platform specific actions,
2179  * they can be added here. These functions can go to sleep when writes
2180  * to certain registers are done.
2181  * These functions are relying on sdhci_set_ios not using spinlock.
2182  */
2183 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
2184 {
2185         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2186         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2187         u32 req_type = 0;
2188
2189         switch (reg) {
2190         case SDHCI_HOST_CONTROL2:
2191                 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
2192                         REQ_IO_HIGH;
2193                 break;
2194         case SDHCI_SOFTWARE_RESET:
2195                 if (host->pwr && (val & SDHCI_RESET_ALL))
2196                         req_type = REQ_BUS_OFF;
2197                 break;
2198         case SDHCI_POWER_CONTROL:
2199                 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
2200                 break;
2201         case SDHCI_TRANSFER_MODE:
2202                 msm_host->transfer_mode = val;
2203                 break;
2204         case SDHCI_COMMAND:
2205                 if (!msm_host->use_cdr)
2206                         break;
2207                 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
2208                     SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
2209                     SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
2210                         sdhci_msm_set_cdr(host, true);
2211                 else
2212                         sdhci_msm_set_cdr(host, false);
2213                 break;
2214         }
2215
2216         if (req_type) {
2217                 msm_host->pwr_irq_flag = 0;
2218                 /*
2219                  * Since this register write may trigger a power irq, ensure
2220                  * all previous register writes are complete by this point.
2221                  */
2222                 mb();
2223         }
2224         return req_type;
2225 }
2226
2227 /* This function may sleep*/
2228 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
2229 {
2230         u32 req_type = 0;
2231
2232         req_type = __sdhci_msm_check_write(host, val, reg);
2233         writew_relaxed(val, host->ioaddr + reg);
2234
2235         if (req_type)
2236                 sdhci_msm_check_power_status(host, req_type);
2237 }
2238
2239 /* This function may sleep*/
2240 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
2241 {
2242         u32 req_type = 0;
2243
2244         req_type = __sdhci_msm_check_write(host, val, reg);
2245
2246         writeb_relaxed(val, host->ioaddr + reg);
2247
2248         if (req_type)
2249                 sdhci_msm_check_power_status(host, req_type);
2250 }
2251
2252 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
2253 {
2254         struct mmc_host *mmc = msm_host->mmc;
2255         struct regulator *supply = mmc->supply.vqmmc;
2256         u32 caps = 0, config;
2257         struct sdhci_host *host = mmc_priv(mmc);
2258         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2259
2260         if (!IS_ERR(mmc->supply.vqmmc)) {
2261                 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
2262                         caps |= CORE_1_8V_SUPPORT;
2263                 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
2264                         caps |= CORE_3_0V_SUPPORT;
2265
2266                 if (!caps)
2267                         pr_warn("%s: 1.8/3V not supported for vqmmc\n",
2268                                         mmc_hostname(mmc));
2269         }
2270
2271         if (caps) {
2272                 /*
2273                  * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
2274                  * bit can be used as required later on.
2275                  */
2276                 u32 io_level = msm_host->curr_io_level;
2277
2278                 config = readl_relaxed(host->ioaddr +
2279                                 msm_offset->core_vendor_spec);
2280                 config |= CORE_IO_PAD_PWR_SWITCH_EN;
2281
2282                 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
2283                         config &= ~CORE_IO_PAD_PWR_SWITCH;
2284                 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
2285                         config |= CORE_IO_PAD_PWR_SWITCH;
2286
2287                 writel_relaxed(config,
2288                                 host->ioaddr + msm_offset->core_vendor_spec);
2289         }
2290         msm_host->caps_0 |= caps;
2291         pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
2292 }
2293
2294 static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
2295 {
2296         if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL))
2297                 cqhci_deactivate(host->mmc);
2298         sdhci_reset(host, mask);
2299 }
2300
2301 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)
2302 {
2303         int ret;
2304
2305         ret = mmc_regulator_get_supply(msm_host->mmc);
2306         if (ret)
2307                 return ret;
2308
2309         sdhci_msm_set_regulator_caps(msm_host);
2310
2311         return 0;
2312 }
2313
2314 static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc,
2315                                       struct mmc_ios *ios)
2316 {
2317         struct sdhci_host *host = mmc_priv(mmc);
2318         u16 ctrl, status;
2319
2320         /*
2321          * Signal Voltage Switching is only applicable for Host Controllers
2322          * v3.00 and above.
2323          */
2324         if (host->version < SDHCI_SPEC_300)
2325                 return 0;
2326
2327         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2328
2329         switch (ios->signal_voltage) {
2330         case MMC_SIGNAL_VOLTAGE_330:
2331                 if (!(host->flags & SDHCI_SIGNALING_330))
2332                         return -EINVAL;
2333
2334                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2335                 ctrl &= ~SDHCI_CTRL_VDD_180;
2336                 break;
2337         case MMC_SIGNAL_VOLTAGE_180:
2338                 if (!(host->flags & SDHCI_SIGNALING_180))
2339                         return -EINVAL;
2340
2341                 /* Enable 1.8V Signal Enable in the Host Control2 register */
2342                 ctrl |= SDHCI_CTRL_VDD_180;
2343                 break;
2344
2345         default:
2346                 return -EINVAL;
2347         }
2348
2349         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2350
2351         /* Wait for 5ms */
2352         usleep_range(5000, 5500);
2353
2354         /* regulator output should be stable within 5 ms */
2355         status = ctrl & SDHCI_CTRL_VDD_180;
2356         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2357         if ((ctrl & SDHCI_CTRL_VDD_180) == status)
2358                 return 0;
2359
2360         dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n",
2361                 mmc_hostname(mmc));
2362
2363         return -EAGAIN;
2364 }
2365
2366 #define DRIVER_NAME "sdhci_msm"
2367 #define SDHCI_MSM_DUMP(f, x...) \
2368         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2369
2370 static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
2371 {
2372         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2373         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2374         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2375
2376         SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n");
2377
2378         SDHCI_MSM_DUMP(
2379                         "DLL sts: 0x%08x | DLL cfg:  0x%08x | DLL cfg2: 0x%08x\n",
2380                 readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
2381                 readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
2382                 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
2383         SDHCI_MSM_DUMP(
2384                         "DLL cfg3: 0x%08x | DLL usr ctl:  0x%08x | DDR cfg: 0x%08x\n",
2385                 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
2386                 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
2387                 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
2388         SDHCI_MSM_DUMP(
2389                         "Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
2390                 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
2391                 readl_relaxed(host->ioaddr +
2392                         msm_offset->core_vendor_spec_func2),
2393                 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
2394 }
2395
2396 static const struct sdhci_msm_variant_ops mci_var_ops = {
2397         .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
2398         .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
2399 };
2400
2401 static const struct sdhci_msm_variant_ops v5_var_ops = {
2402         .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
2403         .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
2404 };
2405
2406 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
2407         .var_ops = &mci_var_ops,
2408         .offset = &sdhci_msm_mci_offset,
2409 };
2410
2411 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
2412         .mci_removed = true,
2413         .var_ops = &v5_var_ops,
2414         .offset = &sdhci_msm_v5_offset,
2415 };
2416
2417 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
2418         .mci_removed = true,
2419         .restore_dll_config = true,
2420         .var_ops = &v5_var_ops,
2421         .offset = &sdhci_msm_v5_offset,
2422 };
2423
2424 static const struct of_device_id sdhci_msm_dt_match[] = {
2425         {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2426         {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2427         {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2428         {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2429         {},
2430 };
2431
2432 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
2433
2434 static const struct sdhci_ops sdhci_msm_ops = {
2435         .reset = sdhci_msm_reset,
2436         .set_clock = sdhci_msm_set_clock,
2437         .get_min_clock = sdhci_msm_get_min_clock,
2438         .get_max_clock = sdhci_msm_get_max_clock,
2439         .set_bus_width = sdhci_set_bus_width,
2440         .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
2441         .write_w = sdhci_msm_writew,
2442         .write_b = sdhci_msm_writeb,
2443         .irq    = sdhci_msm_cqe_irq,
2444         .dump_vendor_regs = sdhci_msm_dump_vendor_regs,
2445         .set_power = sdhci_set_power_noreg,
2446 };
2447
2448 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
2449         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
2450                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
2451                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
2452                   SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
2453
2454         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
2455         .ops = &sdhci_msm_ops,
2456 };
2457
2458 static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
2459                 struct sdhci_host *host)
2460 {
2461         struct device_node *node = pdev->dev.of_node;
2462         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2463         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2464
2465         if (of_property_read_u32(node, "qcom,ddr-config",
2466                                 &msm_host->ddr_config))
2467                 msm_host->ddr_config = DDR_CONFIG_POR_VAL;
2468
2469         of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
2470 }
2471
2472
2473 static int sdhci_msm_probe(struct platform_device *pdev)
2474 {
2475         struct sdhci_host *host;
2476         struct sdhci_pltfm_host *pltfm_host;
2477         struct sdhci_msm_host *msm_host;
2478         struct clk *clk;
2479         int ret;
2480         u16 host_version, core_minor;
2481         u32 core_version, config;
2482         u8 core_major;
2483         const struct sdhci_msm_offset *msm_offset;
2484         const struct sdhci_msm_variant_info *var_info;
2485         struct device_node *node = pdev->dev.of_node;
2486
2487         host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
2488         if (IS_ERR(host))
2489                 return PTR_ERR(host);
2490
2491         host->sdma_boundary = 0;
2492         pltfm_host = sdhci_priv(host);
2493         msm_host = sdhci_pltfm_priv(pltfm_host);
2494         msm_host->mmc = host->mmc;
2495         msm_host->pdev = pdev;
2496
2497         ret = mmc_of_parse(host->mmc);
2498         if (ret)
2499                 goto pltfm_free;
2500
2501         /*
2502          * Based on the compatible string, load the required msm host info from
2503          * the data associated with the version info.
2504          */
2505         var_info = of_device_get_match_data(&pdev->dev);
2506
2507         msm_host->mci_removed = var_info->mci_removed;
2508         msm_host->restore_dll_config = var_info->restore_dll_config;
2509         msm_host->var_ops = var_info->var_ops;
2510         msm_host->offset = var_info->offset;
2511
2512         msm_offset = msm_host->offset;
2513
2514         sdhci_get_of_property(pdev);
2515         sdhci_msm_get_of_property(pdev, host);
2516
2517         msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
2518
2519         /* Setup SDCC bus voter clock. */
2520         msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
2521         if (!IS_ERR(msm_host->bus_clk)) {
2522                 /* Vote for max. clk rate for max. performance */
2523                 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
2524                 if (ret)
2525                         goto pltfm_free;
2526                 ret = clk_prepare_enable(msm_host->bus_clk);
2527                 if (ret)
2528                         goto pltfm_free;
2529         }
2530
2531         /* Setup main peripheral bus clock */
2532         clk = devm_clk_get(&pdev->dev, "iface");
2533         if (IS_ERR(clk)) {
2534                 ret = PTR_ERR(clk);
2535                 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
2536                 goto bus_clk_disable;
2537         }
2538         msm_host->bulk_clks[1].clk = clk;
2539
2540         /* Setup SDC MMC clock */
2541         clk = devm_clk_get(&pdev->dev, "core");
2542         if (IS_ERR(clk)) {
2543                 ret = PTR_ERR(clk);
2544                 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
2545                 goto bus_clk_disable;
2546         }
2547         msm_host->bulk_clks[0].clk = clk;
2548
2549          /* Check for optional interconnect paths */
2550         ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL);
2551         if (ret)
2552                 goto bus_clk_disable;
2553
2554         msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core");
2555         if (IS_ERR(msm_host->opp_table)) {
2556                 ret = PTR_ERR(msm_host->opp_table);
2557                 goto bus_clk_disable;
2558         }
2559
2560         /* OPP table is optional */
2561         ret = dev_pm_opp_of_add_table(&pdev->dev);
2562         if (ret && ret != -ENODEV) {
2563                 dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
2564                 goto opp_put_clkname;
2565         }
2566
2567         /* Vote for maximum clock rate for maximum performance */
2568         ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX);
2569         if (ret)
2570                 dev_warn(&pdev->dev, "core clock boost failed\n");
2571
2572         clk = devm_clk_get(&pdev->dev, "cal");
2573         if (IS_ERR(clk))
2574                 clk = NULL;
2575         msm_host->bulk_clks[2].clk = clk;
2576
2577         clk = devm_clk_get(&pdev->dev, "sleep");
2578         if (IS_ERR(clk))
2579                 clk = NULL;
2580         msm_host->bulk_clks[3].clk = clk;
2581
2582         clk = sdhci_msm_ice_get_clk(&pdev->dev);
2583         if (IS_ERR(clk))
2584                 clk = NULL;
2585         msm_host->bulk_clks[4].clk = clk;
2586
2587         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2588                                       msm_host->bulk_clks);
2589         if (ret)
2590                 goto opp_cleanup;
2591
2592         /*
2593          * xo clock is needed for FLL feature of cm_dll.
2594          * In case if xo clock is not mentioned in DT, warn and proceed.
2595          */
2596         msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
2597         if (IS_ERR(msm_host->xo_clk)) {
2598                 ret = PTR_ERR(msm_host->xo_clk);
2599                 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
2600         }
2601
2602         if (!msm_host->mci_removed) {
2603                 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
2604                 if (IS_ERR(msm_host->core_mem)) {
2605                         ret = PTR_ERR(msm_host->core_mem);
2606                         goto clk_disable;
2607                 }
2608         }
2609
2610         /* Reset the vendor spec register to power on reset state */
2611         writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
2612                         host->ioaddr + msm_offset->core_vendor_spec);
2613
2614         if (!msm_host->mci_removed) {
2615                 /* Set HC_MODE_EN bit in HC_MODE register */
2616                 msm_host_writel(msm_host, HC_MODE_EN, host,
2617                                 msm_offset->core_hc_mode);
2618                 config = msm_host_readl(msm_host, host,
2619                                 msm_offset->core_hc_mode);
2620                 config |= FF_CLK_SW_RST_DIS;
2621                 msm_host_writel(msm_host, config, host,
2622                                 msm_offset->core_hc_mode);
2623         }
2624
2625         host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
2626         dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
2627                 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
2628                                SDHCI_VENDOR_VER_SHIFT));
2629
2630         core_version = msm_host_readl(msm_host, host,
2631                         msm_offset->core_mci_version);
2632         core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
2633                       CORE_VERSION_MAJOR_SHIFT;
2634         core_minor = core_version & CORE_VERSION_MINOR_MASK;
2635         dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
2636                 core_version, core_major, core_minor);
2637
2638         if (core_major == 1 && core_minor >= 0x42)
2639                 msm_host->use_14lpp_dll_reset = true;
2640
2641         /*
2642          * SDCC 5 controller with major version 1, minor version 0x34 and later
2643          * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
2644          */
2645         if (core_major == 1 && core_minor < 0x34)
2646                 msm_host->use_cdclp533 = true;
2647
2648         /*
2649          * Support for some capabilities is not advertised by newer
2650          * controller versions and must be explicitly enabled.
2651          */
2652         if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
2653                 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
2654                 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
2655                 writel_relaxed(config, host->ioaddr +
2656                                 msm_offset->core_vendor_spec_capabilities0);
2657         }
2658
2659         if (core_major == 1 && core_minor >= 0x49)
2660                 msm_host->updated_ddr_cfg = true;
2661
2662         if (core_major == 1 && core_minor >= 0x71)
2663                 msm_host->uses_tassadar_dll = true;
2664
2665         ret = sdhci_msm_register_vreg(msm_host);
2666         if (ret)
2667                 goto clk_disable;
2668
2669         /*
2670          * Power on reset state may trigger power irq if previous status of
2671          * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
2672          * interrupt in GIC, any pending power irq interrupt should be
2673          * acknowledged. Otherwise power irq interrupt handler would be
2674          * fired prematurely.
2675          */
2676         sdhci_msm_handle_pwr_irq(host, 0);
2677
2678         /*
2679          * Ensure that above writes are propogated before interrupt enablement
2680          * in GIC.
2681          */
2682         mb();
2683
2684         /* Setup IRQ for handling power/voltage tasks with PMIC */
2685         msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
2686         if (msm_host->pwr_irq < 0) {
2687                 ret = msm_host->pwr_irq;
2688                 goto clk_disable;
2689         }
2690
2691         sdhci_msm_init_pwr_irq_wait(msm_host);
2692         /* Enable pwr irq interrupts */
2693         msm_host_writel(msm_host, INT_MASK, host,
2694                 msm_offset->core_pwrctl_mask);
2695
2696         ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
2697                                         sdhci_msm_pwr_irq, IRQF_ONESHOT,
2698                                         dev_name(&pdev->dev), host);
2699         if (ret) {
2700                 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
2701                 goto clk_disable;
2702         }
2703
2704         msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
2705
2706         pm_runtime_get_noresume(&pdev->dev);
2707         pm_runtime_set_active(&pdev->dev);
2708         pm_runtime_enable(&pdev->dev);
2709         pm_runtime_set_autosuspend_delay(&pdev->dev,
2710                                          MSM_MMC_AUTOSUSPEND_DELAY_MS);
2711         pm_runtime_use_autosuspend(&pdev->dev);
2712
2713         host->mmc_host_ops.start_signal_voltage_switch =
2714                 sdhci_msm_start_signal_voltage_switch;
2715         host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
2716         if (of_property_read_bool(node, "supports-cqe"))
2717                 ret = sdhci_msm_cqe_add_host(host, pdev);
2718         else
2719                 ret = sdhci_add_host(host);
2720         if (ret)
2721                 goto pm_runtime_disable;
2722
2723         pm_runtime_mark_last_busy(&pdev->dev);
2724         pm_runtime_put_autosuspend(&pdev->dev);
2725
2726         return 0;
2727
2728 pm_runtime_disable:
2729         pm_runtime_disable(&pdev->dev);
2730         pm_runtime_set_suspended(&pdev->dev);
2731         pm_runtime_put_noidle(&pdev->dev);
2732 clk_disable:
2733         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2734                                    msm_host->bulk_clks);
2735 opp_cleanup:
2736         dev_pm_opp_of_remove_table(&pdev->dev);
2737 opp_put_clkname:
2738         dev_pm_opp_put_clkname(msm_host->opp_table);
2739 bus_clk_disable:
2740         if (!IS_ERR(msm_host->bus_clk))
2741                 clk_disable_unprepare(msm_host->bus_clk);
2742 pltfm_free:
2743         sdhci_pltfm_free(pdev);
2744         return ret;
2745 }
2746
2747 static int sdhci_msm_remove(struct platform_device *pdev)
2748 {
2749         struct sdhci_host *host = platform_get_drvdata(pdev);
2750         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2751         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2752         int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
2753                     0xffffffff);
2754
2755         sdhci_remove_host(host, dead);
2756
2757         dev_pm_opp_of_remove_table(&pdev->dev);
2758         dev_pm_opp_put_clkname(msm_host->opp_table);
2759         pm_runtime_get_sync(&pdev->dev);
2760         pm_runtime_disable(&pdev->dev);
2761         pm_runtime_put_noidle(&pdev->dev);
2762
2763         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2764                                    msm_host->bulk_clks);
2765         if (!IS_ERR(msm_host->bus_clk))
2766                 clk_disable_unprepare(msm_host->bus_clk);
2767         sdhci_pltfm_free(pdev);
2768         return 0;
2769 }
2770
2771 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
2772 {
2773         struct sdhci_host *host = dev_get_drvdata(dev);
2774         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2775         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2776
2777         /* Drop the performance vote */
2778         dev_pm_opp_set_rate(dev, 0);
2779         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2780                                    msm_host->bulk_clks);
2781
2782         return 0;
2783 }
2784
2785 static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
2786 {
2787         struct sdhci_host *host = dev_get_drvdata(dev);
2788         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2789         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2790         int ret;
2791
2792         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2793                                        msm_host->bulk_clks);
2794         if (ret)
2795                 return ret;
2796         /*
2797          * Whenever core-clock is gated dynamically, it's needed to
2798          * restore the SDR DLL settings when the clock is ungated.
2799          */
2800         if (msm_host->restore_dll_config && msm_host->clk_rate) {
2801                 ret = sdhci_msm_restore_sdr_dll_config(host);
2802                 if (ret)
2803                         return ret;
2804         }
2805
2806         dev_pm_opp_set_rate(dev, msm_host->clk_rate);
2807
2808         return sdhci_msm_ice_resume(msm_host);
2809 }
2810
2811 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2812         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2813                                 pm_runtime_force_resume)
2814         SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2815                            sdhci_msm_runtime_resume,
2816                            NULL)
2817 };
2818
2819 static struct platform_driver sdhci_msm_driver = {
2820         .probe = sdhci_msm_probe,
2821         .remove = sdhci_msm_remove,
2822         .driver = {
2823                    .name = "sdhci_msm",
2824                    .of_match_table = sdhci_msm_dt_match,
2825                    .pm = &sdhci_msm_pm_ops,
2826                    .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2827         },
2828 };
2829
2830 module_platform_driver(sdhci_msm_driver);
2831
2832 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2833 MODULE_LICENSE("GPL v2");