1 // SPDX-License-Identifier: GPL-2.0
3 * Freescale eSDHC i.MX controller driver for the platform bus.
5 * derived from the OF-version.
7 * Copyright (c) 2010 Pengutronix e.K.
8 * Author: Wolfram Sang <kernel@pengutronix.de>
11 #include <linux/bitfield.h>
13 #include <linux/iopoll.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/pm_qos.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/sdio.h>
23 #include <linux/mmc/slot-gpio.h>
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_data/mmc-esdhc-imx.h>
28 #include <linux/pm_runtime.h>
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
33 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
34 #define ESDHC_CTRL_D3CD 0x08
35 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
36 /* VENDOR SPEC register */
37 #define ESDHC_VENDOR_SPEC 0xc0
38 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
39 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
40 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
41 #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2
42 #define ESDHC_DEBUG_SEL_REG 0xc3
43 #define ESDHC_DEBUG_SEL_MASK 0xf
44 #define ESDHC_DEBUG_SEL_CMD_STATE 1
45 #define ESDHC_DEBUG_SEL_DATA_STATE 2
46 #define ESDHC_DEBUG_SEL_TRANS_STATE 3
47 #define ESDHC_DEBUG_SEL_DMA_STATE 4
48 #define ESDHC_DEBUG_SEL_ADMA_STATE 5
49 #define ESDHC_DEBUG_SEL_FIFO_STATE 6
50 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7
51 #define ESDHC_WTMK_LVL 0x44
52 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
53 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
54 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
55 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
56 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
57 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64
58 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128
59 #define ESDHC_MIX_CTRL 0x48
60 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
61 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
62 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
63 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
64 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
65 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
66 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
67 #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
68 /* Bits 3 and 6 are not SDHCI standard definitions */
69 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
71 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
73 /* dll control register */
74 #define ESDHC_DLL_CTRL 0x60
75 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
76 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
78 /* tune control register */
79 #define ESDHC_TUNE_CTRL_STATUS 0x68
80 #define ESDHC_TUNE_CTRL_STEP 1
81 #define ESDHC_TUNE_CTRL_MIN 0
82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
84 /* strobe dll register */
85 #define ESDHC_STROBE_DLL_CTRL 0x70
86 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
87 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
90 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
92 #define ESDHC_STROBE_DLL_STATUS 0x74
93 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
94 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
96 #define ESDHC_VEND_SPEC2 0xc8
97 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
99 #define ESDHC_TUNING_CTRL 0xcc
100 #define ESDHC_STD_TUNING_EN (1 << 24)
101 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
102 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
103 #define ESDHC_TUNING_START_TAP_MASK 0x7f
104 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7)
105 #define ESDHC_TUNING_STEP_MASK 0x00070000
106 #define ESDHC_TUNING_STEP_SHIFT 16
109 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
110 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
113 * Our interpretation of the SDHCI_HOST_CONTROL register
115 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
116 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
117 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
120 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
121 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
122 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
123 * Define this macro DMA error INT for fsl eSDHC
125 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
127 /* the address offset of CQHCI */
128 #define ESDHC_CQHCI_ADDR_OFFSET 0x100
131 * The CMDTYPE of the CMD register (offset 0xE) should be set to
132 * "11" when the STOP CMD12 is issued on imx53 to abort one
133 * open ended multi-blk IO. Otherwise the TC INT wouldn't
135 * In exact block transfer, the controller doesn't complete the
136 * operations automatically as required at the end of the
137 * transfer and remains on hold if the abort command is not sent.
138 * As a result, the TC flag is not asserted and SW received timeout
139 * exception. Bit1 of Vendor Spec register is used to fix it.
141 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
143 * The flag tells that the ESDHC controller is an USDHC block that is
144 * integrated on the i.MX6 series.
146 #define ESDHC_FLAG_USDHC BIT(3)
147 /* The IP supports manual tuning process */
148 #define ESDHC_FLAG_MAN_TUNING BIT(4)
149 /* The IP supports standard tuning process */
150 #define ESDHC_FLAG_STD_TUNING BIT(5)
151 /* The IP has SDHCI_CAPABILITIES_1 register */
152 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
154 * The IP has erratum ERR004536
155 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
156 * when reading data from the card
157 * This flag is also set for i.MX25 and i.MX35 in order to get
158 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
160 #define ESDHC_FLAG_ERR004536 BIT(7)
161 /* The IP supports HS200 mode */
162 #define ESDHC_FLAG_HS200 BIT(8)
163 /* The IP supports HS400 mode */
164 #define ESDHC_FLAG_HS400 BIT(9)
166 * The IP has errata ERR010450
167 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
168 * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
170 #define ESDHC_FLAG_ERR010450 BIT(10)
171 /* The IP supports HS400ES mode */
172 #define ESDHC_FLAG_HS400_ES BIT(11)
173 /* The IP has Host Controller Interface for Command Queuing */
174 #define ESDHC_FLAG_CQHCI BIT(12)
175 /* need request pmqos during low power */
176 #define ESDHC_FLAG_PMQOS BIT(13)
177 /* The IP state got lost in low power mode */
178 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14)
179 /* The IP lost clock rate in PM_RUNTIME */
180 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15)
182 * The IP do not support the ACMD23 feature completely when use ADMA mode.
183 * In ADMA mode, it only use the 16 bit block count of the register 0x4
184 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
185 * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
186 * write operation in RPMB, because RPMB reliable write need to set the bit31
187 * of the CMD23's argument.
188 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
189 * do not has this limitation. so when these SoC use ADMA mode, it need to
190 * disable the ACMD23 feature.
192 #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
194 struct esdhc_soc_data {
198 static const struct esdhc_soc_data esdhc_imx25_data = {
199 .flags = ESDHC_FLAG_ERR004536,
202 static const struct esdhc_soc_data esdhc_imx35_data = {
203 .flags = ESDHC_FLAG_ERR004536,
206 static const struct esdhc_soc_data esdhc_imx51_data = {
210 static const struct esdhc_soc_data esdhc_imx53_data = {
211 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
214 static const struct esdhc_soc_data usdhc_imx6q_data = {
215 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
216 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
219 static const struct esdhc_soc_data usdhc_imx6sl_data = {
220 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
221 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
223 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
226 static const struct esdhc_soc_data usdhc_imx6sll_data = {
227 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
228 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
230 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
233 static const struct esdhc_soc_data usdhc_imx6sx_data = {
234 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
235 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
236 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
237 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
240 static const struct esdhc_soc_data usdhc_imx6ull_data = {
241 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
242 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
243 | ESDHC_FLAG_ERR010450
244 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
247 static const struct esdhc_soc_data usdhc_imx7d_data = {
248 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
249 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
251 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
252 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
255 static struct esdhc_soc_data usdhc_imx7ulp_data = {
256 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
257 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
258 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
259 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
262 static struct esdhc_soc_data usdhc_imx8qxp_data = {
263 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
264 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
265 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
267 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
268 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
271 static struct esdhc_soc_data usdhc_imx8mm_data = {
272 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
273 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
274 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
276 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
279 struct pltfm_imx_data {
281 struct pinctrl *pinctrl;
282 struct pinctrl_state *pins_100mhz;
283 struct pinctrl_state *pins_200mhz;
284 const struct esdhc_soc_data *socdata;
285 struct esdhc_platform_data boarddata;
289 unsigned int actual_clock;
291 NO_CMD_PENDING, /* no multiblock command pending */
292 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
293 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
296 struct pm_qos_request pm_qos_req;
299 static const struct of_device_id imx_esdhc_dt_ids[] = {
300 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
301 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
302 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
303 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
304 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
305 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
306 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
307 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
308 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
309 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
310 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
311 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
312 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
315 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
317 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
319 return data->socdata == &esdhc_imx25_data;
322 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
324 return data->socdata == &esdhc_imx53_data;
327 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
329 return data->socdata == &usdhc_imx6q_data;
332 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
334 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
337 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
339 void __iomem *base = host->ioaddr + (reg & ~0x3);
340 u32 shift = (reg & 0x3) * 8;
342 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
345 #define DRIVER_NAME "sdhci-esdhc-imx"
346 #define ESDHC_IMX_DUMP(f, x...) \
347 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
348 static void esdhc_dump_debug_regs(struct sdhci_host *host)
351 char *debug_status[7] = {
354 "trans debug status",
358 "async fifo debug status"
361 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
362 for (i = 0; i < 7; i++) {
363 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
364 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
365 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i],
366 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
369 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
373 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
378 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
379 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
380 if (ret == -ETIMEDOUT)
381 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
384 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
386 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
387 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
388 u32 val = readl(host->ioaddr + reg);
390 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
392 /* save the least 20 bits */
393 val = fsl_prss & 0x000FFFFF;
394 /* move dat[0-3] bits */
395 val |= (fsl_prss & 0x0F000000) >> 4;
396 /* move cmd line bit */
397 val |= (fsl_prss & 0x00800000) << 1;
400 if (unlikely(reg == SDHCI_CAPABILITIES)) {
401 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
402 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
405 /* In FSL esdhc IC module, only bit20 is used to indicate the
406 * ADMA2 capability of esdhc, but this bit is messed up on
407 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
408 * don't actually support ADMA2). So set the BROKEN_ADMA
409 * quirk on MX25/35 platforms.
412 if (val & SDHCI_CAN_DO_ADMA1) {
413 val &= ~SDHCI_CAN_DO_ADMA1;
414 val |= SDHCI_CAN_DO_ADMA2;
418 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
419 if (esdhc_is_usdhc(imx_data)) {
420 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
421 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
423 /* imx6q/dl does not have cap_1 register, fake one */
424 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
425 | SDHCI_SUPPORT_SDR50
426 | SDHCI_USE_SDR50_TUNING
427 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
428 SDHCI_TUNING_MODE_3);
430 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
431 val |= SDHCI_SUPPORT_HS400;
434 * Do not advertise faster UHS modes if there are no
435 * pinctrl states for 100MHz/200MHz.
437 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
438 IS_ERR_OR_NULL(imx_data->pins_200mhz))
439 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
440 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
444 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
446 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
447 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
448 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
451 if (unlikely(reg == SDHCI_INT_STATUS)) {
452 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
453 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
454 val |= SDHCI_INT_ADMA_ERROR;
458 * mask off the interrupt we get in response to the manually
461 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
462 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
463 val &= ~SDHCI_INT_RESPONSE;
464 writel(SDHCI_INT_RESPONSE, host->ioaddr +
466 imx_data->multiblock_status = NO_CMD_PENDING;
473 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
475 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
476 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
479 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
480 reg == SDHCI_INT_STATUS)) {
481 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
483 * Clear and then set D3CD bit to avoid missing the
484 * card interrupt. This is an eSDHC controller problem
485 * so we need to apply the following workaround: clear
486 * and set D3CD bit will make eSDHC re-sample the card
487 * interrupt. In case a card interrupt was lost,
488 * re-sample it by the following steps.
490 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
491 data &= ~ESDHC_CTRL_D3CD;
492 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
493 data |= ESDHC_CTRL_D3CD;
494 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
497 if (val & SDHCI_INT_ADMA_ERROR) {
498 val &= ~SDHCI_INT_ADMA_ERROR;
499 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
503 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
504 && (reg == SDHCI_INT_STATUS)
505 && (val & SDHCI_INT_DATA_END))) {
507 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
508 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
509 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
511 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
513 /* send a manual CMD12 with RESPTYP=none */
514 data = MMC_STOP_TRANSMISSION << 24 |
515 SDHCI_CMD_ABORTCMD << 16;
516 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
517 imx_data->multiblock_status = WAIT_FOR_INT;
521 writel(val, host->ioaddr + reg);
524 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
526 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
527 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
531 if (unlikely(reg == SDHCI_HOST_VERSION)) {
533 if (esdhc_is_usdhc(imx_data)) {
535 * The usdhc register returns a wrong host version.
538 return SDHCI_SPEC_300;
542 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
543 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
544 if (val & ESDHC_VENDOR_SPEC_VSELECT)
545 ret |= SDHCI_CTRL_VDD_180;
547 if (esdhc_is_usdhc(imx_data)) {
548 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
549 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
550 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
551 /* the std tuning bits is in ACMD12_ERR for imx6sl */
552 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
555 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
556 ret |= SDHCI_CTRL_EXEC_TUNING;
557 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
558 ret |= SDHCI_CTRL_TUNED_CLK;
560 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
565 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
566 if (esdhc_is_usdhc(imx_data)) {
567 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
568 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
570 if (m & ESDHC_MIX_CTRL_AC23EN) {
571 ret &= ~ESDHC_MIX_CTRL_AC23EN;
572 ret |= SDHCI_TRNS_AUTO_CMD23;
575 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
581 return readw(host->ioaddr + reg);
584 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
586 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
587 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
591 case SDHCI_CLOCK_CONTROL:
592 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
593 if (val & SDHCI_CLOCK_CARD_EN)
594 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
596 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
597 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
598 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
599 esdhc_wait_for_card_clock_gate_off(host);
601 case SDHCI_HOST_CONTROL2:
602 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
603 if (val & SDHCI_CTRL_VDD_180)
604 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
606 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
607 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
608 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
609 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
610 if (val & SDHCI_CTRL_TUNED_CLK) {
611 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
612 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
614 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
615 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
617 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
618 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
619 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
620 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
621 if (val & SDHCI_CTRL_TUNED_CLK) {
622 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
624 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
625 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
626 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
629 if (val & SDHCI_CTRL_EXEC_TUNING) {
630 v |= ESDHC_MIX_CTRL_EXE_TUNE;
631 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
632 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
634 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
637 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
638 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
641 case SDHCI_TRANSFER_MODE:
642 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
643 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
644 && (host->cmd->data->blocks > 1)
645 && (host->cmd->data->flags & MMC_DATA_READ)) {
647 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
648 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
649 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
652 if (esdhc_is_usdhc(imx_data)) {
654 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
656 if (val & SDHCI_TRNS_AUTO_CMD23) {
657 val &= ~SDHCI_TRNS_AUTO_CMD23;
658 val |= ESDHC_MIX_CTRL_AC23EN;
660 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
661 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
663 /* Set watermark levels for PIO access to maximum value
664 * (128 words) to accommodate full 512 bytes buffer.
665 * For DMA access restore the levels to default value.
667 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
668 if (val & SDHCI_TRNS_DMA) {
669 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
672 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
675 * Since already disable DMA mode, so also need
676 * to clear the DMASEL. Otherwise, for standard
677 * tuning, when send tuning command, usdhc will
678 * still prefetch the ADMA script from wrong
679 * DMA address, then we will see IOMMU report
680 * some error which show lack of TLB mapping.
682 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
683 ctrl &= ~SDHCI_CTRL_DMA_MASK;
684 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
686 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
687 ESDHC_WTMK_LVL_WR_WML_MASK);
688 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
689 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
690 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
693 * Postpone this write, we must do it together with a
694 * command write that is down below.
696 imx_data->scratchpad = val;
700 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
701 val |= SDHCI_CMD_ABORTCMD;
703 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
704 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
705 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
707 if (esdhc_is_usdhc(imx_data))
709 host->ioaddr + SDHCI_TRANSFER_MODE);
711 writel(val << 16 | imx_data->scratchpad,
712 host->ioaddr + SDHCI_TRANSFER_MODE);
714 case SDHCI_BLOCK_SIZE:
715 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
718 esdhc_clrset_le(host, 0xffff, val, reg);
721 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
727 case SDHCI_HOST_CONTROL:
728 val = readl(host->ioaddr + reg);
730 ret = val & SDHCI_CTRL_LED;
731 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
732 ret |= (val & ESDHC_CTRL_4BITBUS);
733 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
737 return readb(host->ioaddr + reg);
740 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
742 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
743 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
748 case SDHCI_POWER_CONTROL:
750 * FSL put some DMA bits here
751 * If your board has a regulator, code should be here
754 case SDHCI_HOST_CONTROL:
755 /* FSL messed up here, so we need to manually compose it. */
756 new_val = val & SDHCI_CTRL_LED;
757 /* ensure the endianness */
758 new_val |= ESDHC_HOST_CONTROL_LE;
759 /* bits 8&9 are reserved on mx25 */
760 if (!is_imx25_esdhc(imx_data)) {
761 /* DMA mode bits are shifted */
762 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
766 * Do not touch buswidth bits here. This is done in
767 * esdhc_pltfm_bus_width.
768 * Do not touch the D3CD bit either which is used for the
769 * SDIO interrupt erratum workaround.
771 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
773 esdhc_clrset_le(host, mask, new_val, reg);
775 case SDHCI_SOFTWARE_RESET:
776 if (val & SDHCI_RESET_DATA)
777 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
780 esdhc_clrset_le(host, 0xff, val, reg);
782 if (reg == SDHCI_SOFTWARE_RESET) {
783 if (val & SDHCI_RESET_ALL) {
785 * The esdhc has a design violation to SDHC spec which
786 * tells that software reset should not affect card
787 * detection circuit. But esdhc clears its SYSCTL
788 * register bits [0..2] during the software reset. This
789 * will stop those clocks that card detection circuit
790 * relies on. To work around it, we turn the clocks on
791 * back to keep card detection circuit functional.
793 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
795 * The reset on usdhc fails to clear MIX_CTRL register.
796 * Do it manually here.
798 if (esdhc_is_usdhc(imx_data)) {
800 * the tuning bits should be kept during reset
802 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
803 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
804 host->ioaddr + ESDHC_MIX_CTRL);
805 imx_data->is_ddr = 0;
807 } else if (val & SDHCI_RESET_DATA) {
809 * The eSDHC DAT line software reset clears at least the
810 * data transfer width on i.MX25, so make sure that the
811 * Host Control register is unaffected.
813 esdhc_clrset_le(host, 0xff, new_val,
819 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
821 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
823 return pltfm_host->clock;
826 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
828 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
830 return pltfm_host->clock / 256 / 16;
833 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
836 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
837 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
838 unsigned int host_clock = pltfm_host->clock;
839 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
845 if (esdhc_is_usdhc(imx_data)) {
846 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
847 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
848 host->ioaddr + ESDHC_VENDOR_SPEC);
849 esdhc_wait_for_card_clock_gate_off(host);
853 host->mmc->actual_clock = 0;
857 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
858 if (is_imx53_esdhc(imx_data)) {
860 * According to the i.MX53 reference manual, if DLLCTRL[10] can
861 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
863 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
864 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
865 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
866 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
871 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
872 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
874 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
876 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
877 unsigned int max_clock;
879 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
881 clock = min(clock, max_clock);
884 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
888 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
891 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
892 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
893 clock, host->mmc->actual_clock);
898 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
899 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
900 | (div << ESDHC_DIVIDER_SHIFT)
901 | (pre_div << ESDHC_PREDIV_SHIFT));
902 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
904 /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
905 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
906 (temp & ESDHC_CLOCK_STABLE), 2, 100);
907 if (ret == -ETIMEDOUT)
908 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
910 if (esdhc_is_usdhc(imx_data)) {
911 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
912 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
913 host->ioaddr + ESDHC_VENDOR_SPEC);
918 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
920 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
921 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
922 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
924 switch (boarddata->wp_type) {
926 return mmc_gpio_get_ro(host->mmc);
927 case ESDHC_WP_CONTROLLER:
928 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
929 SDHCI_WRITE_PROTECT);
937 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
942 case MMC_BUS_WIDTH_8:
943 ctrl = ESDHC_CTRL_8BITBUS;
945 case MMC_BUS_WIDTH_4:
946 ctrl = ESDHC_CTRL_4BITBUS;
953 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
957 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
959 struct sdhci_host *host = mmc_priv(mmc);
962 * i.MX uSDHC internally already uses a fixed optimized timing for
963 * DDR50, normally does not require tuning for DDR50 mode.
965 if (host->timing == MMC_TIMING_UHS_DDR50)
968 return sdhci_execute_tuning(mmc, opcode);
971 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
977 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
980 /* IC suggest to reset USDHC before every tuning command */
981 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
982 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
983 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
984 if (ret == -ETIMEDOUT)
985 dev_warn(mmc_dev(host->mmc),
986 "warning! RESET_ALL never complete before sending tuning command\n");
988 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
989 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
990 ESDHC_MIX_CTRL_FBCLK_SEL;
991 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
992 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
993 dev_dbg(mmc_dev(host->mmc),
994 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
995 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
998 static void esdhc_post_tuning(struct sdhci_host *host)
1002 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1003 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1004 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1005 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1008 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1010 int min, max, avg, ret;
1012 /* find the mininum delay first which can pass tuning */
1013 min = ESDHC_TUNE_CTRL_MIN;
1014 while (min < ESDHC_TUNE_CTRL_MAX) {
1015 esdhc_prepare_tuning(host, min);
1016 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1018 min += ESDHC_TUNE_CTRL_STEP;
1021 /* find the maxinum delay which can not pass tuning */
1022 max = min + ESDHC_TUNE_CTRL_STEP;
1023 while (max < ESDHC_TUNE_CTRL_MAX) {
1024 esdhc_prepare_tuning(host, max);
1025 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1026 max -= ESDHC_TUNE_CTRL_STEP;
1029 max += ESDHC_TUNE_CTRL_STEP;
1032 /* use average delay to get the best timing */
1033 avg = (min + max) / 2;
1034 esdhc_prepare_tuning(host, avg);
1035 ret = mmc_send_tuning(host->mmc, opcode, NULL);
1036 esdhc_post_tuning(host);
1038 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1039 ret ? "failed" : "passed", avg, ret);
1044 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1046 struct sdhci_host *host = mmc_priv(mmc);
1049 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1050 if (ios->enhanced_strobe)
1051 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1053 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1054 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1057 static int esdhc_change_pinstate(struct sdhci_host *host,
1060 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1061 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1062 struct pinctrl_state *pinctrl;
1064 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1066 if (IS_ERR(imx_data->pinctrl) ||
1067 IS_ERR(imx_data->pins_100mhz) ||
1068 IS_ERR(imx_data->pins_200mhz))
1072 case MMC_TIMING_UHS_SDR50:
1073 case MMC_TIMING_UHS_DDR50:
1074 pinctrl = imx_data->pins_100mhz;
1076 case MMC_TIMING_UHS_SDR104:
1077 case MMC_TIMING_MMC_HS200:
1078 case MMC_TIMING_MMC_HS400:
1079 pinctrl = imx_data->pins_200mhz;
1082 /* back to default state for other legacy timing */
1083 return pinctrl_select_default_state(mmc_dev(host->mmc));
1086 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1090 * For HS400 eMMC, there is a data_strobe line. This signal is generated
1091 * by the device and used for data output and CRC status response output
1092 * in HS400 mode. The frequency of this signal follows the frequency of
1093 * CLK generated by host. The host receives the data which is aligned to the
1094 * edge of data_strobe line. Due to the time delay between CLK line and
1095 * data_strobe line, if the delay time is larger than one clock cycle,
1096 * then CLK and data_strobe line will be misaligned, read error shows up.
1098 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1100 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1101 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1106 /* disable clock before enabling strobe dll */
1107 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1108 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1109 host->ioaddr + ESDHC_VENDOR_SPEC);
1110 esdhc_wait_for_card_clock_gate_off(host);
1112 /* force a reset on strobe dll */
1113 writel(ESDHC_STROBE_DLL_CTRL_RESET,
1114 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1115 /* clear the reset bit on strobe dll before any setting */
1116 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1119 * enable strobe dll ctrl and adjust the delay target
1120 * for the uSDHC loopback read clock
1122 if (imx_data->boarddata.strobe_dll_delay_target)
1123 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1125 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1126 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1127 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1128 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1129 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1131 /* wait max 50us to get the REF/SLV lock */
1132 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1133 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1134 if (ret == -ETIMEDOUT)
1135 dev_warn(mmc_dev(host->mmc),
1136 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1139 static void esdhc_reset_tuning(struct sdhci_host *host)
1141 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1142 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1145 /* Reset the tuning circuit */
1146 if (esdhc_is_usdhc(imx_data)) {
1147 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1148 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1149 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1150 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1151 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1152 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1153 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1154 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1155 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1156 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1161 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1164 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1165 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1166 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1168 /* disable ddr mode and disable HS400 mode */
1169 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1170 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1171 imx_data->is_ddr = 0;
1174 case MMC_TIMING_UHS_SDR12:
1175 case MMC_TIMING_UHS_SDR25:
1176 case MMC_TIMING_UHS_SDR50:
1177 case MMC_TIMING_UHS_SDR104:
1178 case MMC_TIMING_MMC_HS:
1179 case MMC_TIMING_MMC_HS200:
1180 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1182 case MMC_TIMING_UHS_DDR50:
1183 case MMC_TIMING_MMC_DDR52:
1184 m |= ESDHC_MIX_CTRL_DDREN;
1185 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1186 imx_data->is_ddr = 1;
1187 if (boarddata->delay_line) {
1189 v = boarddata->delay_line <<
1190 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1191 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1192 if (is_imx53_esdhc(imx_data))
1194 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1197 case MMC_TIMING_MMC_HS400:
1198 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1199 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1200 imx_data->is_ddr = 1;
1201 /* update clock after enable DDR for strobe DLL lock */
1202 host->ops->set_clock(host, host->clock);
1203 esdhc_set_strobe_dll(host);
1205 case MMC_TIMING_LEGACY:
1207 esdhc_reset_tuning(host);
1211 esdhc_change_pinstate(host, timing);
1214 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1216 sdhci_reset(host, mask);
1218 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1219 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1222 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1224 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1225 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1227 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1228 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1231 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1233 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1234 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1236 /* use maximum timeout counter */
1237 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1238 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1239 SDHCI_TIMEOUT_CONTROL);
1242 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1247 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1250 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1255 static struct sdhci_ops sdhci_esdhc_ops = {
1256 .read_l = esdhc_readl_le,
1257 .read_w = esdhc_readw_le,
1258 .read_b = esdhc_readb_le,
1259 .write_l = esdhc_writel_le,
1260 .write_w = esdhc_writew_le,
1261 .write_b = esdhc_writeb_le,
1262 .set_clock = esdhc_pltfm_set_clock,
1263 .get_max_clock = esdhc_pltfm_get_max_clock,
1264 .get_min_clock = esdhc_pltfm_get_min_clock,
1265 .get_max_timeout_count = esdhc_get_max_timeout_count,
1266 .get_ro = esdhc_pltfm_get_ro,
1267 .set_timeout = esdhc_set_timeout,
1268 .set_bus_width = esdhc_pltfm_set_bus_width,
1269 .set_uhs_signaling = esdhc_set_uhs_signaling,
1270 .reset = esdhc_reset,
1271 .irq = esdhc_cqhci_irq,
1272 .dump_vendor_regs = esdhc_dump_debug_regs,
1275 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1276 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1277 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1278 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1279 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1280 .ops = &sdhci_esdhc_ops,
1283 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1285 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1286 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1287 struct cqhci_host *cq_host = host->mmc->cqe_private;
1290 if (esdhc_is_usdhc(imx_data)) {
1292 * The imx6q ROM code will change the default watermark
1293 * level setting to something insane. Change it back here.
1295 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1298 * ROM code will change the bit burst_length_enable setting
1299 * to zero if this usdhc is chosen to boot system. Change
1300 * it back here, otherwise it will impact the performance a
1301 * lot. This bit is used to enable/disable the burst length
1302 * for the external AHB2AXI bridge. It's useful especially
1303 * for INCR transfer because without burst length indicator,
1304 * the AHB2AXI bridge does not know the burst length in
1305 * advance. And without burst length indicator, AHB INCR
1306 * transfer can only be converted to singles on the AXI side.
1308 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1309 | ESDHC_BURST_LEN_EN_INCR,
1310 host->ioaddr + SDHCI_HOST_CONTROL);
1313 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1314 * TO1.1, it's harmless for MX6SL
1316 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1317 host->ioaddr + 0x6c);
1319 /* disable DLL_CTRL delay line settings */
1320 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1323 * For the case of command with busy, if set the bit
1324 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1325 * transfer complete interrupt when busy is deasserted.
1326 * When CQHCI use DCMD to send a CMD need R1b respons,
1327 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1328 * otherwise DCMD will always meet timeout waiting for
1329 * hardware interrupt issue.
1331 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1332 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1333 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1334 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1336 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1339 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1340 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1341 tmp |= ESDHC_STD_TUNING_EN |
1342 ESDHC_TUNING_START_TAP_DEFAULT;
1343 if (imx_data->boarddata.tuning_start_tap) {
1344 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1345 tmp |= imx_data->boarddata.tuning_start_tap;
1348 if (imx_data->boarddata.tuning_step) {
1349 tmp &= ~ESDHC_TUNING_STEP_MASK;
1350 tmp |= imx_data->boarddata.tuning_step
1351 << ESDHC_TUNING_STEP_SHIFT;
1354 /* Disable the CMD CRC check for tuning, if not, need to
1355 * add some delay after every tuning command, because
1356 * hardware standard tuning logic will directly go to next
1357 * step once it detect the CMD CRC error, will not wait for
1358 * the card side to finally send out the tuning data, trigger
1359 * the buffer read ready interrupt immediately. If usdhc send
1360 * the next tuning command some eMMC card will stuck, can't
1361 * response, block the tuning procedure or the first command
1362 * after the whole tuning procedure always can't get any response.
1364 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1365 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1366 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1368 * ESDHC_STD_TUNING_EN may be configed in bootloader
1369 * or ROM code, so clear this bit here to make sure
1370 * the manual tuning can work.
1372 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1373 tmp &= ~ESDHC_STD_TUNING_EN;
1374 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1378 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1379 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
1380 * the 1st linux configure power/clock for the 2nd Linux.
1382 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1383 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1384 * After we clear the pending interrupt and halt CQCTL, issue gone.
1387 tmp = cqhci_readl(cq_host, CQHCI_IS);
1388 cqhci_writel(cq_host, tmp, CQHCI_IS);
1389 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1394 static void esdhc_cqe_enable(struct mmc_host *mmc)
1396 struct sdhci_host *host = mmc_priv(mmc);
1397 struct cqhci_host *cq_host = mmc->cqe_private;
1403 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1404 * the case after tuning, so ensure the buffer is drained.
1406 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1407 while (reg & SDHCI_DATA_AVAILABLE) {
1408 sdhci_readl(host, SDHCI_BUFFER);
1409 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1411 dev_warn(mmc_dev(host->mmc),
1412 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1419 * Runtime resume will reset the entire host controller, which
1420 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1421 * Here set DMAEN and BCEN when enable CMDQ.
1423 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1424 if (host->flags & SDHCI_REQ_USE_DMA)
1425 mode |= SDHCI_TRNS_DMA;
1426 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1427 mode |= SDHCI_TRNS_BLK_CNT_EN;
1428 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1431 * Though Runtime resume reset the entire host controller,
1432 * but do not impact the CQHCI side, need to clear the
1433 * HALT bit, avoid CQHCI stuck in the first request when
1434 * system resume back.
1436 cqhci_writel(cq_host, 0, CQHCI_CTL);
1437 if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
1438 dev_err(mmc_dev(host->mmc),
1439 "failed to exit halt state when enable CQE\n");
1442 sdhci_cqe_enable(mmc);
1445 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1447 sdhci_dumpregs(mmc_priv(mmc));
1450 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1451 .enable = esdhc_cqe_enable,
1452 .disable = sdhci_cqe_disable,
1453 .dumpregs = esdhc_sdhci_dumpregs,
1458 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1459 struct sdhci_host *host,
1460 struct pltfm_imx_data *imx_data)
1462 struct device_node *np = pdev->dev.of_node;
1463 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1466 if (of_get_property(np, "fsl,wp-controller", NULL))
1467 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1470 * If we have this property, then activate WP check.
1471 * Retrieveing and requesting the actual WP GPIO will happen
1472 * in the call to mmc_of_parse().
1474 if (of_property_read_bool(np, "wp-gpios"))
1475 boarddata->wp_type = ESDHC_WP_GPIO;
1477 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1478 of_property_read_u32(np, "fsl,tuning-start-tap",
1479 &boarddata->tuning_start_tap);
1481 of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1482 &boarddata->strobe_dll_delay_target);
1483 if (of_find_property(np, "no-1-8-v", NULL))
1484 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1486 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1487 boarddata->delay_line = 0;
1489 mmc_of_parse_voltage(np, &host->ocr_mask);
1491 if (esdhc_is_usdhc(imx_data)) {
1492 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1493 ESDHC_PINCTRL_STATE_100MHZ);
1494 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1495 ESDHC_PINCTRL_STATE_200MHZ);
1498 /* call to generic mmc_of_parse to support additional capabilities */
1499 ret = mmc_of_parse(host->mmc);
1503 if (mmc_gpio_get_cd(host->mmc) >= 0)
1504 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1510 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1511 struct sdhci_host *host,
1512 struct pltfm_imx_data *imx_data)
1518 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1520 const struct of_device_id *of_id =
1521 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1522 struct sdhci_pltfm_host *pltfm_host;
1523 struct sdhci_host *host;
1524 struct cqhci_host *cq_host;
1526 struct pltfm_imx_data *imx_data;
1528 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1531 return PTR_ERR(host);
1533 pltfm_host = sdhci_priv(host);
1535 imx_data = sdhci_pltfm_priv(pltfm_host);
1537 imx_data->socdata = of_id->data;
1539 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1540 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1542 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1543 if (IS_ERR(imx_data->clk_ipg)) {
1544 err = PTR_ERR(imx_data->clk_ipg);
1548 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1549 if (IS_ERR(imx_data->clk_ahb)) {
1550 err = PTR_ERR(imx_data->clk_ahb);
1554 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1555 if (IS_ERR(imx_data->clk_per)) {
1556 err = PTR_ERR(imx_data->clk_per);
1560 pltfm_host->clk = imx_data->clk_per;
1561 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1562 err = clk_prepare_enable(imx_data->clk_per);
1565 err = clk_prepare_enable(imx_data->clk_ipg);
1567 goto disable_per_clk;
1568 err = clk_prepare_enable(imx_data->clk_ahb);
1570 goto disable_ipg_clk;
1572 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1573 if (IS_ERR(imx_data->pinctrl))
1574 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1576 if (esdhc_is_usdhc(imx_data)) {
1577 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1578 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1580 /* GPIO CD can be set as a wakeup source */
1581 host->mmc->caps |= MMC_CAP_CD_WAKE;
1583 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1584 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1586 /* clear tuning bits in case ROM has set it already */
1587 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1588 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1589 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1592 * Link usdhc specific mmc_host_ops execute_tuning function,
1593 * to replace the standard one in sdhci_ops.
1595 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1598 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1599 sdhci_esdhc_ops.platform_execute_tuning =
1600 esdhc_executing_tuning;
1602 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1603 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1605 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1606 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1608 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1609 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1611 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1612 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1613 host->mmc_host_ops.hs400_enhanced_strobe =
1614 esdhc_hs400_enhanced_strobe;
1617 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1618 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1619 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1622 goto disable_ahb_clk;
1625 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1626 cq_host->ops = &esdhc_cqhci_ops;
1628 err = cqhci_init(cq_host, host->mmc, false);
1630 goto disable_ahb_clk;
1633 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1635 goto disable_ahb_clk;
1637 sdhci_esdhc_imx_hwinit(host);
1639 err = sdhci_add_host(host);
1641 goto disable_ahb_clk;
1643 pm_runtime_set_active(&pdev->dev);
1644 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1645 pm_runtime_use_autosuspend(&pdev->dev);
1646 pm_suspend_ignore_children(&pdev->dev, 1);
1647 pm_runtime_enable(&pdev->dev);
1652 clk_disable_unprepare(imx_data->clk_ahb);
1654 clk_disable_unprepare(imx_data->clk_ipg);
1656 clk_disable_unprepare(imx_data->clk_per);
1658 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1659 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1660 sdhci_pltfm_free(pdev);
1664 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1666 struct sdhci_host *host = platform_get_drvdata(pdev);
1667 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1668 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1671 pm_runtime_get_sync(&pdev->dev);
1672 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1673 pm_runtime_disable(&pdev->dev);
1674 pm_runtime_put_noidle(&pdev->dev);
1676 sdhci_remove_host(host, dead);
1678 clk_disable_unprepare(imx_data->clk_per);
1679 clk_disable_unprepare(imx_data->clk_ipg);
1680 clk_disable_unprepare(imx_data->clk_ahb);
1682 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1683 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1685 sdhci_pltfm_free(pdev);
1690 #ifdef CONFIG_PM_SLEEP
1691 static int sdhci_esdhc_suspend(struct device *dev)
1693 struct sdhci_host *host = dev_get_drvdata(dev);
1694 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1695 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1698 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1699 ret = cqhci_suspend(host->mmc);
1704 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1705 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1706 mmc_retune_timer_stop(host->mmc);
1707 mmc_retune_needed(host->mmc);
1710 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1711 mmc_retune_needed(host->mmc);
1713 ret = sdhci_suspend_host(host);
1717 ret = pinctrl_pm_select_sleep_state(dev);
1721 ret = mmc_gpio_set_cd_wake(host->mmc, true);
1726 static int sdhci_esdhc_resume(struct device *dev)
1728 struct sdhci_host *host = dev_get_drvdata(dev);
1731 ret = pinctrl_pm_select_default_state(dev);
1735 /* re-initialize hw state in case it's lost in low power mode */
1736 sdhci_esdhc_imx_hwinit(host);
1738 ret = sdhci_resume_host(host);
1742 if (host->mmc->caps2 & MMC_CAP2_CQE)
1743 ret = cqhci_resume(host->mmc);
1746 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1753 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1755 struct sdhci_host *host = dev_get_drvdata(dev);
1756 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1757 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1760 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1761 ret = cqhci_suspend(host->mmc);
1766 ret = sdhci_runtime_suspend_host(host);
1770 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1771 mmc_retune_needed(host->mmc);
1773 imx_data->actual_clock = host->mmc->actual_clock;
1774 esdhc_pltfm_set_clock(host, 0);
1775 clk_disable_unprepare(imx_data->clk_per);
1776 clk_disable_unprepare(imx_data->clk_ipg);
1777 clk_disable_unprepare(imx_data->clk_ahb);
1779 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1780 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1785 static int sdhci_esdhc_runtime_resume(struct device *dev)
1787 struct sdhci_host *host = dev_get_drvdata(dev);
1788 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1789 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1792 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1793 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1795 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1796 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1798 err = clk_prepare_enable(imx_data->clk_ahb);
1800 goto remove_pm_qos_request;
1802 err = clk_prepare_enable(imx_data->clk_per);
1804 goto disable_ahb_clk;
1806 err = clk_prepare_enable(imx_data->clk_ipg);
1808 goto disable_per_clk;
1810 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1812 err = sdhci_runtime_resume_host(host, 0);
1814 goto disable_ipg_clk;
1816 if (host->mmc->caps2 & MMC_CAP2_CQE)
1817 err = cqhci_resume(host->mmc);
1822 clk_disable_unprepare(imx_data->clk_ipg);
1824 clk_disable_unprepare(imx_data->clk_per);
1826 clk_disable_unprepare(imx_data->clk_ahb);
1827 remove_pm_qos_request:
1828 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1829 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1834 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1835 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1836 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1837 sdhci_esdhc_runtime_resume, NULL)
1840 static struct platform_driver sdhci_esdhc_imx_driver = {
1842 .name = "sdhci-esdhc-imx",
1843 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1844 .of_match_table = imx_esdhc_dt_ids,
1845 .pm = &sdhci_esdhc_pmops,
1847 .probe = sdhci_esdhc_imx_probe,
1848 .remove = sdhci_esdhc_imx_remove,
1851 module_platform_driver(sdhci_esdhc_imx_driver);
1853 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1854 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1855 MODULE_LICENSE("GPL v2");