drivers/mmc/host/sdhci-esdhc-imx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Freescale eSDHC i.MX controller driver for the platform bus.
   4  *
   5  * derived from the OF-version.
   6  *
   7  * Copyright (c) 2010 Pengutronix e.K.
   8  *   Author: Wolfram Sang <kernel@pengutronix.de>
   9  */
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/module.h>
  18 #include <linux/slab.h>
  19 #include <linux/pm_qos.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/mmc.h>
  22 #include <linux/mmc/sdio.h>
  23 #include <linux/mmc/slot-gpio.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/pinctrl/consumer.h>
  27 #include <linux/platform_data/mmc-esdhc-imx.h>
  28 #include <linux/pm_runtime.h>
  29 #include "sdhci-pltfm.h"
  30 #include "sdhci-esdhc.h"
  31 #include "cqhci.h"
  32
  33 #define ESDHC_SYS_CTRL_DTOCV_MASK       0x0f
  34 #define ESDHC_CTRL_D3CD                 0x08
  35 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
  36 /* VENDOR SPEC register */
  37 #define ESDHC_VENDOR_SPEC               0xc0
  38 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  39 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  40 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  41 #define ESDHC_DEBUG_SEL_AND_STATUS_REG          0xc2
  42 #define ESDHC_DEBUG_SEL_REG                     0xc3
  43 #define ESDHC_DEBUG_SEL_MASK                    0xf
  44 #define ESDHC_DEBUG_SEL_CMD_STATE               1
  45 #define ESDHC_DEBUG_SEL_DATA_STATE              2
  46 #define ESDHC_DEBUG_SEL_TRANS_STATE             3
  47 #define ESDHC_DEBUG_SEL_DMA_STATE               4
  48 #define ESDHC_DEBUG_SEL_ADMA_STATE              5
  49 #define ESDHC_DEBUG_SEL_FIFO_STATE              6
  50 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE        7
  51 #define ESDHC_WTMK_LVL                  0x44
  52 #define  ESDHC_WTMK_DEFAULT_VAL         0x10401040
  53 #define  ESDHC_WTMK_LVL_RD_WML_MASK     0x000000FF
  54 #define  ESDHC_WTMK_LVL_RD_WML_SHIFT    0
  55 #define  ESDHC_WTMK_LVL_WR_WML_MASK     0x00FF0000
  56 #define  ESDHC_WTMK_LVL_WR_WML_SHIFT    16
  57 #define  ESDHC_WTMK_LVL_WML_VAL_DEF     64
  58 #define  ESDHC_WTMK_LVL_WML_VAL_MAX     128
  59 #define ESDHC_MIX_CTRL                  0x48
  60 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  61 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  62 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  63 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  64 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN    (1 << 24)
  65 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  66 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
  67 #define  ESDHC_MIX_CTRL_HS400_ES_EN     (1 << 27)
  68 /* Bits 3 and 6 are not SDHCI standard definitions */
  69 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  70 /* Tuning bits */
  71 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  72
  73 /* dll control register */
  74 #define ESDHC_DLL_CTRL                  0x60
  75 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  76 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  77
  78 /* tune control register */
  79 #define ESDHC_TUNE_CTRL_STATUS          0x68
  80 #define  ESDHC_TUNE_CTRL_STEP           1
  81 #define  ESDHC_TUNE_CTRL_MIN            0
  82 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  83
  84 /* strobe dll register */
  85 #define ESDHC_STROBE_DLL_CTRL           0x70
  86 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
  87 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
  88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT    0x7
  89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
  90 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT    (4 << 20)
  91
  92 #define ESDHC_STROBE_DLL_STATUS         0x74
  93 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
  94 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
  95
  96 #define ESDHC_VEND_SPEC2                0xc8
  97 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ    (1 << 8)
  98
  99 #define ESDHC_TUNING_CTRL               0xcc
 100 #define ESDHC_STD_TUNING_EN             (1 << 24)
 101 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
 102 #define ESDHC_TUNING_START_TAP_DEFAULT  0x1
 103 #define ESDHC_TUNING_START_TAP_MASK     0x7f
 104 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE      (1 << 7)
 105 #define ESDHC_TUNING_STEP_MASK          0x00070000
 106 #define ESDHC_TUNING_STEP_SHIFT         16
 107
 108 /* pinctrl state */
 109 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
 110 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
 111
 112 /*
 113  * Our interpretation of the SDHCI_HOST_CONTROL register
 114  */
 115 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
 116 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
 117 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 118
 119 /*
 120  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
 121  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 122  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 123  * Define this macro DMA error INT for fsl eSDHC
 124  */
 125 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
 126
 127 /* the address offset of CQHCI */
 128 #define ESDHC_CQHCI_ADDR_OFFSET         0x100
 129
 130 /*
 131  * The CMDTYPE of the CMD register (offset 0xE) should be set to
 132  * "11" when the STOP CMD12 is issued on imx53 to abort one
 133  * open ended multi-blk IO. Otherwise the TC INT wouldn't
 134  * be generated.
 135  * In exact block transfer, the controller doesn't complete the
 136  * operations automatically as required at the end of the
 137  * transfer and remains on hold if the abort command is not sent.
 138  * As a result, the TC flag is not asserted and SW received timeout
 139  * exception. Bit1 of Vendor Spec register is used to fix it.
 140  */
 141 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 142 /*
 143  * The flag tells that the ESDHC controller is an USDHC block that is
 144  * integrated on the i.MX6 series.
 145  */
 146 #define ESDHC_FLAG_USDHC                BIT(3)
 147 /* The IP supports manual tuning process */
 148 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 149 /* The IP supports standard tuning process */
 150 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 151 /* The IP has SDHCI_CAPABILITIES_1 register */
 152 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 153 /*
 154  * The IP has erratum ERR004536
 155  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 156  * when reading data from the card
 157  * This flag is also set for i.MX25 and i.MX35 in order to get
 158  * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
 159  */
 160 #define ESDHC_FLAG_ERR004536            BIT(7)
 161 /* The IP supports HS200 mode */
 162 #define ESDHC_FLAG_HS200                BIT(8)
 163 /* The IP supports HS400 mode */
 164 #define ESDHC_FLAG_HS400                BIT(9)
 165 /*
 166  * The IP has errata ERR010450
 167  * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
 168  * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
 169  */
 170 #define ESDHC_FLAG_ERR010450            BIT(10)
 171 /* The IP supports HS400ES mode */
 172 #define ESDHC_FLAG_HS400_ES             BIT(11)
 173 /* The IP has Host Controller Interface for Command Queuing */
 174 #define ESDHC_FLAG_CQHCI                BIT(12)
 175 /* need request pmqos during low power */
 176 #define ESDHC_FLAG_PMQOS                BIT(13)
 177 /* The IP state got lost in low power mode */
 178 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE         BIT(14)
 179 /* The IP lost clock rate in PM_RUNTIME */
 180 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME  BIT(15)
 181 /*
 182  * The IP do not support the ACMD23 feature completely when use ADMA mode.
 183  * In ADMA mode, it only use the 16 bit block count of the register 0x4
 184  * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
 185  * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
 186  * write operation in RPMB, because RPMB reliable write need to set the bit31
 187  * of the CMD23's argument.
 188  * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
 189  * do not has this limitation. so when these SoC use ADMA mode, it need to
 190  * disable the ACMD23 feature.
 191  */
 192 #define ESDHC_FLAG_BROKEN_AUTO_CMD23    BIT(16)
 193
 194 struct esdhc_soc_data {
 195         u32 flags;
 196 };
 197
 198 static const struct esdhc_soc_data esdhc_imx25_data = {
 199         .flags = ESDHC_FLAG_ERR004536,
 200 };
 201
 202 static const struct esdhc_soc_data esdhc_imx35_data = {
 203         .flags = ESDHC_FLAG_ERR004536,
 204 };
 205
 206 static const struct esdhc_soc_data esdhc_imx51_data = {
 207         .flags = 0,
 208 };
 209
 210 static const struct esdhc_soc_data esdhc_imx53_data = {
 211         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 212 };
 213
 214 static const struct esdhc_soc_data usdhc_imx6q_data = {
 215         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
 216                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 217 };
 218
 219 static const struct esdhc_soc_data usdhc_imx6sl_data = {
 220         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 221                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
 222                         | ESDHC_FLAG_HS200
 223                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 224 };
 225
 226 static const struct esdhc_soc_data usdhc_imx6sll_data = {
 227         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 228                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 229                         | ESDHC_FLAG_HS400
 230                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 231 };
 232
 233 static const struct esdhc_soc_data usdhc_imx6sx_data = {
 234         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 235                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 236                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 237                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 238 };
 239
 240 static const struct esdhc_soc_data usdhc_imx6ull_data = {
 241         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 242                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 243                         | ESDHC_FLAG_ERR010450
 244                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 245 };
 246
 247 static const struct esdhc_soc_data usdhc_imx7d_data = {
 248         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 249                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 250                         | ESDHC_FLAG_HS400
 251                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 252                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 253 };
 254
 255 static struct esdhc_soc_data usdhc_imx7ulp_data = {
 256         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 257                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 258                         | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
 259                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 260 };
 261
 262 static struct esdhc_soc_data usdhc_imx8qxp_data = {
 263         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 264                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 265                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 266                         | ESDHC_FLAG_CQHCI
 267                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 268                         | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
 269 };
 270
 271 static struct esdhc_soc_data usdhc_imx8mm_data = {
 272         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 273                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 274                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 275                         | ESDHC_FLAG_CQHCI
 276                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 277 };
 278
 279 struct pltfm_imx_data {
 280         u32 scratchpad;
 281         struct pinctrl *pinctrl;
 282         struct pinctrl_state *pins_100mhz;
 283         struct pinctrl_state *pins_200mhz;
 284         const struct esdhc_soc_data *socdata;
 285         struct esdhc_platform_data boarddata;
 286         struct clk *clk_ipg;
 287         struct clk *clk_ahb;
 288         struct clk *clk_per;
 289         unsigned int actual_clock;
 290         enum {
 291                 NO_CMD_PENDING,      /* no multiblock command pending */
 292                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 293                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 294         } multiblock_status;
 295         u32 is_ddr;
 296         struct pm_qos_request pm_qos_req;
 297 };
 298
 299 static const struct of_device_id imx_esdhc_dt_ids[] = {
 300         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 301         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 302         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 303         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 304         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
 305         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 306         { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
 307         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 308         { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
 309         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
 310         { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
 311         { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
 312         { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
 313         { /* sentinel */ }
 314 };
 315 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 316
 317 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 318 {
 319         return data->socdata == &esdhc_imx25_data;
 320 }
 321
 322 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 323 {
 324         return data->socdata == &esdhc_imx53_data;
 325 }
 326
 327 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 328 {
 329         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 330 }
 331
 332 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 333 {
 334         void __iomem *base = host->ioaddr + (reg & ~0x3);
 335         u32 shift = (reg & 0x3) * 8;
 336
 337         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 338 }
 339
 340 #define DRIVER_NAME "sdhci-esdhc-imx"
 341 #define ESDHC_IMX_DUMP(f, x...) \
 342         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
 343 static void esdhc_dump_debug_regs(struct sdhci_host *host)
 344 {
 345         int i;
 346         char *debug_status[7] = {
 347                                  "cmd debug status",
 348                                  "data debug status",
 349                                  "trans debug status",
 350                                  "dma debug status",
 351                                  "adma debug status",
 352                                  "fifo debug status",
 353                                  "async fifo debug status"
 354         };
 355
 356         ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
 357         for (i = 0; i < 7; i++) {
 358                 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
 359                         ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
 360                 ESDHC_IMX_DUMP("%s:  0x%04x\n", debug_status[i],
 361                         readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
 362         }
 363
 364         esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
 365
 366 }
 367
 368 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
 369 {
 370         u32 present_state;
 371         int ret;
 372
 373         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
 374                                 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
 375         if (ret == -ETIMEDOUT)
 376                 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
 377 }
 378
 379 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 380 {
 381         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 382         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 383         u32 val = readl(host->ioaddr + reg);
 384
 385         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 386                 u32 fsl_prss = val;
 387                 /* save the least 20 bits */
 388                 val = fsl_prss & 0x000FFFFF;
 389                 /* move dat[0-3] bits */
 390                 val |= (fsl_prss & 0x0F000000) >> 4;
 391                 /* move cmd line bit */
 392                 val |= (fsl_prss & 0x00800000) << 1;
 393         }
 394
 395         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 396                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 397                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 398                         val &= 0xffff0000;
 399
 400                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 401                  * ADMA2 capability of esdhc, but this bit is messed up on
 402                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 403                  * don't actually support ADMA2). So set the BROKEN_ADMA
 404                  * quirk on MX25/35 platforms.
 405                  */
 406
 407                 if (val & SDHCI_CAN_DO_ADMA1) {
 408                         val &= ~SDHCI_CAN_DO_ADMA1;
 409                         val |= SDHCI_CAN_DO_ADMA2;
 410                 }
 411         }
 412
 413         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 414                 if (esdhc_is_usdhc(imx_data)) {
 415                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 416                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 417                         else
 418                                 /* imx6q/dl does not have cap_1 register, fake one */
 419                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 420                                         | SDHCI_SUPPORT_SDR50
 421                                         | SDHCI_USE_SDR50_TUNING
 422                                         | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
 423                                                      SDHCI_TUNING_MODE_3);
 424
 425                         /*
 426                          * Do not advertise faster UHS modes if there are no
 427                          * pinctrl states for 100MHz/200MHz.
 428                          */
 429                         if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
 430                                 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
 431                         if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
 432                                 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
 433                 }
 434         }
 435
 436         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 437                 val = 0;
 438                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
 439                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
 440                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
 441         }
 442
 443         if (unlikely(reg == SDHCI_INT_STATUS)) {
 444                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 445                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 446                         val |= SDHCI_INT_ADMA_ERROR;
 447                 }
 448
 449                 /*
 450                  * mask off the interrupt we get in response to the manually
 451                  * sent CMD12
 452                  */
 453                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 454                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 455                         val &= ~SDHCI_INT_RESPONSE;
 456                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 457                                                    SDHCI_INT_STATUS);
 458                         imx_data->multiblock_status = NO_CMD_PENDING;
 459                 }
 460         }
 461
 462         return val;
 463 }
 464
 465 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 466 {
 467         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 468         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 469         u32 data;
 470
 471         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
 472                         reg == SDHCI_INT_STATUS)) {
 473                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
 474                         /*
 475                          * Clear and then set D3CD bit to avoid missing the
 476                          * card interrupt. This is an eSDHC controller problem
 477                          * so we need to apply the following workaround: clear
 478                          * and set D3CD bit will make eSDHC re-sample the card
 479                          * interrupt. In case a card interrupt was lost,
 480                          * re-sample it by the following steps.
 481                          */
 482                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 483                         data &= ~ESDHC_CTRL_D3CD;
 484                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 485                         data |= ESDHC_CTRL_D3CD;
 486                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 487                 }
 488
 489                 if (val & SDHCI_INT_ADMA_ERROR) {
 490                         val &= ~SDHCI_INT_ADMA_ERROR;
 491                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 492                 }
 493         }
 494
 495         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 496                                 && (reg == SDHCI_INT_STATUS)
 497                                 && (val & SDHCI_INT_DATA_END))) {
 498                         u32 v;
 499                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 500                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 501                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 502
 503                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 504                         {
 505                                 /* send a manual CMD12 with RESPTYP=none */
 506                                 data = MMC_STOP_TRANSMISSION << 24 |
 507                                        SDHCI_CMD_ABORTCMD << 16;
 508                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 509                                 imx_data->multiblock_status = WAIT_FOR_INT;
 510                         }
 511         }
 512
 513         writel(val, host->ioaddr + reg);
 514 }
 515
 516 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 517 {
 518         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 519         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 520         u16 ret = 0;
 521         u32 val;
 522
 523         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 524                 reg ^= 2;
 525                 if (esdhc_is_usdhc(imx_data)) {
 526                         /*
 527                          * The usdhc register returns a wrong host version.
 528                          * Correct it here.
 529                          */
 530                         return SDHCI_SPEC_300;
 531                 }
 532         }
 533
 534         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 535                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 536                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 537                         ret |= SDHCI_CTRL_VDD_180;
 538
 539                 if (esdhc_is_usdhc(imx_data)) {
 540                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 541                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 542                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 543                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 544                                 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 545                 }
 546
 547                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 548                         ret |= SDHCI_CTRL_EXEC_TUNING;
 549                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 550                         ret |= SDHCI_CTRL_TUNED_CLK;
 551
 552                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 553
 554                 return ret;
 555         }
 556
 557         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 558                 if (esdhc_is_usdhc(imx_data)) {
 559                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 560                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 561                         /* Swap AC23 bit */
 562                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 563                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 564                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 565                         }
 566                 } else {
 567                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 568                 }
 569
 570                 return ret;
 571         }
 572
 573         return readw(host->ioaddr + reg);
 574 }
 575
 576 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 577 {
 578         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 579         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 580         u32 new_val = 0;
 581
 582         switch (reg) {
 583         case SDHCI_CLOCK_CONTROL:
 584                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 585                 if (val & SDHCI_CLOCK_CARD_EN)
 586                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 587                 else
 588                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 589                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 590                 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
 591                         esdhc_wait_for_card_clock_gate_off(host);
 592                 return;
 593         case SDHCI_HOST_CONTROL2:
 594                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 595                 if (val & SDHCI_CTRL_VDD_180)
 596                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 597                 else
 598                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 599                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 600                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 601                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 602                         if (val & SDHCI_CTRL_TUNED_CLK) {
 603                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 604                                 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 605                         } else {
 606                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 607                                 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 608                         }
 609                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 610                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 611                         u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 612                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 613                         if (val & SDHCI_CTRL_TUNED_CLK) {
 614                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 615                         } else {
 616                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 617                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 618                                 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 619                         }
 620
 621                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 622                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 623                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 624                                 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 625                         } else {
 626                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 627                         }
 628
 629                         writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 630                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 631                 }
 632                 return;
 633         case SDHCI_TRANSFER_MODE:
 634                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 635                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 636                                 && (host->cmd->data->blocks > 1)
 637                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 638                         u32 v;
 639                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 640                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 641                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 642                 }
 643
 644                 if (esdhc_is_usdhc(imx_data)) {
 645                         u32 wml;
 646                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 647                         /* Swap AC23 bit */
 648                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 649                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 650                                 val |= ESDHC_MIX_CTRL_AC23EN;
 651                         }
 652                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 653                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 654
 655                         /* Set watermark levels for PIO access to maximum value
 656                          * (128 words) to accommodate full 512 bytes buffer.
 657                          * For DMA access restore the levels to default value.
 658                          */
 659                         m = readl(host->ioaddr + ESDHC_WTMK_LVL);
 660                         if (val & SDHCI_TRNS_DMA) {
 661                                 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
 662                         } else {
 663                                 u8 ctrl;
 664                                 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
 665
 666                                 /*
 667                                  * Since already disable DMA mode, so also need
 668                                  * to clear the DMASEL. Otherwise, for standard
 669                                  * tuning, when send tuning command, usdhc will
 670                                  * still prefetch the ADMA script from wrong
 671                                  * DMA address, then we will see IOMMU report
 672                                  * some error which show lack of TLB mapping.
 673                                  */
 674                                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 675                                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 676                                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 677                         }
 678                         m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
 679                                ESDHC_WTMK_LVL_WR_WML_MASK);
 680                         m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
 681                              (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
 682                         writel(m, host->ioaddr + ESDHC_WTMK_LVL);
 683                 } else {
 684                         /*
 685                          * Postpone this write, we must do it together with a
 686                          * command write that is down below.
 687                          */
 688                         imx_data->scratchpad = val;
 689                 }
 690                 return;
 691         case SDHCI_COMMAND:
 692                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 693                         val |= SDHCI_CMD_ABORTCMD;
 694
 695                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 696                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 697                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 698
 699                 if (esdhc_is_usdhc(imx_data))
 700                         writel(val << 16,
 701                                host->ioaddr + SDHCI_TRANSFER_MODE);
 702                 else
 703                         writel(val << 16 | imx_data->scratchpad,
 704                                host->ioaddr + SDHCI_TRANSFER_MODE);
 705                 return;
 706         case SDHCI_BLOCK_SIZE:
 707                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 708                 break;
 709         }
 710         esdhc_clrset_le(host, 0xffff, val, reg);
 711 }
 712
 713 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
 714 {
 715         u8 ret;
 716         u32 val;
 717
 718         switch (reg) {
 719         case SDHCI_HOST_CONTROL:
 720                 val = readl(host->ioaddr + reg);
 721
 722                 ret = val & SDHCI_CTRL_LED;
 723                 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
 724                 ret |= (val & ESDHC_CTRL_4BITBUS);
 725                 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
 726                 return ret;
 727         }
 728
 729         return readb(host->ioaddr + reg);
 730 }
 731
 732 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 733 {
 734         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 735         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 736         u32 new_val = 0;
 737         u32 mask;
 738
 739         switch (reg) {
 740         case SDHCI_POWER_CONTROL:
 741                 /*
 742                  * FSL put some DMA bits here
 743                  * If your board has a regulator, code should be here
 744                  */
 745                 return;
 746         case SDHCI_HOST_CONTROL:
 747                 /* FSL messed up here, so we need to manually compose it. */
 748                 new_val = val & SDHCI_CTRL_LED;
 749                 /* ensure the endianness */
 750                 new_val |= ESDHC_HOST_CONTROL_LE;
 751                 /* bits 8&9 are reserved on mx25 */
 752                 if (!is_imx25_esdhc(imx_data)) {
 753                         /* DMA mode bits are shifted */
 754                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 755                 }
 756
 757                 /*
 758                  * Do not touch buswidth bits here. This is done in
 759                  * esdhc_pltfm_bus_width.
 760                  * Do not touch the D3CD bit either which is used for the
 761                  * SDIO interrupt erratum workaround.
 762                  */
 763                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 764
 765                 esdhc_clrset_le(host, mask, new_val, reg);
 766                 return;
 767         case SDHCI_SOFTWARE_RESET:
 768                 if (val & SDHCI_RESET_DATA)
 769                         new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 770                 break;
 771         }
 772         esdhc_clrset_le(host, 0xff, val, reg);
 773
 774         if (reg == SDHCI_SOFTWARE_RESET) {
 775                 if (val & SDHCI_RESET_ALL) {
 776                         /*
 777                          * The esdhc has a design violation to SDHC spec which
 778                          * tells that software reset should not affect card
 779                          * detection circuit. But esdhc clears its SYSCTL
 780                          * register bits [0..2] during the software reset. This
 781                          * will stop those clocks that card detection circuit
 782                          * relies on. To work around it, we turn the clocks on
 783                          * back to keep card detection circuit functional.
 784                          */
 785                         esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 786                         /*
 787                          * The reset on usdhc fails to clear MIX_CTRL register.
 788                          * Do it manually here.
 789                          */
 790                         if (esdhc_is_usdhc(imx_data)) {
 791                                 /*
 792                                  * the tuning bits should be kept during reset
 793                                  */
 794                                 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 795                                 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 796                                                 host->ioaddr + ESDHC_MIX_CTRL);
 797                                 imx_data->is_ddr = 0;
 798                         }
 799                 } else if (val & SDHCI_RESET_DATA) {
 800                         /*
 801                          * The eSDHC DAT line software reset clears at least the
 802                          * data transfer width on i.MX25, so make sure that the
 803                          * Host Control register is unaffected.
 804                          */
 805                         esdhc_clrset_le(host, 0xff, new_val,
 806                                         SDHCI_HOST_CONTROL);
 807                 }
 808         }
 809 }
 810
 811 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 812 {
 813         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 814
 815         return pltfm_host->clock;
 816 }
 817
 818 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 819 {
 820         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 821
 822         return pltfm_host->clock / 256 / 16;
 823 }
 824
 825 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 826                                          unsigned int clock)
 827 {
 828         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 829         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 830         unsigned int host_clock = pltfm_host->clock;
 831         int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
 832         int pre_div = 1;
 833         int div = 1;
 834         int ret;
 835         u32 temp, val;
 836
 837         if (esdhc_is_usdhc(imx_data)) {
 838                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 839                 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 840                         host->ioaddr + ESDHC_VENDOR_SPEC);
 841                 esdhc_wait_for_card_clock_gate_off(host);
 842         }
 843
 844         if (clock == 0) {
 845                 host->mmc->actual_clock = 0;
 846                 return;
 847         }
 848
 849         /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
 850         if (is_imx53_esdhc(imx_data)) {
 851                 /*
 852                  * According to the i.MX53 reference manual, if DLLCTRL[10] can
 853                  * be set, then the controller is eSDHCv3, else it is eSDHCv2.
 854                  */
 855                 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
 856                 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
 857                 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
 858                 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
 859                 if (temp & BIT(10))
 860                         pre_div = 2;
 861         }
 862
 863         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 864         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 865                 | ESDHC_CLOCK_MASK);
 866         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 867
 868         if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
 869                 unsigned int max_clock;
 870
 871                 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
 872
 873                 clock = min(clock, max_clock);
 874         }
 875
 876         while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
 877                         pre_div < 256)
 878                 pre_div *= 2;
 879
 880         while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
 881                 div++;
 882
 883         host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
 884         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 885                 clock, host->mmc->actual_clock);
 886
 887         pre_div >>= 1;
 888         div--;
 889
 890         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 891         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 892                 | (div << ESDHC_DIVIDER_SHIFT)
 893                 | (pre_div << ESDHC_PREDIV_SHIFT));
 894         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 895
 896         /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
 897         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
 898                                 (temp & ESDHC_CLOCK_STABLE), 2, 100);
 899         if (ret == -ETIMEDOUT)
 900                 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
 901
 902         if (esdhc_is_usdhc(imx_data)) {
 903                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 904                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 905                         host->ioaddr + ESDHC_VENDOR_SPEC);
 906         }
 907
 908 }
 909
 910 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 911 {
 912         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 913         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 914         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 915
 916         switch (boarddata->wp_type) {
 917         case ESDHC_WP_GPIO:
 918                 return mmc_gpio_get_ro(host->mmc);
 919         case ESDHC_WP_CONTROLLER:
 920                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 921                                SDHCI_WRITE_PROTECT);
 922         case ESDHC_WP_NONE:
 923                 break;
 924         }
 925
 926         return -ENOSYS;
 927 }
 928
 929 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 930 {
 931         u32 ctrl;
 932
 933         switch (width) {
 934         case MMC_BUS_WIDTH_8:
 935                 ctrl = ESDHC_CTRL_8BITBUS;
 936                 break;
 937         case MMC_BUS_WIDTH_4:
 938                 ctrl = ESDHC_CTRL_4BITBUS;
 939                 break;
 940         default:
 941                 ctrl = 0;
 942                 break;
 943         }
 944
 945         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 946                         SDHCI_HOST_CONTROL);
 947 }
 948
 949 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 950 {
 951         struct sdhci_host *host = mmc_priv(mmc);
 952
 953         /*
 954          * i.MX uSDHC internally already uses a fixed optimized timing for
 955          * DDR50, normally does not require tuning for DDR50 mode.
 956          */
 957         if (host->timing == MMC_TIMING_UHS_DDR50)
 958                 return 0;
 959
 960         return sdhci_execute_tuning(mmc, opcode);
 961 }
 962
 963 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 964 {
 965         u32 reg;
 966         u8 sw_rst;
 967         int ret;
 968
 969         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 970         mdelay(1);
 971
 972         /* IC suggest to reset USDHC before every tuning command */
 973         esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
 974         ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
 975                                 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
 976         if (ret == -ETIMEDOUT)
 977                 dev_warn(mmc_dev(host->mmc),
 978                 "warning! RESET_ALL never complete before sending tuning command\n");
 979
 980         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 981         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 982                         ESDHC_MIX_CTRL_FBCLK_SEL;
 983         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 984         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 985         dev_dbg(mmc_dev(host->mmc),
 986                 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 987                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 988 }
 989
 990 static void esdhc_post_tuning(struct sdhci_host *host)
 991 {
 992         u32 reg;
 993
 994         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 995         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 996         reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 997         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 998 }
 999
1000 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1001 {
1002         int min, max, avg, ret;
1003
1004         /* find the mininum delay first which can pass tuning */
1005         min = ESDHC_TUNE_CTRL_MIN;
1006         while (min < ESDHC_TUNE_CTRL_MAX) {
1007                 esdhc_prepare_tuning(host, min);
1008                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1009                         break;
1010                 min += ESDHC_TUNE_CTRL_STEP;
1011         }
1012
1013         /* find the maxinum delay which can not pass tuning */
1014         max = min + ESDHC_TUNE_CTRL_STEP;
1015         while (max < ESDHC_TUNE_CTRL_MAX) {
1016                 esdhc_prepare_tuning(host, max);
1017                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1018                         max -= ESDHC_TUNE_CTRL_STEP;
1019                         break;
1020                 }
1021                 max += ESDHC_TUNE_CTRL_STEP;
1022         }
1023
1024         /* use average delay to get the best timing */
1025         avg = (min + max) / 2;
1026         esdhc_prepare_tuning(host, avg);
1027         ret = mmc_send_tuning(host->mmc, opcode, NULL);
1028         esdhc_post_tuning(host);
1029
1030         dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1031                 ret ? "failed" : "passed", avg, ret);
1032
1033         return ret;
1034 }
1035
1036 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1037 {
1038         struct sdhci_host *host = mmc_priv(mmc);
1039         u32 m;
1040
1041         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1042         if (ios->enhanced_strobe)
1043                 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1044         else
1045                 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1046         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1047 }
1048
1049 static int esdhc_change_pinstate(struct sdhci_host *host,
1050                                                 unsigned int uhs)
1051 {
1052         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1053         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1054         struct pinctrl_state *pinctrl;
1055
1056         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1057
1058         if (IS_ERR(imx_data->pinctrl) ||
1059                 IS_ERR(imx_data->pins_100mhz) ||
1060                 IS_ERR(imx_data->pins_200mhz))
1061                 return -EINVAL;
1062
1063         switch (uhs) {
1064         case MMC_TIMING_UHS_SDR50:
1065         case MMC_TIMING_UHS_DDR50:
1066                 pinctrl = imx_data->pins_100mhz;
1067                 break;
1068         case MMC_TIMING_UHS_SDR104:
1069         case MMC_TIMING_MMC_HS200:
1070         case MMC_TIMING_MMC_HS400:
1071                 pinctrl = imx_data->pins_200mhz;
1072                 break;
1073         default:
1074                 /* back to default state for other legacy timing */
1075                 return pinctrl_select_default_state(mmc_dev(host->mmc));
1076         }
1077
1078         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1079 }
1080
1081 /*
1082  * For HS400 eMMC, there is a data_strobe line. This signal is generated
1083  * by the device and used for data output and CRC status response output
1084  * in HS400 mode. The frequency of this signal follows the frequency of
1085  * CLK generated by host. The host receives the data which is aligned to the
1086  * edge of data_strobe line. Due to the time delay between CLK line and
1087  * data_strobe line, if the delay time is larger than one clock cycle,
1088  * then CLK and data_strobe line will be misaligned, read error shows up.
1089  */
1090 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1091 {
1092         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1093         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1094         u32 strobe_delay;
1095         u32 v;
1096         int ret;
1097
1098         /* disable clock before enabling strobe dll */
1099         writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1100                 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1101                 host->ioaddr + ESDHC_VENDOR_SPEC);
1102         esdhc_wait_for_card_clock_gate_off(host);
1103
1104         /* force a reset on strobe dll */
1105         writel(ESDHC_STROBE_DLL_CTRL_RESET,
1106                 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1107         /* clear the reset bit on strobe dll before any setting */
1108         writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1109
1110         /*
1111          * enable strobe dll ctrl and adjust the delay target
1112          * for the uSDHC loopback read clock
1113          */
1114         if (imx_data->boarddata.strobe_dll_delay_target)
1115                 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1116         else
1117                 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1118         v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1119                 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1120                 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1121         writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1122
1123         /* wait max 50us to get the REF/SLV lock */
1124         ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1125                 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1126         if (ret == -ETIMEDOUT)
1127                 dev_warn(mmc_dev(host->mmc),
1128                 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1129 }
1130
1131 static void esdhc_reset_tuning(struct sdhci_host *host)
1132 {
1133         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1134         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1135         u32 ctrl;
1136
1137         /* Reset the tuning circuit */
1138         if (esdhc_is_usdhc(imx_data)) {
1139                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1140                         ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1141                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1142                         ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1143                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1144                         writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1145                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1146                         ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1147                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1148                         writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1149                 }
1150         }
1151 }
1152
1153 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1154 {
1155         u32 m;
1156         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1157         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1158         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1159
1160         /* disable ddr mode and disable HS400 mode */
1161         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1162         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1163         imx_data->is_ddr = 0;
1164
1165         switch (timing) {
1166         case MMC_TIMING_UHS_SDR12:
1167         case MMC_TIMING_UHS_SDR25:
1168         case MMC_TIMING_UHS_SDR50:
1169         case MMC_TIMING_UHS_SDR104:
1170         case MMC_TIMING_MMC_HS:
1171         case MMC_TIMING_MMC_HS200:
1172                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1173                 break;
1174         case MMC_TIMING_UHS_DDR50:
1175         case MMC_TIMING_MMC_DDR52:
1176                 m |= ESDHC_MIX_CTRL_DDREN;
1177                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1178                 imx_data->is_ddr = 1;
1179                 if (boarddata->delay_line) {
1180                         u32 v;
1181                         v = boarddata->delay_line <<
1182                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1183                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1184                         if (is_imx53_esdhc(imx_data))
1185                                 v <<= 1;
1186                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1187                 }
1188                 break;
1189         case MMC_TIMING_MMC_HS400:
1190                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1191                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1192                 imx_data->is_ddr = 1;
1193                 /* update clock after enable DDR for strobe DLL lock */
1194                 host->ops->set_clock(host, host->clock);
1195                 esdhc_set_strobe_dll(host);
1196                 break;
1197         case MMC_TIMING_LEGACY:
1198         default:
1199                 esdhc_reset_tuning(host);
1200                 break;
1201         }
1202
1203         esdhc_change_pinstate(host, timing);
1204 }
1205
1206 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1207 {
1208         sdhci_reset(host, mask);
1209
1210         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1211         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1212 }
1213
1214 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1215 {
1216         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1217         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1218
1219         /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1220         return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1221 }
1222
1223 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1224 {
1225         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1226         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1227
1228         /* use maximum timeout counter */
1229         esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1230                         esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1231                         SDHCI_TIMEOUT_CONTROL);
1232 }
1233
1234 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1235 {
1236         int cmd_error = 0;
1237         int data_error = 0;
1238
1239         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1240                 return intmask;
1241
1242         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1243
1244         return 0;
1245 }
1246
1247 static struct sdhci_ops sdhci_esdhc_ops = {
1248         .read_l = esdhc_readl_le,
1249         .read_w = esdhc_readw_le,
1250         .read_b = esdhc_readb_le,
1251         .write_l = esdhc_writel_le,
1252         .write_w = esdhc_writew_le,
1253         .write_b = esdhc_writeb_le,
1254         .set_clock = esdhc_pltfm_set_clock,
1255         .get_max_clock = esdhc_pltfm_get_max_clock,
1256         .get_min_clock = esdhc_pltfm_get_min_clock,
1257         .get_max_timeout_count = esdhc_get_max_timeout_count,
1258         .get_ro = esdhc_pltfm_get_ro,
1259         .set_timeout = esdhc_set_timeout,
1260         .set_bus_width = esdhc_pltfm_set_bus_width,
1261         .set_uhs_signaling = esdhc_set_uhs_signaling,
1262         .reset = esdhc_reset,
1263         .irq = esdhc_cqhci_irq,
1264         .dump_vendor_regs = esdhc_dump_debug_regs,
1265 };
1266
1267 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1268         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1269                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1270                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1271                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1272         .ops = &sdhci_esdhc_ops,
1273 };
1274
1275 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1276 {
1277         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1278         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1279         struct cqhci_host *cq_host = host->mmc->cqe_private;
1280         int tmp;
1281
1282         if (esdhc_is_usdhc(imx_data)) {
1283                 /*
1284                  * The imx6q ROM code will change the default watermark
1285                  * level setting to something insane.  Change it back here.
1286                  */
1287                 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1288
1289                 /*
1290                  * ROM code will change the bit burst_length_enable setting
1291                  * to zero if this usdhc is chosen to boot system. Change
1292                  * it back here, otherwise it will impact the performance a
1293                  * lot. This bit is used to enable/disable the burst length
1294                  * for the external AHB2AXI bridge. It's useful especially
1295                  * for INCR transfer because without burst length indicator,
1296                  * the AHB2AXI bridge does not know the burst length in
1297                  * advance. And without burst length indicator, AHB INCR
1298                  * transfer can only be converted to singles on the AXI side.
1299                  */
1300                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1301                         | ESDHC_BURST_LEN_EN_INCR,
1302                         host->ioaddr + SDHCI_HOST_CONTROL);
1303
1304                 /*
1305                  * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1306                  * TO1.1, it's harmless for MX6SL
1307                  */
1308                 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1309                         host->ioaddr + 0x6c);
1310
1311                 /* disable DLL_CTRL delay line settings */
1312                 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1313
1314                 /*
1315                  * For the case of command with busy, if set the bit
1316                  * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1317                  * transfer complete interrupt when busy is deasserted.
1318                  * When CQHCI use DCMD to send a CMD need R1b respons,
1319                  * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1320                  * otherwise DCMD will always meet timeout waiting for
1321                  * hardware interrupt issue.
1322                  */
1323                 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1324                         tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1325                         tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1326                         writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1327
1328                         host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1329                 }
1330
1331                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1332                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1333                         tmp |= ESDHC_STD_TUNING_EN |
1334                                 ESDHC_TUNING_START_TAP_DEFAULT;
1335                         if (imx_data->boarddata.tuning_start_tap) {
1336                                 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1337                                 tmp |= imx_data->boarddata.tuning_start_tap;
1338                         }
1339
1340                         if (imx_data->boarddata.tuning_step) {
1341                                 tmp &= ~ESDHC_TUNING_STEP_MASK;
1342                                 tmp |= imx_data->boarddata.tuning_step
1343                                         << ESDHC_TUNING_STEP_SHIFT;
1344                         }
1345
1346                         /* Disable the CMD CRC check for tuning, if not, need to
1347                          * add some delay after every tuning command, because
1348                          * hardware standard tuning logic will directly go to next
1349                          * step once it detect the CMD CRC error, will not wait for
1350                          * the card side to finally send out the tuning data, trigger
1351                          * the buffer read ready interrupt immediately. If usdhc send
1352                          * the next tuning command some eMMC card will stuck, can't
1353                          * response, block the tuning procedure or the first command
1354                          * after the whole tuning procedure always can't get any response.
1355                          */
1356                         tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1357                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1358                 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1359                         /*
1360                          * ESDHC_STD_TUNING_EN may be configed in bootloader
1361                          * or ROM code, so clear this bit here to make sure
1362                          * the manual tuning can work.
1363                          */
1364                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1365                         tmp &= ~ESDHC_STD_TUNING_EN;
1366                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1367                 }
1368
1369                 /*
1370                  * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1371                  * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
1372                  * the 1st linux configure power/clock for the 2nd Linux.
1373                  *
1374                  * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1375                  * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1376                  * After we clear the pending interrupt and halt CQCTL, issue gone.
1377                  */
1378                 if (cq_host) {
1379                         tmp = cqhci_readl(cq_host, CQHCI_IS);
1380                         cqhci_writel(cq_host, tmp, CQHCI_IS);
1381                         cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1382                 }
1383         }
1384 }
1385
1386 static void esdhc_cqe_enable(struct mmc_host *mmc)
1387 {
1388         struct sdhci_host *host = mmc_priv(mmc);
1389         struct cqhci_host *cq_host = mmc->cqe_private;
1390         u32 reg;
1391         u16 mode;
1392         int count = 10;
1393
1394         /*
1395          * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1396          * the case after tuning, so ensure the buffer is drained.
1397          */
1398         reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1399         while (reg & SDHCI_DATA_AVAILABLE) {
1400                 sdhci_readl(host, SDHCI_BUFFER);
1401                 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1402                 if (count-- == 0) {
1403                         dev_warn(mmc_dev(host->mmc),
1404                                 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1405                         break;
1406                 }
1407                 mdelay(1);
1408         }
1409
1410         /*
1411          * Runtime resume will reset the entire host controller, which
1412          * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1413          * Here set DMAEN and BCEN when enable CMDQ.
1414          */
1415         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1416         if (host->flags & SDHCI_REQ_USE_DMA)
1417                 mode |= SDHCI_TRNS_DMA;
1418         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1419                 mode |= SDHCI_TRNS_BLK_CNT_EN;
1420         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1421
1422         /*
1423          * Though Runtime resume reset the entire host controller,
1424          * but do not impact the CQHCI side, need to clear the
1425          * HALT bit, avoid CQHCI stuck in the first request when
1426          * system resume back.
1427          */
1428         cqhci_writel(cq_host, 0, CQHCI_CTL);
1429         if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
1430                 dev_err(mmc_dev(host->mmc),
1431                         "failed to exit halt state when enable CQE\n");
1432
1433
1434         sdhci_cqe_enable(mmc);
1435 }
1436
1437 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1438 {
1439         sdhci_dumpregs(mmc_priv(mmc));
1440 }
1441
1442 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1443         .enable         = esdhc_cqe_enable,
1444         .disable        = sdhci_cqe_disable,
1445         .dumpregs       = esdhc_sdhci_dumpregs,
1446 };
1447
1448 static int
1449 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1450                          struct sdhci_host *host,
1451                          struct pltfm_imx_data *imx_data)
1452 {
1453         struct device_node *np = pdev->dev.of_node;
1454         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1455         int ret;
1456
1457         if (of_get_property(np, "fsl,wp-controller", NULL))
1458                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1459
1460         /*
1461          * If we have this property, then activate WP check.
1462          * Retrieveing and requesting the actual WP GPIO will happen
1463          * in the call to mmc_of_parse().
1464          */
1465         if (of_property_read_bool(np, "wp-gpios"))
1466                 boarddata->wp_type = ESDHC_WP_GPIO;
1467
1468         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1469         of_property_read_u32(np, "fsl,tuning-start-tap",
1470                              &boarddata->tuning_start_tap);
1471
1472         of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1473                                 &boarddata->strobe_dll_delay_target);
1474         if (of_find_property(np, "no-1-8-v", NULL))
1475                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1476
1477         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1478                 boarddata->delay_line = 0;
1479
1480         mmc_of_parse_voltage(host->mmc, &host->ocr_mask);
1481
1482         if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1483                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1484                                                 ESDHC_PINCTRL_STATE_100MHZ);
1485                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1486                                                 ESDHC_PINCTRL_STATE_200MHZ);
1487         }
1488
1489         /* call to generic mmc_of_parse to support additional capabilities */
1490         ret = mmc_of_parse(host->mmc);
1491         if (ret)
1492                 return ret;
1493
1494         if (mmc_gpio_get_cd(host->mmc) >= 0)
1495                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1496
1497         return 0;
1498 }
1499
1500 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1501 {
1502         struct sdhci_pltfm_host *pltfm_host;
1503         struct sdhci_host *host;
1504         struct cqhci_host *cq_host;
1505         int err;
1506         struct pltfm_imx_data *imx_data;
1507
1508         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1509                                 sizeof(*imx_data));
1510         if (IS_ERR(host))
1511                 return PTR_ERR(host);
1512
1513         pltfm_host = sdhci_priv(host);
1514
1515         imx_data = sdhci_pltfm_priv(pltfm_host);
1516
1517         imx_data->socdata = device_get_match_data(&pdev->dev);
1518
1519         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1520                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1521
1522         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1523         if (IS_ERR(imx_data->clk_ipg)) {
1524                 err = PTR_ERR(imx_data->clk_ipg);
1525                 goto free_sdhci;
1526         }
1527
1528         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1529         if (IS_ERR(imx_data->clk_ahb)) {
1530                 err = PTR_ERR(imx_data->clk_ahb);
1531                 goto free_sdhci;
1532         }
1533
1534         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1535         if (IS_ERR(imx_data->clk_per)) {
1536                 err = PTR_ERR(imx_data->clk_per);
1537                 goto free_sdhci;
1538         }
1539
1540         pltfm_host->clk = imx_data->clk_per;
1541         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1542         err = clk_prepare_enable(imx_data->clk_per);
1543         if (err)
1544                 goto free_sdhci;
1545         err = clk_prepare_enable(imx_data->clk_ipg);
1546         if (err)
1547                 goto disable_per_clk;
1548         err = clk_prepare_enable(imx_data->clk_ahb);
1549         if (err)
1550                 goto disable_ipg_clk;
1551
1552         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1553         if (IS_ERR(imx_data->pinctrl))
1554                 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1555
1556         if (esdhc_is_usdhc(imx_data)) {
1557                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1558                 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1559
1560                 /* GPIO CD can be set as a wakeup source */
1561                 host->mmc->caps |= MMC_CAP_CD_WAKE;
1562
1563                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1564                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1565
1566                 /* clear tuning bits in case ROM has set it already */
1567                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1568                 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1569                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1570
1571                 /*
1572                  * Link usdhc specific mmc_host_ops execute_tuning function,
1573                  * to replace the standard one in sdhci_ops.
1574                  */
1575                 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1576         }
1577
1578         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1579                 sdhci_esdhc_ops.platform_execute_tuning =
1580                                         esdhc_executing_tuning;
1581
1582         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1583                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1584
1585         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1586                 host->mmc->caps2 |= MMC_CAP2_HS400;
1587
1588         if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1589                 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1590
1591         if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1592                 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1593                 host->mmc_host_ops.hs400_enhanced_strobe =
1594                                         esdhc_hs400_enhanced_strobe;
1595         }
1596
1597         if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1598                 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1599                 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1600                 if (!cq_host) {
1601                         err = -ENOMEM;
1602                         goto disable_ahb_clk;
1603                 }
1604
1605                 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1606                 cq_host->ops = &esdhc_cqhci_ops;
1607
1608                 err = cqhci_init(cq_host, host->mmc, false);
1609                 if (err)
1610                         goto disable_ahb_clk;
1611         }
1612
1613         err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1614         if (err)
1615                 goto disable_ahb_clk;
1616
1617         sdhci_esdhc_imx_hwinit(host);
1618
1619         err = sdhci_add_host(host);
1620         if (err)
1621                 goto disable_ahb_clk;
1622
1623         /*
1624          * Setup the wakeup capability here, let user to decide
1625          * whether need to enable this wakeup through sysfs interface.
1626          */
1627         if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) &&
1628                         (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ))
1629                 device_set_wakeup_capable(&pdev->dev, true);
1630
1631         pm_runtime_set_active(&pdev->dev);
1632         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1633         pm_runtime_use_autosuspend(&pdev->dev);
1634         pm_suspend_ignore_children(&pdev->dev, 1);
1635         pm_runtime_enable(&pdev->dev);
1636
1637         return 0;
1638
1639 disable_ahb_clk:
1640         clk_disable_unprepare(imx_data->clk_ahb);
1641 disable_ipg_clk:
1642         clk_disable_unprepare(imx_data->clk_ipg);
1643 disable_per_clk:
1644         clk_disable_unprepare(imx_data->clk_per);
1645 free_sdhci:
1646         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1647                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1648         sdhci_pltfm_free(pdev);
1649         return err;
1650 }
1651
1652 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1653 {
1654         struct sdhci_host *host = platform_get_drvdata(pdev);
1655         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1656         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1657         int dead;
1658
1659         pm_runtime_get_sync(&pdev->dev);
1660         dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1661         pm_runtime_disable(&pdev->dev);
1662         pm_runtime_put_noidle(&pdev->dev);
1663
1664         sdhci_remove_host(host, dead);
1665
1666         clk_disable_unprepare(imx_data->clk_per);
1667         clk_disable_unprepare(imx_data->clk_ipg);
1668         clk_disable_unprepare(imx_data->clk_ahb);
1669
1670         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1671                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1672
1673         sdhci_pltfm_free(pdev);
1674
1675         return 0;
1676 }
1677
1678 #ifdef CONFIG_PM_SLEEP
1679 static int sdhci_esdhc_suspend(struct device *dev)
1680 {
1681         struct sdhci_host *host = dev_get_drvdata(dev);
1682         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1683         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1684         int ret;
1685
1686         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1687                 ret = cqhci_suspend(host->mmc);
1688                 if (ret)
1689                         return ret;
1690         }
1691
1692         if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1693                 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1694                 mmc_retune_timer_stop(host->mmc);
1695                 mmc_retune_needed(host->mmc);
1696         }
1697
1698         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1699                 mmc_retune_needed(host->mmc);
1700
1701         ret = sdhci_suspend_host(host);
1702         if (ret)
1703                 return ret;
1704
1705         ret = pinctrl_pm_select_sleep_state(dev);
1706         if (ret)
1707                 return ret;
1708
1709         ret = mmc_gpio_set_cd_wake(host->mmc, true);
1710
1711         return ret;
1712 }
1713
1714 static int sdhci_esdhc_resume(struct device *dev)
1715 {
1716         struct sdhci_host *host = dev_get_drvdata(dev);
1717         int ret;
1718
1719         ret = pinctrl_pm_select_default_state(dev);
1720         if (ret)
1721                 return ret;
1722
1723         /* re-initialize hw state in case it's lost in low power mode */
1724         sdhci_esdhc_imx_hwinit(host);
1725
1726         ret = sdhci_resume_host(host);
1727         if (ret)
1728                 return ret;
1729
1730         if (host->mmc->caps2 & MMC_CAP2_CQE)
1731                 ret = cqhci_resume(host->mmc);
1732
1733         if (!ret)
1734                 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1735
1736         return ret;
1737 }
1738 #endif
1739
1740 #ifdef CONFIG_PM
1741 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1742 {
1743         struct sdhci_host *host = dev_get_drvdata(dev);
1744         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1745         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1746         int ret;
1747
1748         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1749                 ret = cqhci_suspend(host->mmc);
1750                 if (ret)
1751                         return ret;
1752         }
1753
1754         ret = sdhci_runtime_suspend_host(host);
1755         if (ret)
1756                 return ret;
1757
1758         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1759                 mmc_retune_needed(host->mmc);
1760
1761         imx_data->actual_clock = host->mmc->actual_clock;
1762         esdhc_pltfm_set_clock(host, 0);
1763         clk_disable_unprepare(imx_data->clk_per);
1764         clk_disable_unprepare(imx_data->clk_ipg);
1765         clk_disable_unprepare(imx_data->clk_ahb);
1766
1767         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1768                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1769
1770         return ret;
1771 }
1772
1773 static int sdhci_esdhc_runtime_resume(struct device *dev)
1774 {
1775         struct sdhci_host *host = dev_get_drvdata(dev);
1776         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1777         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1778         int err;
1779
1780         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1781                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1782
1783         if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1784                 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1785
1786         err = clk_prepare_enable(imx_data->clk_ahb);
1787         if (err)
1788                 goto remove_pm_qos_request;
1789
1790         err = clk_prepare_enable(imx_data->clk_per);
1791         if (err)
1792                 goto disable_ahb_clk;
1793
1794         err = clk_prepare_enable(imx_data->clk_ipg);
1795         if (err)
1796                 goto disable_per_clk;
1797
1798         esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1799
1800         err = sdhci_runtime_resume_host(host, 0);
1801         if (err)
1802                 goto disable_ipg_clk;
1803
1804         if (host->mmc->caps2 & MMC_CAP2_CQE)
1805                 err = cqhci_resume(host->mmc);
1806
1807         return err;
1808
1809 disable_ipg_clk:
1810         clk_disable_unprepare(imx_data->clk_ipg);
1811 disable_per_clk:
1812         clk_disable_unprepare(imx_data->clk_per);
1813 disable_ahb_clk:
1814         clk_disable_unprepare(imx_data->clk_ahb);
1815 remove_pm_qos_request:
1816         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1817                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1818         return err;
1819 }
1820 #endif
1821
1822 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1823         SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1824         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1825                                 sdhci_esdhc_runtime_resume, NULL)
1826 };
1827
1828 static struct platform_driver sdhci_esdhc_imx_driver = {
1829         .driver         = {
1830                 .name   = "sdhci-esdhc-imx",
1831                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1832                 .of_match_table = imx_esdhc_dt_ids,
1833                 .pm     = &sdhci_esdhc_pmops,
1834         },
1835         .probe          = sdhci_esdhc_imx_probe,
1836         .remove         = sdhci_esdhc_imx_remove,
1837 };
1838
1839 module_platform_driver(sdhci_esdhc_imx_driver);
1840
1841 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1842 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1843 MODULE_LICENSE("GPL v2");