drivers/mmc/host/sdhci-acpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Secure Digital Host Controller Interface ACPI driver.
   4  *
   5  * Copyright (c) 2012, Intel Corporation.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/init.h>
  10 #include <linux/export.h>
  11 #include <linux/module.h>
  12 #include <linux/device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/ioport.h>
  15 #include <linux/io.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/compiler.h>
  18 #include <linux/stddef.h>
  19 #include <linux/bitops.h>
  20 #include <linux/types.h>
  21 #include <linux/err.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/acpi.h>
  24 #include <linux/pm.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/delay.h>
  27 #include <linux/dmi.h>
  28
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/pm.h>
  31 #include <linux/mmc/slot-gpio.h>
  32
  33 #ifdef CONFIG_X86
  34 #include <linux/platform_data/x86/soc.h>
  35 #include <asm/iosf_mbi.h>
  36 #endif
  37
  38 #include "sdhci.h"
  39
  40 enum {
  41         SDHCI_ACPI_SD_CD                = BIT(0),
  42         SDHCI_ACPI_RUNTIME_PM           = BIT(1),
  43         SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
  44 };
  45
  46 struct sdhci_acpi_chip {
  47         const struct    sdhci_ops *ops;
  48         unsigned int    quirks;
  49         unsigned int    quirks2;
  50         unsigned long   caps;
  51         unsigned int    caps2;
  52         mmc_pm_flag_t   pm_caps;
  53 };
  54
  55 struct sdhci_acpi_slot {
  56         const struct    sdhci_acpi_chip *chip;
  57         unsigned int    quirks;
  58         unsigned int    quirks2;
  59         unsigned long   caps;
  60         unsigned int    caps2;
  61         mmc_pm_flag_t   pm_caps;
  62         unsigned int    flags;
  63         size_t          priv_size;
  64         int (*probe_slot)(struct platform_device *, struct acpi_device *);
  65         int (*remove_slot)(struct platform_device *);
  66         int (*free_slot)(struct platform_device *pdev);
  67         int (*setup_host)(struct platform_device *pdev);
  68 };
  69
  70 struct sdhci_acpi_host {
  71         struct sdhci_host               *host;
  72         const struct sdhci_acpi_slot    *slot;
  73         struct platform_device          *pdev;
  74         bool                            use_runtime_pm;
  75         bool                            is_intel;
  76         bool                            reset_signal_volt_on_suspend;
  77         unsigned long                   private[] ____cacheline_aligned;
  78 };
  79
  80 enum {
  81         DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP                  = BIT(0),
  82         DMI_QUIRK_SD_NO_WRITE_PROTECT                           = BIT(1),
  83 };
  84
  85 static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
  86 {
  87         return (void *)c->private;
  88 }
  89
  90 static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
  91 {
  92         return c->slot && (c->slot->flags & flag);
  93 }
  94
  95 #define INTEL_DSM_HS_CAPS_SDR25         BIT(0)
  96 #define INTEL_DSM_HS_CAPS_DDR50         BIT(1)
  97 #define INTEL_DSM_HS_CAPS_SDR50         BIT(2)
  98 #define INTEL_DSM_HS_CAPS_SDR104        BIT(3)
  99
 100 enum {
 101         INTEL_DSM_FNS           =  0,
 102         INTEL_DSM_V18_SWITCH    =  3,
 103         INTEL_DSM_V33_SWITCH    =  4,
 104         INTEL_DSM_HS_CAPS       =  8,
 105 };
 106
 107 struct intel_host {
 108         u32     dsm_fns;
 109         u32     hs_caps;
 110 };
 111
 112 static const guid_t intel_dsm_guid =
 113         GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
 114                   0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
 115
 116 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
 117                        unsigned int fn, u32 *result)
 118 {
 119         union acpi_object *obj;
 120         int err = 0;
 121
 122         obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
 123         if (!obj)
 124                 return -EOPNOTSUPP;
 125
 126         if (obj->type == ACPI_TYPE_INTEGER) {
 127                 *result = obj->integer.value;
 128         } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
 129                 size_t len = min_t(size_t, obj->buffer.length, 4);
 130
 131                 *result = 0;
 132                 memcpy(result, obj->buffer.pointer, len);
 133         } else {
 134                 dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
 135                         __func__, fn, obj->type, obj->buffer.length);
 136                 err = -EINVAL;
 137         }
 138
 139         ACPI_FREE(obj);
 140
 141         return err;
 142 }
 143
 144 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
 145                      unsigned int fn, u32 *result)
 146 {
 147         if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
 148                 return -EOPNOTSUPP;
 149
 150         return __intel_dsm(intel_host, dev, fn, result);
 151 }
 152
 153 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
 154                            struct mmc_host *mmc)
 155 {
 156         int err;
 157
 158         intel_host->hs_caps = ~0;
 159
 160         err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
 161         if (err) {
 162                 pr_debug("%s: DSM not supported, error %d\n",
 163                          mmc_hostname(mmc), err);
 164                 return;
 165         }
 166
 167         pr_debug("%s: DSM function mask %#x\n",
 168                  mmc_hostname(mmc), intel_host->dsm_fns);
 169
 170         intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
 171 }
 172
 173 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
 174                                              struct mmc_ios *ios)
 175 {
 176         struct device *dev = mmc_dev(mmc);
 177         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
 178         struct intel_host *intel_host = sdhci_acpi_priv(c);
 179         unsigned int fn;
 180         u32 result = 0;
 181         int err;
 182
 183         err = sdhci_start_signal_voltage_switch(mmc, ios);
 184         if (err)
 185                 return err;
 186
 187         switch (ios->signal_voltage) {
 188         case MMC_SIGNAL_VOLTAGE_330:
 189                 fn = INTEL_DSM_V33_SWITCH;
 190                 break;
 191         case MMC_SIGNAL_VOLTAGE_180:
 192                 fn = INTEL_DSM_V18_SWITCH;
 193                 break;
 194         default:
 195                 return 0;
 196         }
 197
 198         err = intel_dsm(intel_host, dev, fn, &result);
 199         pr_debug("%s: %s DSM fn %u error %d result %u\n",
 200                  mmc_hostname(mmc), __func__, fn, err, result);
 201
 202         return 0;
 203 }
 204
 205 static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
 206 {
 207         u8 reg;
 208
 209         reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
 210         reg |= 0x10;
 211         sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
 212         /* For eMMC, minimum is 1us but give it 9us for good measure */
 213         udelay(9);
 214         reg &= ~0x10;
 215         sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
 216         /* For eMMC, minimum is 200us but give it 300us for good measure */
 217         usleep_range(300, 1000);
 218 }
 219
 220 static const struct sdhci_ops sdhci_acpi_ops_dflt = {
 221         .set_clock = sdhci_set_clock,
 222         .set_bus_width = sdhci_set_bus_width,
 223         .reset = sdhci_reset,
 224         .set_uhs_signaling = sdhci_set_uhs_signaling,
 225 };
 226
 227 static const struct sdhci_ops sdhci_acpi_ops_int = {
 228         .set_clock = sdhci_set_clock,
 229         .set_bus_width = sdhci_set_bus_width,
 230         .reset = sdhci_reset,
 231         .set_uhs_signaling = sdhci_set_uhs_signaling,
 232         .hw_reset   = sdhci_acpi_int_hw_reset,
 233 };
 234
 235 static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
 236         .ops = &sdhci_acpi_ops_int,
 237 };
 238
 239 #ifdef CONFIG_X86
 240
 241 #define BYT_IOSF_SCCEP                  0x63
 242 #define BYT_IOSF_OCP_NETCTRL0           0x1078
 243 #define BYT_IOSF_OCP_TIMEOUT_BASE       GENMASK(10, 8)
 244
 245 static void sdhci_acpi_byt_setting(struct device *dev)
 246 {
 247         u32 val = 0;
 248
 249         if (!soc_intel_is_byt())
 250                 return;
 251
 252         if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
 253                           &val)) {
 254                 dev_err(dev, "%s read error\n", __func__);
 255                 return;
 256         }
 257
 258         if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
 259                 return;
 260
 261         val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
 262
 263         if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
 264                            val)) {
 265                 dev_err(dev, "%s write error\n", __func__);
 266                 return;
 267         }
 268
 269         dev_dbg(dev, "%s completed\n", __func__);
 270 }
 271
 272 static bool sdhci_acpi_byt_defer(struct device *dev)
 273 {
 274         if (!soc_intel_is_byt())
 275                 return false;
 276
 277         if (!iosf_mbi_available())
 278                 return true;
 279
 280         sdhci_acpi_byt_setting(dev);
 281
 282         return false;
 283 }
 284
 285 #else
 286
 287 static inline void sdhci_acpi_byt_setting(struct device *dev)
 288 {
 289 }
 290
 291 static inline bool sdhci_acpi_byt_defer(struct device *dev)
 292 {
 293         return false;
 294 }
 295
 296 #endif
 297
 298 static int bxt_get_cd(struct mmc_host *mmc)
 299 {
 300         int gpio_cd = mmc_gpio_get_cd(mmc);
 301
 302         if (!gpio_cd)
 303                 return 0;
 304
 305         return sdhci_get_cd_nogpio(mmc);
 306 }
 307
 308 static int intel_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
 309 {
 310         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 311         struct intel_host *intel_host = sdhci_acpi_priv(c);
 312         struct sdhci_host *host = c->host;
 313
 314         if (acpi_dev_hid_uid_match(adev, "80860F14", "1") &&
 315             sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
 316             sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
 317                 host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
 318
 319         if (acpi_dev_hid_uid_match(adev, "80865ACA", NULL))
 320                 host->mmc_host_ops.get_cd = bxt_get_cd;
 321
 322         intel_dsm_init(intel_host, &pdev->dev, host->mmc);
 323
 324         host->mmc_host_ops.start_signal_voltage_switch =
 325                                         intel_start_signal_voltage_switch;
 326
 327         c->is_intel = true;
 328
 329         return 0;
 330 }
 331
 332 static int intel_setup_host(struct platform_device *pdev)
 333 {
 334         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 335         struct intel_host *intel_host = sdhci_acpi_priv(c);
 336
 337         if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
 338                 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
 339
 340         if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
 341                 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
 342
 343         if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
 344                 c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
 345
 346         if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
 347                 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
 348
 349         return 0;
 350 }
 351
 352 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
 353         .chip    = &sdhci_acpi_chip_int,
 354         .caps    = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
 355                    MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
 356                    MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
 357         .flags   = SDHCI_ACPI_RUNTIME_PM,
 358         .quirks  = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
 359                    SDHCI_QUIRK_NO_LED,
 360         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 361                    SDHCI_QUIRK2_STOP_WITH_TC |
 362                    SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
 363         .probe_slot     = intel_probe_slot,
 364         .setup_host     = intel_setup_host,
 365         .priv_size      = sizeof(struct intel_host),
 366 };
 367
 368 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
 369         .quirks  = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 370                    SDHCI_QUIRK_NO_LED |
 371                    SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 372         .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
 373         .caps    = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
 374                    MMC_CAP_WAIT_WHILE_BUSY,
 375         .flags   = SDHCI_ACPI_RUNTIME_PM,
 376         .pm_caps = MMC_PM_KEEP_POWER,
 377         .probe_slot     = intel_probe_slot,
 378         .setup_host     = intel_setup_host,
 379         .priv_size      = sizeof(struct intel_host),
 380 };
 381
 382 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
 383         .flags   = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
 384                    SDHCI_ACPI_RUNTIME_PM,
 385         .quirks  = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
 386                    SDHCI_QUIRK_NO_LED,
 387         .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
 388                    SDHCI_QUIRK2_STOP_WITH_TC,
 389         .caps    = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
 390         .probe_slot     = intel_probe_slot,
 391         .setup_host     = intel_setup_host,
 392         .priv_size      = sizeof(struct intel_host),
 393 };
 394
 395 #define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG        0x1a8
 396 #define VENDOR_SPECIFIC_PWRCTL_CTL_REG          0x1ac
 397 static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr)
 398 {
 399         struct sdhci_host *host = ptr;
 400
 401         sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG);
 402         sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG);
 403
 404         return IRQ_HANDLED;
 405 }
 406
 407 static int qcom_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
 408 {
 409         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 410         struct sdhci_host *host = c->host;
 411         int *irq = sdhci_acpi_priv(c);
 412
 413         *irq = -EINVAL;
 414
 415         if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
 416                 return 0;
 417
 418         *irq = platform_get_irq(pdev, 1);
 419         if (*irq < 0)
 420                 return 0;
 421
 422         return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler,
 423                                     IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
 424                                     "sdhci_qcom", host);
 425 }
 426
 427 static int qcom_free_slot(struct platform_device *pdev)
 428 {
 429         struct device *dev = &pdev->dev;
 430         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 431         struct sdhci_host *host = c->host;
 432         struct acpi_device *adev;
 433         int *irq = sdhci_acpi_priv(c);
 434
 435         adev = ACPI_COMPANION(dev);
 436         if (!adev)
 437                 return -ENODEV;
 438
 439         if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
 440                 return 0;
 441
 442         if (*irq < 0)
 443                 return 0;
 444
 445         free_irq(*irq, host);
 446         return 0;
 447 }
 448
 449 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
 450         .quirks  = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 451         .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
 452         .caps    = MMC_CAP_NONREMOVABLE,
 453         .priv_size      = sizeof(int),
 454         .probe_slot     = qcom_probe_slot,
 455         .free_slot      = qcom_free_slot,
 456 };
 457
 458 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
 459         .quirks  = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 460         .caps    = MMC_CAP_NONREMOVABLE,
 461 };
 462
 463 struct amd_sdhci_host {
 464         bool    tuned_clock;
 465         bool    dll_enabled;
 466 };
 467
 468 /* AMD sdhci reset dll register. */
 469 #define SDHCI_AMD_RESET_DLL_REGISTER    0x908
 470
 471 static int amd_select_drive_strength(struct mmc_card *card,
 472                                      unsigned int max_dtr, int host_drv,
 473                                      int card_drv, int *host_driver_strength)
 474 {
 475         struct sdhci_host *host = mmc_priv(card->host);
 476         u16 preset, preset_driver_strength;
 477
 478         /*
 479          * This method is only called by mmc_select_hs200 so we only need to
 480          * read from the HS200 (SDR104) preset register.
 481          *
 482          * Firmware that has "invalid/default" presets return a driver strength
 483          * of A. This matches the previously hard coded value.
 484          */
 485         preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
 486         preset_driver_strength = FIELD_GET(SDHCI_PRESET_DRV_MASK, preset);
 487
 488         /*
 489          * We want the controller driver strength to match the card's driver
 490          * strength so they have similar rise/fall times.
 491          *
 492          * The controller driver strength set by this method is sticky for all
 493          * timings after this method is called. This unfortunately means that
 494          * while HS400 tuning is in progress we end up with mismatched driver
 495          * strengths between the controller and the card. HS400 tuning requires
 496          * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch
 497          * happens while in DDR52 and HS modes. This has not been observed to
 498          * cause problems. Enabling presets would fix this issue.
 499          */
 500         *host_driver_strength = preset_driver_strength;
 501
 502         /*
 503          * The resulting card driver strength is only set when switching the
 504          * card's timing to HS200 or HS400. The card will use the default driver
 505          * strength (B) for any other mode.
 506          */
 507         return preset_driver_strength;
 508 }
 509
 510 static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable)
 511 {
 512         struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
 513         struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
 514
 515         /* AMD Platform requires dll setting */
 516         sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
 517         usleep_range(10, 20);
 518         if (enable)
 519                 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
 520
 521         amd_host->dll_enabled = enable;
 522 }
 523
 524 /*
 525  * The initialization sequence for HS400 is:
 526  *     HS->HS200->Perform Tuning->HS->HS400
 527  *
 528  * The re-tuning sequence is:
 529  *     HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
 530  *
 531  * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
 532  * mode. If we switch to a different mode, we need to disable the tuned clock.
 533  * If we have previously performed tuning and switch back to HS200 or
 534  * HS400, we can re-enable the tuned clock.
 535  *
 536  */
 537 static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 538 {
 539         struct sdhci_host *host = mmc_priv(mmc);
 540         struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
 541         struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
 542         unsigned int old_timing = host->timing;
 543         u16 val;
 544
 545         sdhci_set_ios(mmc, ios);
 546
 547         if (old_timing != host->timing && amd_host->tuned_clock) {
 548                 if (host->timing == MMC_TIMING_MMC_HS400 ||
 549                     host->timing == MMC_TIMING_MMC_HS200) {
 550                         val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 551                         val |= SDHCI_CTRL_TUNED_CLK;
 552                         sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
 553                 } else {
 554                         val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 555                         val &= ~SDHCI_CTRL_TUNED_CLK;
 556                         sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
 557                 }
 558
 559                 /* DLL is only required for HS400 */
 560                 if (host->timing == MMC_TIMING_MMC_HS400 &&
 561                     !amd_host->dll_enabled)
 562                         sdhci_acpi_amd_hs400_dll(host, true);
 563         }
 564 }
 565
 566 static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 567 {
 568         int err;
 569         struct sdhci_host *host = mmc_priv(mmc);
 570         struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
 571         struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
 572
 573         amd_host->tuned_clock = false;
 574
 575         err = sdhci_execute_tuning(mmc, opcode);
 576
 577         if (!err && !host->tuning_err)
 578                 amd_host->tuned_clock = true;
 579
 580         return err;
 581 }
 582
 583 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
 584 {
 585         struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
 586         struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
 587
 588         if (mask & SDHCI_RESET_ALL) {
 589                 amd_host->tuned_clock = false;
 590                 sdhci_acpi_amd_hs400_dll(host, false);
 591         }
 592
 593         sdhci_reset(host, mask);
 594 }
 595
 596 static const struct sdhci_ops sdhci_acpi_ops_amd = {
 597         .set_clock      = sdhci_set_clock,
 598         .set_bus_width  = sdhci_set_bus_width,
 599         .reset          = amd_sdhci_reset,
 600         .set_uhs_signaling = sdhci_set_uhs_signaling,
 601 };
 602
 603 static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
 604         .ops = &sdhci_acpi_ops_amd,
 605 };
 606
 607 static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
 608                                           struct acpi_device *adev)
 609 {
 610         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 611         struct sdhci_host *host   = c->host;
 612
 613         sdhci_read_caps(host);
 614         if (host->caps1 & SDHCI_SUPPORT_DDR50)
 615                 host->mmc->caps = MMC_CAP_1_8V_DDR;
 616
 617         if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
 618             (host->mmc->caps & MMC_CAP_1_8V_DDR))
 619                 host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
 620
 621         /*
 622          * There are two types of presets out in the wild:
 623          * 1) Default/broken presets.
 624          *    These presets have two sets of problems:
 625          *    a) The clock divisor for SDR12, SDR25, and SDR50 is too small.
 626          *       This results in clock frequencies that are 2x higher than
 627          *       acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 =
 628          *       100 MHz.x
 629          *    b) The HS200 and HS400 driver strengths don't match.
 630          *       By default, the SDR104 preset register has a driver strength of
 631          *       A, but the (internal) HS400 preset register has a driver
 632          *       strength of B. As part of initializing HS400, HS200 tuning
 633          *       needs to be performed. Having different driver strengths
 634          *       between tuning and operation is wrong. It results in different
 635          *       rise/fall times that lead to incorrect sampling.
 636          * 2) Firmware with properly initialized presets.
 637          *    These presets have proper clock divisors. i.e., SDR12 => 12MHz,
 638          *    SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and
 639          *    HS400 preset driver strengths match.
 640          *
 641          *    Enabling presets for HS400 doesn't work for the following reasons:
 642          *    1) sdhci_set_ios has a hard coded list of timings that are used
 643          *       to determine if presets should be enabled.
 644          *    2) sdhci_get_preset_value is using a non-standard register to
 645          *       read out HS400 presets. The AMD controller doesn't support this
 646          *       non-standard register. In fact, it doesn't expose the HS400
 647          *       preset register anywhere in the SDHCI memory map. This results
 648          *       in reading a garbage value and using the wrong presets.
 649          *
 650          *       Since HS400 and HS200 presets must be identical, we could
 651          *       instead use the the SDR104 preset register.
 652          *
 653          *    If the above issues are resolved we could remove this quirk for
 654          *    firmware that that has valid presets (i.e., SDR12 <= 12 MHz).
 655          */
 656         host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 657
 658         host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
 659         host->mmc_host_ops.set_ios = amd_set_ios;
 660         host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
 661         return 0;
 662 }
 663
 664 static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
 665         .chip           = &sdhci_acpi_chip_amd,
 666         .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
 667         .quirks         = SDHCI_QUIRK_32BIT_DMA_ADDR |
 668                           SDHCI_QUIRK_32BIT_DMA_SIZE |
 669                           SDHCI_QUIRK_32BIT_ADMA_SIZE,
 670         .quirks2        = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
 671         .probe_slot     = sdhci_acpi_emmc_amd_probe_slot,
 672         .priv_size      = sizeof(struct amd_sdhci_host),
 673 };
 674
 675 struct sdhci_acpi_uid_slot {
 676         const char *hid;
 677         const char *uid;
 678         const struct sdhci_acpi_slot *slot;
 679 };
 680
 681 static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
 682         { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
 683         { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
 684         { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
 685         { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
 686         { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
 687         { "80860F14" , "3" , &sdhci_acpi_slot_int_sd   },
 688         { "80860F16" , NULL, &sdhci_acpi_slot_int_sd   },
 689         { "INT33BB"  , "2" , &sdhci_acpi_slot_int_sdio },
 690         { "INT33BB"  , "3" , &sdhci_acpi_slot_int_sd },
 691         { "INT33C6"  , NULL, &sdhci_acpi_slot_int_sdio },
 692         { "INT3436"  , NULL, &sdhci_acpi_slot_int_sdio },
 693         { "INT344D"  , NULL, &sdhci_acpi_slot_int_sdio },
 694         { "PNP0FFF"  , "3" , &sdhci_acpi_slot_int_sd   },
 695         { "PNP0D40"  },
 696         { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
 697         { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
 698         { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
 699         { "AMDI0041", NULL, &sdhci_acpi_slot_amd_emmc },
 700         { },
 701 };
 702
 703 static const struct acpi_device_id sdhci_acpi_ids[] = {
 704         { "80865ACA" },
 705         { "80865ACC" },
 706         { "80865AD0" },
 707         { "80860F14" },
 708         { "80860F16" },
 709         { "INT33BB"  },
 710         { "INT33C6"  },
 711         { "INT3436"  },
 712         { "INT344D"  },
 713         { "PNP0D40"  },
 714         { "QCOM8051" },
 715         { "QCOM8052" },
 716         { "AMDI0040" },
 717         { "AMDI0041" },
 718         { },
 719 };
 720 MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
 721
 722 static const struct dmi_system_id sdhci_acpi_quirks[] = {
 723         {
 724                 /*
 725                  * The Lenovo Miix 320-10ICR has a bug in the _PS0 method of
 726                  * the SHC1 ACPI device, this bug causes it to reprogram the
 727                  * wrong LDO (DLDO3) to 1.8V if 1.8V modes are used and the
 728                  * card is (runtime) suspended + resumed. DLDO3 is used for
 729                  * the LCD and setting it to 1.8V causes the LCD to go black.
 730                  */
 731                 .matches = {
 732                         DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
 733                         DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
 734                 },
 735                 .driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP,
 736         },
 737         {
 738                 /*
 739                  * The Acer Aspire Switch 10 (SW5-012) microSD slot always
 740                  * reports the card being write-protected even though microSD
 741                  * cards do not have a write-protect switch at all.
 742                  */
 743                 .matches = {
 744                         DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
 745                         DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
 746                 },
 747                 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
 748         },
 749         {
 750                 /*
 751                  * The Toshiba WT8-B's microSD slot always reports the card being
 752                  * write-protected.
 753                  */
 754                 .matches = {
 755                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 756                         DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA ENCORE 2 WT8-B"),
 757                 },
 758                 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
 759         },
 760         {} /* Terminating entry */
 761 };
 762
 763 static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(struct acpi_device *adev)
 764 {
 765         const struct sdhci_acpi_uid_slot *u;
 766
 767         for (u = sdhci_acpi_uids; u->hid; u++) {
 768                 if (acpi_dev_hid_uid_match(adev, u->hid, u->uid))
 769                         return u->slot;
 770         }
 771         return NULL;
 772 }
 773
 774 static int sdhci_acpi_probe(struct platform_device *pdev)
 775 {
 776         struct device *dev = &pdev->dev;
 777         const struct sdhci_acpi_slot *slot;
 778         struct acpi_device *device, *child;
 779         const struct dmi_system_id *id;
 780         struct sdhci_acpi_host *c;
 781         struct sdhci_host *host;
 782         struct resource *iomem;
 783         resource_size_t len;
 784         size_t priv_size;
 785         int quirks = 0;
 786         int err;
 787
 788         device = ACPI_COMPANION(dev);
 789         if (!device)
 790                 return -ENODEV;
 791
 792         id = dmi_first_match(sdhci_acpi_quirks);
 793         if (id)
 794                 quirks = (long)id->driver_data;
 795
 796         slot = sdhci_acpi_get_slot(device);
 797
 798         /* Power on the SDHCI controller and its children */
 799         acpi_device_fix_up_power(device);
 800         list_for_each_entry(child, &device->children, node)
 801                 if (child->status.present && child->status.enabled)
 802                         acpi_device_fix_up_power(child);
 803
 804         if (sdhci_acpi_byt_defer(dev))
 805                 return -EPROBE_DEFER;
 806
 807         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 808         if (!iomem)
 809                 return -ENOMEM;
 810
 811         len = resource_size(iomem);
 812         if (len < 0x100)
 813                 dev_err(dev, "Invalid iomem size!\n");
 814
 815         if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
 816                 return -ENOMEM;
 817
 818         priv_size = slot ? slot->priv_size : 0;
 819         host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
 820         if (IS_ERR(host))
 821                 return PTR_ERR(host);
 822
 823         c = sdhci_priv(host);
 824         c->host = host;
 825         c->slot = slot;
 826         c->pdev = pdev;
 827         c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
 828
 829         platform_set_drvdata(pdev, c);
 830
 831         host->hw_name   = "ACPI";
 832         host->ops       = &sdhci_acpi_ops_dflt;
 833         host->irq       = platform_get_irq(pdev, 0);
 834         if (host->irq < 0) {
 835                 err = -EINVAL;
 836                 goto err_free;
 837         }
 838
 839         host->ioaddr = devm_ioremap(dev, iomem->start,
 840                                             resource_size(iomem));
 841         if (host->ioaddr == NULL) {
 842                 err = -ENOMEM;
 843                 goto err_free;
 844         }
 845
 846         if (c->slot) {
 847                 if (c->slot->probe_slot) {
 848                         err = c->slot->probe_slot(pdev, device);
 849                         if (err)
 850                                 goto err_free;
 851                 }
 852                 if (c->slot->chip) {
 853                         host->ops            = c->slot->chip->ops;
 854                         host->quirks        |= c->slot->chip->quirks;
 855                         host->quirks2       |= c->slot->chip->quirks2;
 856                         host->mmc->caps     |= c->slot->chip->caps;
 857                         host->mmc->caps2    |= c->slot->chip->caps2;
 858                         host->mmc->pm_caps  |= c->slot->chip->pm_caps;
 859                 }
 860                 host->quirks        |= c->slot->quirks;
 861                 host->quirks2       |= c->slot->quirks2;
 862                 host->mmc->caps     |= c->slot->caps;
 863                 host->mmc->caps2    |= c->slot->caps2;
 864                 host->mmc->pm_caps  |= c->slot->pm_caps;
 865         }
 866
 867         host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
 868
 869         if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
 870                 bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
 871
 872                 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
 873                 if (err) {
 874                         if (err == -EPROBE_DEFER)
 875                                 goto err_free;
 876                         dev_warn(dev, "failed to setup card detect gpio\n");
 877                         c->use_runtime_pm = false;
 878                 }
 879
 880                 if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)
 881                         c->reset_signal_volt_on_suspend = true;
 882
 883                 if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT)
 884                         host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
 885         }
 886
 887         err = sdhci_setup_host(host);
 888         if (err)
 889                 goto err_free;
 890
 891         if (c->slot && c->slot->setup_host) {
 892                 err = c->slot->setup_host(pdev);
 893                 if (err)
 894                         goto err_cleanup;
 895         }
 896
 897         err = __sdhci_add_host(host);
 898         if (err)
 899                 goto err_cleanup;
 900
 901         if (c->use_runtime_pm) {
 902                 pm_runtime_set_active(dev);
 903                 pm_suspend_ignore_children(dev, 1);
 904                 pm_runtime_set_autosuspend_delay(dev, 50);
 905                 pm_runtime_use_autosuspend(dev);
 906                 pm_runtime_enable(dev);
 907         }
 908
 909         device_enable_async_suspend(dev);
 910
 911         return 0;
 912
 913 err_cleanup:
 914         sdhci_cleanup_host(c->host);
 915 err_free:
 916         if (c->slot && c->slot->free_slot)
 917                 c->slot->free_slot(pdev);
 918
 919         sdhci_free_host(c->host);
 920         return err;
 921 }
 922
 923 static int sdhci_acpi_remove(struct platform_device *pdev)
 924 {
 925         struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
 926         struct device *dev = &pdev->dev;
 927         int dead;
 928
 929         if (c->use_runtime_pm) {
 930                 pm_runtime_get_sync(dev);
 931                 pm_runtime_disable(dev);
 932                 pm_runtime_put_noidle(dev);
 933         }
 934
 935         if (c->slot && c->slot->remove_slot)
 936                 c->slot->remove_slot(pdev);
 937
 938         dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
 939         sdhci_remove_host(c->host, dead);
 940
 941         if (c->slot && c->slot->free_slot)
 942                 c->slot->free_slot(pdev);
 943
 944         sdhci_free_host(c->host);
 945
 946         return 0;
 947 }
 948
 949 static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed(
 950         struct device *dev)
 951 {
 952         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
 953         struct sdhci_host *host = c->host;
 954
 955         if (c->is_intel && c->reset_signal_volt_on_suspend &&
 956             host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
 957                 struct intel_host *intel_host = sdhci_acpi_priv(c);
 958                 unsigned int fn = INTEL_DSM_V33_SWITCH;
 959                 u32 result = 0;
 960
 961                 intel_dsm(intel_host, dev, fn, &result);
 962         }
 963 }
 964
 965 #ifdef CONFIG_PM_SLEEP
 966
 967 static int sdhci_acpi_suspend(struct device *dev)
 968 {
 969         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
 970         struct sdhci_host *host = c->host;
 971         int ret;
 972
 973         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 974                 mmc_retune_needed(host->mmc);
 975
 976         ret = sdhci_suspend_host(host);
 977         if (ret)
 978                 return ret;
 979
 980         sdhci_acpi_reset_signal_voltage_if_needed(dev);
 981         return 0;
 982 }
 983
 984 static int sdhci_acpi_resume(struct device *dev)
 985 {
 986         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
 987
 988         sdhci_acpi_byt_setting(&c->pdev->dev);
 989
 990         return sdhci_resume_host(c->host);
 991 }
 992
 993 #endif
 994
 995 #ifdef CONFIG_PM
 996
 997 static int sdhci_acpi_runtime_suspend(struct device *dev)
 998 {
 999         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1000         struct sdhci_host *host = c->host;
1001         int ret;
1002
1003         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1004                 mmc_retune_needed(host->mmc);
1005
1006         ret = sdhci_runtime_suspend_host(host);
1007         if (ret)
1008                 return ret;
1009
1010         sdhci_acpi_reset_signal_voltage_if_needed(dev);
1011         return 0;
1012 }
1013
1014 static int sdhci_acpi_runtime_resume(struct device *dev)
1015 {
1016         struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1017
1018         sdhci_acpi_byt_setting(&c->pdev->dev);
1019
1020         return sdhci_runtime_resume_host(c->host, 0);
1021 }
1022
1023 #endif
1024
1025 static const struct dev_pm_ops sdhci_acpi_pm_ops = {
1026         SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
1027         SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
1028                         sdhci_acpi_runtime_resume, NULL)
1029 };
1030
1031 static struct platform_driver sdhci_acpi_driver = {
1032         .driver = {
1033                 .name                   = "sdhci-acpi",
1034                 .probe_type             = PROBE_PREFER_ASYNCHRONOUS,
1035                 .acpi_match_table       = sdhci_acpi_ids,
1036                 .pm                     = &sdhci_acpi_pm_ops,
1037         },
1038         .probe  = sdhci_acpi_probe,
1039         .remove = sdhci_acpi_remove,
1040 };
1041
1042 module_platform_driver(sdhci_acpi_driver);
1043
1044 MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
1045 MODULE_AUTHOR("Adrian Hunter");
1046 MODULE_LICENSE("GPL v2");