drivers/mmc/host/s3cmci.c

   1 /*
   2  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   3  *
   4  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   5  *
   6  * Current driver maintained by Ben Dooks and Simtec Electronics
   7  *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/clk.h>
  18 #include <linux/mmc/host.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/cpufreq.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/gpio.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/io.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/mmc/slot-gpio.h>
  30
  31 #include <plat/gpio-cfg.h>
  32 #include <mach/dma.h>
  33 #include <mach/gpio-samsung.h>
  34
  35 #include <linux/platform_data/mmc-s3cmci.h>
  36
  37 #include "s3cmci.h"
  38
  39 #define DRIVER_NAME "s3c-mci"
  40
  41 #define S3C2410_SDICON                  (0x00)
  42 #define S3C2410_SDIPRE                  (0x04)
  43 #define S3C2410_SDICMDARG               (0x08)
  44 #define S3C2410_SDICMDCON               (0x0C)
  45 #define S3C2410_SDICMDSTAT              (0x10)
  46 #define S3C2410_SDIRSP0                 (0x14)
  47 #define S3C2410_SDIRSP1                 (0x18)
  48 #define S3C2410_SDIRSP2                 (0x1C)
  49 #define S3C2410_SDIRSP3                 (0x20)
  50 #define S3C2410_SDITIMER                (0x24)
  51 #define S3C2410_SDIBSIZE                (0x28)
  52 #define S3C2410_SDIDCON                 (0x2C)
  53 #define S3C2410_SDIDCNT                 (0x30)
  54 #define S3C2410_SDIDSTA                 (0x34)
  55 #define S3C2410_SDIFSTA                 (0x38)
  56
  57 #define S3C2410_SDIDATA                 (0x3C)
  58 #define S3C2410_SDIIMSK                 (0x40)
  59
  60 #define S3C2440_SDIDATA                 (0x40)
  61 #define S3C2440_SDIIMSK                 (0x3C)
  62
  63 #define S3C2440_SDICON_SDRESET          (1 << 8)
  64 #define S3C2410_SDICON_SDIOIRQ          (1 << 3)
  65 #define S3C2410_SDICON_FIFORESET        (1 << 1)
  66 #define S3C2410_SDICON_CLOCKTYPE        (1 << 0)
  67
  68 #define S3C2410_SDICMDCON_LONGRSP       (1 << 10)
  69 #define S3C2410_SDICMDCON_WAITRSP       (1 << 9)
  70 #define S3C2410_SDICMDCON_CMDSTART      (1 << 8)
  71 #define S3C2410_SDICMDCON_SENDERHOST    (1 << 6)
  72 #define S3C2410_SDICMDCON_INDEX         (0x3f)
  73
  74 #define S3C2410_SDICMDSTAT_CRCFAIL      (1 << 12)
  75 #define S3C2410_SDICMDSTAT_CMDSENT      (1 << 11)
  76 #define S3C2410_SDICMDSTAT_CMDTIMEOUT   (1 << 10)
  77 #define S3C2410_SDICMDSTAT_RSPFIN       (1 << 9)
  78
  79 #define S3C2440_SDIDCON_DS_WORD         (2 << 22)
  80 #define S3C2410_SDIDCON_TXAFTERRESP     (1 << 20)
  81 #define S3C2410_SDIDCON_RXAFTERCMD      (1 << 19)
  82 #define S3C2410_SDIDCON_BLOCKMODE       (1 << 17)
  83 #define S3C2410_SDIDCON_WIDEBUS         (1 << 16)
  84 #define S3C2410_SDIDCON_DMAEN           (1 << 15)
  85 #define S3C2410_SDIDCON_STOP            (1 << 14)
  86 #define S3C2440_SDIDCON_DATSTART        (1 << 14)
  87
  88 #define S3C2410_SDIDCON_XFER_RXSTART    (2 << 12)
  89 #define S3C2410_SDIDCON_XFER_TXSTART    (3 << 12)
  90
  91 #define S3C2410_SDIDCON_BLKNUM_MASK     (0xFFF)
  92
  93 #define S3C2410_SDIDSTA_SDIOIRQDETECT   (1 << 9)
  94 #define S3C2410_SDIDSTA_FIFOFAIL        (1 << 8)
  95 #define S3C2410_SDIDSTA_CRCFAIL         (1 << 7)
  96 #define S3C2410_SDIDSTA_RXCRCFAIL       (1 << 6)
  97 #define S3C2410_SDIDSTA_DATATIMEOUT     (1 << 5)
  98 #define S3C2410_SDIDSTA_XFERFINISH      (1 << 4)
  99 #define S3C2410_SDIDSTA_TXDATAON        (1 << 1)
 100 #define S3C2410_SDIDSTA_RXDATAON        (1 << 0)
 101
 102 #define S3C2440_SDIFSTA_FIFORESET       (1 << 16)
 103 #define S3C2440_SDIFSTA_FIFOFAIL        (3 << 14)
 104 #define S3C2410_SDIFSTA_TFDET           (1 << 13)
 105 #define S3C2410_SDIFSTA_RFDET           (1 << 12)
 106 #define S3C2410_SDIFSTA_COUNTMASK       (0x7f)
 107
 108 #define S3C2410_SDIIMSK_RESPONSECRC     (1 << 17)
 109 #define S3C2410_SDIIMSK_CMDSENT         (1 << 16)
 110 #define S3C2410_SDIIMSK_CMDTIMEOUT      (1 << 15)
 111 #define S3C2410_SDIIMSK_RESPONSEND      (1 << 14)
 112 #define S3C2410_SDIIMSK_SDIOIRQ         (1 << 12)
 113 #define S3C2410_SDIIMSK_FIFOFAIL        (1 << 11)
 114 #define S3C2410_SDIIMSK_CRCSTATUS       (1 << 10)
 115 #define S3C2410_SDIIMSK_DATACRC         (1 << 9)
 116 #define S3C2410_SDIIMSK_DATATIMEOUT     (1 << 8)
 117 #define S3C2410_SDIIMSK_DATAFINISH      (1 << 7)
 118 #define S3C2410_SDIIMSK_TXFIFOHALF      (1 << 4)
 119 #define S3C2410_SDIIMSK_RXFIFOLAST      (1 << 2)
 120 #define S3C2410_SDIIMSK_RXFIFOHALF      (1 << 0)
 121
 122 enum dbg_channels {
 123         dbg_err   = (1 << 0),
 124         dbg_debug = (1 << 1),
 125         dbg_info  = (1 << 2),
 126         dbg_irq   = (1 << 3),
 127         dbg_sg    = (1 << 4),
 128         dbg_dma   = (1 << 5),
 129         dbg_pio   = (1 << 6),
 130         dbg_fail  = (1 << 7),
 131         dbg_conf  = (1 << 8),
 132 };
 133
 134 static const int dbgmap_err   = dbg_fail;
 135 static const int dbgmap_info  = dbg_info | dbg_conf;
 136 static const int dbgmap_debug = dbg_err | dbg_debug;
 137
 138 #define dbg(host, channels, args...)              \
 139         do {                                      \
 140         if (dbgmap_err & channels)                \
 141                 dev_err(&host->pdev->dev, args);  \
 142         else if (dbgmap_info & channels)          \
 143                 dev_info(&host->pdev->dev, args); \
 144         else if (dbgmap_debug & channels)         \
 145                 dev_dbg(&host->pdev->dev, args);  \
 146         } while (0)
 147
 148 static void finalize_request(struct s3cmci_host *host);
 149 static void s3cmci_send_request(struct mmc_host *mmc);
 150 static void s3cmci_reset(struct s3cmci_host *host);
 151
 152 #ifdef CONFIG_MMC_DEBUG
 153
 154 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
 155 {
 156         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
 157         u32 datcon, datcnt, datsta, fsta, imask;
 158
 159         con     = readl(host->base + S3C2410_SDICON);
 160         pre     = readl(host->base + S3C2410_SDIPRE);
 161         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
 162         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
 163         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
 164         r0      = readl(host->base + S3C2410_SDIRSP0);
 165         r1      = readl(host->base + S3C2410_SDIRSP1);
 166         r2      = readl(host->base + S3C2410_SDIRSP2);
 167         r3      = readl(host->base + S3C2410_SDIRSP3);
 168         timer   = readl(host->base + S3C2410_SDITIMER);
 169         bsize   = readl(host->base + S3C2410_SDIBSIZE);
 170         datcon  = readl(host->base + S3C2410_SDIDCON);
 171         datcnt  = readl(host->base + S3C2410_SDIDCNT);
 172         datsta  = readl(host->base + S3C2410_SDIDSTA);
 173         fsta    = readl(host->base + S3C2410_SDIFSTA);
 174         imask   = readl(host->base + host->sdiimsk);
 175
 176         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
 177                                 prefix, con, pre, timer);
 178
 179         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
 180                                 prefix, cmdcon, cmdarg, cmdsta);
 181
 182         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
 183                                " DSTA:[%08x] DCNT:[%08x]\n",
 184                                 prefix, datcon, fsta, datsta, datcnt);
 185
 186         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 187                                "   R2:[%08x]   R3:[%08x]\n",
 188                                 prefix, r0, r1, r2, r3);
 189 }
 190
 191 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 192                            int stop)
 193 {
 194         snprintf(host->dbgmsg_cmd, 300,
 195                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 196                  host->ccnt, (stop ? " (STOP)" : ""),
 197                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 198
 199         if (cmd->data) {
 200                 snprintf(host->dbgmsg_dat, 300,
 201                          "#%u bsize:%u blocks:%u bytes:%u",
 202                          host->dcnt, cmd->data->blksz,
 203                          cmd->data->blocks,
 204                          cmd->data->blocks * cmd->data->blksz);
 205         } else {
 206                 host->dbgmsg_dat[0] = '\0';
 207         }
 208 }
 209
 210 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 211                         int fail)
 212 {
 213         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 214
 215         if (!cmd)
 216                 return;
 217
 218         if (cmd->error == 0) {
 219                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 220                         host->dbgmsg_cmd, cmd->resp[0]);
 221         } else {
 222                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 223                         cmd->error, host->dbgmsg_cmd, host->status);
 224         }
 225
 226         if (!cmd->data)
 227                 return;
 228
 229         if (cmd->data->error == 0) {
 230                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 231         } else {
 232                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 233                         cmd->data->error, host->dbgmsg_dat,
 234                         readl(host->base + S3C2410_SDIDCNT));
 235         }
 236 }
 237 #else
 238 static void dbg_dumpcmd(struct s3cmci_host *host,
 239                         struct mmc_command *cmd, int fail) { }
 240
 241 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 242                            int stop) { }
 243
 244 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 245
 246 #endif /* CONFIG_MMC_DEBUG */
 247
 248 /**
 249  * s3cmci_host_usedma - return whether the host is using dma or pio
 250  * @host: The host state
 251  *
 252  * Return true if the host is using DMA to transfer data, else false
 253  * to use PIO mode. Will return static data depending on the driver
 254  * configuration.
 255  */
 256 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
 257 {
 258 #ifdef CONFIG_MMC_S3C_PIO
 259         return false;
 260 #else /* CONFIG_MMC_S3C_DMA */
 261         return true;
 262 #endif
 263 }
 264
 265 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 266 {
 267         u32 newmask;
 268
 269         newmask = readl(host->base + host->sdiimsk);
 270         newmask |= imask;
 271
 272         writel(newmask, host->base + host->sdiimsk);
 273
 274         return newmask;
 275 }
 276
 277 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 278 {
 279         u32 newmask;
 280
 281         newmask = readl(host->base + host->sdiimsk);
 282         newmask &= ~imask;
 283
 284         writel(newmask, host->base + host->sdiimsk);
 285
 286         return newmask;
 287 }
 288
 289 static inline void clear_imask(struct s3cmci_host *host)
 290 {
 291         u32 mask = readl(host->base + host->sdiimsk);
 292
 293         /* preserve the SDIO IRQ mask state */
 294         mask &= S3C2410_SDIIMSK_SDIOIRQ;
 295         writel(mask, host->base + host->sdiimsk);
 296 }
 297
 298 /**
 299  * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
 300  * @host: The host to check.
 301  *
 302  * Test to see if the SDIO interrupt is being signalled in case the
 303  * controller has failed to re-detect a card interrupt. Read GPE8 and
 304  * see if it is low and if so, signal a SDIO interrupt.
 305  *
 306  * This is currently called if a request is finished (we assume that the
 307  * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
 308  * already being indicated.
 309 */
 310 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
 311 {
 312         if (host->sdio_irqen) {
 313                 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
 314                         pr_debug("%s: signalling irq\n", __func__);
 315                         mmc_signal_sdio_irq(host->mmc);
 316                 }
 317         }
 318 }
 319
 320 static inline int get_data_buffer(struct s3cmci_host *host,
 321                                   u32 *bytes, u32 **pointer)
 322 {
 323         struct scatterlist *sg;
 324
 325         if (host->pio_active == XFER_NONE)
 326                 return -EINVAL;
 327
 328         if ((!host->mrq) || (!host->mrq->data))
 329                 return -EINVAL;
 330
 331         if (host->pio_sgptr >= host->mrq->data->sg_len) {
 332                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 333                       host->pio_sgptr, host->mrq->data->sg_len);
 334                 return -EBUSY;
 335         }
 336         sg = &host->mrq->data->sg[host->pio_sgptr];
 337
 338         *bytes = sg->length;
 339         *pointer = sg_virt(sg);
 340
 341         host->pio_sgptr++;
 342
 343         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 344             host->pio_sgptr, host->mrq->data->sg_len);
 345
 346         return 0;
 347 }
 348
 349 static inline u32 fifo_count(struct s3cmci_host *host)
 350 {
 351         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 352
 353         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 354         return fifostat;
 355 }
 356
 357 static inline u32 fifo_free(struct s3cmci_host *host)
 358 {
 359         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 360
 361         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 362         return 63 - fifostat;
 363 }
 364
 365 /**
 366  * s3cmci_enable_irq - enable IRQ, after having disabled it.
 367  * @host: The device state.
 368  * @more: True if more IRQs are expected from transfer.
 369  *
 370  * Enable the main IRQ if needed after it has been disabled.
 371  *
 372  * The IRQ can be one of the following states:
 373  *      - disabled during IDLE
 374  *      - disabled whilst processing data
 375  *      - enabled during transfer
 376  *      - enabled whilst awaiting SDIO interrupt detection
 377  */
 378 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
 379 {
 380         unsigned long flags;
 381         bool enable = false;
 382
 383         local_irq_save(flags);
 384
 385         host->irq_enabled = more;
 386         host->irq_disabled = false;
 387
 388         enable = more | host->sdio_irqen;
 389
 390         if (host->irq_state != enable) {
 391                 host->irq_state = enable;
 392
 393                 if (enable)
 394                         enable_irq(host->irq);
 395                 else
 396                         disable_irq(host->irq);
 397         }
 398
 399         local_irq_restore(flags);
 400 }
 401
 402 /**
 403  *
 404  */
 405 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
 406 {
 407         unsigned long flags;
 408
 409         local_irq_save(flags);
 410
 411         /* pr_debug("%s: transfer %d\n", __func__, transfer); */
 412
 413         host->irq_disabled = transfer;
 414
 415         if (transfer && host->irq_state) {
 416                 host->irq_state = false;
 417                 disable_irq(host->irq);
 418         }
 419
 420         local_irq_restore(flags);
 421 }
 422
 423 static void do_pio_read(struct s3cmci_host *host)
 424 {
 425         int res;
 426         u32 fifo;
 427         u32 *ptr;
 428         u32 fifo_words;
 429         void __iomem *from_ptr;
 430
 431         /* write real prescaler to host, it might be set slow to fix */
 432         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 433
 434         from_ptr = host->base + host->sdidata;
 435
 436         while ((fifo = fifo_count(host))) {
 437                 if (!host->pio_bytes) {
 438                         res = get_data_buffer(host, &host->pio_bytes,
 439                                               &host->pio_ptr);
 440                         if (res) {
 441                                 host->pio_active = XFER_NONE;
 442                                 host->complete_what = COMPLETION_FINALIZE;
 443
 444                                 dbg(host, dbg_pio, "pio_read(): "
 445                                     "complete (no more data).\n");
 446                                 return;
 447                         }
 448
 449                         dbg(host, dbg_pio,
 450                             "pio_read(): new target: [%i]@[%p]\n",
 451                             host->pio_bytes, host->pio_ptr);
 452                 }
 453
 454                 dbg(host, dbg_pio,
 455                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 456                     fifo, host->pio_bytes,
 457                     readl(host->base + S3C2410_SDIDCNT));
 458
 459                 /* If we have reached the end of the block, we can
 460                  * read a word and get 1 to 3 bytes.  If we in the
 461                  * middle of the block, we have to read full words,
 462                  * otherwise we will write garbage, so round down to
 463                  * an even multiple of 4. */
 464                 if (fifo >= host->pio_bytes)
 465                         fifo = host->pio_bytes;
 466                 else
 467                         fifo -= fifo & 3;
 468
 469                 host->pio_bytes -= fifo;
 470                 host->pio_count += fifo;
 471
 472                 fifo_words = fifo >> 2;
 473                 ptr = host->pio_ptr;
 474                 while (fifo_words--)
 475                         *ptr++ = readl(from_ptr);
 476                 host->pio_ptr = ptr;
 477
 478                 if (fifo & 3) {
 479                         u32 n = fifo & 3;
 480                         u32 data = readl(from_ptr);
 481                         u8 *p = (u8 *)host->pio_ptr;
 482
 483                         while (n--) {
 484                                 *p++ = data;
 485                                 data >>= 8;
 486                         }
 487                 }
 488         }
 489
 490         if (!host->pio_bytes) {
 491                 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
 492                 if (res) {
 493                         dbg(host, dbg_pio,
 494                             "pio_read(): complete (no more buffers).\n");
 495                         host->pio_active = XFER_NONE;
 496                         host->complete_what = COMPLETION_FINALIZE;
 497
 498                         return;
 499                 }
 500         }
 501
 502         enable_imask(host,
 503                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 504 }
 505
 506 static void do_pio_write(struct s3cmci_host *host)
 507 {
 508         void __iomem *to_ptr;
 509         int res;
 510         u32 fifo;
 511         u32 *ptr;
 512
 513         to_ptr = host->base + host->sdidata;
 514
 515         while ((fifo = fifo_free(host)) > 3) {
 516                 if (!host->pio_bytes) {
 517                         res = get_data_buffer(host, &host->pio_bytes,
 518                                                         &host->pio_ptr);
 519                         if (res) {
 520                                 dbg(host, dbg_pio,
 521                                     "pio_write(): complete (no more data).\n");
 522                                 host->pio_active = XFER_NONE;
 523
 524                                 return;
 525                         }
 526
 527                         dbg(host, dbg_pio,
 528                             "pio_write(): new source: [%i]@[%p]\n",
 529                             host->pio_bytes, host->pio_ptr);
 530
 531                 }
 532
 533                 /* If we have reached the end of the block, we have to
 534                  * write exactly the remaining number of bytes.  If we
 535                  * in the middle of the block, we have to write full
 536                  * words, so round down to an even multiple of 4. */
 537                 if (fifo >= host->pio_bytes)
 538                         fifo = host->pio_bytes;
 539                 else
 540                         fifo -= fifo & 3;
 541
 542                 host->pio_bytes -= fifo;
 543                 host->pio_count += fifo;
 544
 545                 fifo = (fifo + 3) >> 2;
 546                 ptr = host->pio_ptr;
 547                 while (fifo--)
 548                         writel(*ptr++, to_ptr);
 549                 host->pio_ptr = ptr;
 550         }
 551
 552         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 553 }
 554
 555 static void pio_tasklet(unsigned long data)
 556 {
 557         struct s3cmci_host *host = (struct s3cmci_host *) data;
 558
 559         s3cmci_disable_irq(host, true);
 560
 561         if (host->pio_active == XFER_WRITE)
 562                 do_pio_write(host);
 563
 564         if (host->pio_active == XFER_READ)
 565                 do_pio_read(host);
 566
 567         if (host->complete_what == COMPLETION_FINALIZE) {
 568                 clear_imask(host);
 569                 if (host->pio_active != XFER_NONE) {
 570                         dbg(host, dbg_err, "unfinished %s "
 571                             "- pio_count:[%u] pio_bytes:[%u]\n",
 572                             (host->pio_active == XFER_READ) ? "read" : "write",
 573                             host->pio_count, host->pio_bytes);
 574
 575                         if (host->mrq->data)
 576                                 host->mrq->data->error = -EINVAL;
 577                 }
 578
 579                 s3cmci_enable_irq(host, false);
 580                 finalize_request(host);
 581         } else
 582                 s3cmci_enable_irq(host, true);
 583 }
 584
 585 /*
 586  * ISR for SDI Interface IRQ
 587  * Communication between driver and ISR works as follows:
 588  *   host->mrq                  points to current request
 589  *   host->complete_what        Indicates when the request is considered done
 590  *     COMPLETION_CMDSENT         when the command was sent
 591  *     COMPLETION_RSPFIN          when a response was received
 592  *     COMPLETION_XFERFINISH      when the data transfer is finished
 593  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 594  *   host->complete_request     is the completion-object the driver waits for
 595  *
 596  * 1) Driver sets up host->mrq and host->complete_what
 597  * 2) Driver prepares the transfer
 598  * 3) Driver enables interrupts
 599  * 4) Driver starts transfer
 600  * 5) Driver waits for host->complete_rquest
 601  * 6) ISR checks for request status (errors and success)
 602  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 603  * 7) ISR completes host->complete_request
 604  * 8) ISR disables interrupts
 605  * 9) Driver wakes up and takes care of the request
 606  *
 607  * Note: "->error"-fields are expected to be set to 0 before the request
 608  *       was issued by mmc.c - therefore they are only set, when an error
 609  *       contition comes up
 610  */
 611
 612 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 613 {
 614         struct s3cmci_host *host = dev_id;
 615         struct mmc_command *cmd;
 616         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 617         u32 mci_cclear = 0, mci_dclear;
 618         unsigned long iflags;
 619
 620         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 621         mci_imsk = readl(host->base + host->sdiimsk);
 622
 623         if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
 624                 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
 625                         mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
 626                         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 627
 628                         mmc_signal_sdio_irq(host->mmc);
 629                         return IRQ_HANDLED;
 630                 }
 631         }
 632
 633         spin_lock_irqsave(&host->complete_lock, iflags);
 634
 635         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 636         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 637         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 638         mci_dclear = 0;
 639
 640         if ((host->complete_what == COMPLETION_NONE) ||
 641             (host->complete_what == COMPLETION_FINALIZE)) {
 642                 host->status = "nothing to complete";
 643                 clear_imask(host);
 644                 goto irq_out;
 645         }
 646
 647         if (!host->mrq) {
 648                 host->status = "no active mrq";
 649                 clear_imask(host);
 650                 goto irq_out;
 651         }
 652
 653         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 654
 655         if (!cmd) {
 656                 host->status = "no active cmd";
 657                 clear_imask(host);
 658                 goto irq_out;
 659         }
 660
 661         if (!s3cmci_host_usedma(host)) {
 662                 if ((host->pio_active == XFER_WRITE) &&
 663                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 664
 665                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 666                         tasklet_schedule(&host->pio_tasklet);
 667                         host->status = "pio tx";
 668                 }
 669
 670                 if ((host->pio_active == XFER_READ) &&
 671                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 672
 673                         disable_imask(host,
 674                                       S3C2410_SDIIMSK_RXFIFOHALF |
 675                                       S3C2410_SDIIMSK_RXFIFOLAST);
 676
 677                         tasklet_schedule(&host->pio_tasklet);
 678                         host->status = "pio rx";
 679                 }
 680         }
 681
 682         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 683                 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
 684                 cmd->error = -ETIMEDOUT;
 685                 host->status = "error: command timeout";
 686                 goto fail_transfer;
 687         }
 688
 689         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 690                 if (host->complete_what == COMPLETION_CMDSENT) {
 691                         host->status = "ok: command sent";
 692                         goto close_transfer;
 693                 }
 694
 695                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 696         }
 697
 698         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 699                 if (cmd->flags & MMC_RSP_CRC) {
 700                         if (host->mrq->cmd->flags & MMC_RSP_136) {
 701                                 dbg(host, dbg_irq,
 702                                     "fixup: ignore CRC fail with long rsp\n");
 703                         } else {
 704                                 /* note, we used to fail the transfer
 705                                  * here, but it seems that this is just
 706                                  * the hardware getting it wrong.
 707                                  *
 708                                  * cmd->error = -EILSEQ;
 709                                  * host->status = "error: bad command crc";
 710                                  * goto fail_transfer;
 711                                 */
 712                         }
 713                 }
 714
 715                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 716         }
 717
 718         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 719                 if (host->complete_what == COMPLETION_RSPFIN) {
 720                         host->status = "ok: command response received";
 721                         goto close_transfer;
 722                 }
 723
 724                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 725                         host->complete_what = COMPLETION_XFERFINISH;
 726
 727                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 728         }
 729
 730         /* errors handled after this point are only relevant
 731            when a data transfer is in progress */
 732
 733         if (!cmd->data)
 734                 goto clear_status_bits;
 735
 736         /* Check for FIFO failure */
 737         if (host->is2440) {
 738                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 739                         dbg(host, dbg_err, "FIFO failure\n");
 740                         host->mrq->data->error = -EILSEQ;
 741                         host->status = "error: 2440 fifo failure";
 742                         goto fail_transfer;
 743                 }
 744         } else {
 745                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 746                         dbg(host, dbg_err, "FIFO failure\n");
 747                         cmd->data->error = -EILSEQ;
 748                         host->status = "error:  fifo failure";
 749                         goto fail_transfer;
 750                 }
 751         }
 752
 753         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 754                 dbg(host, dbg_err, "bad data crc (outgoing)\n");
 755                 cmd->data->error = -EILSEQ;
 756                 host->status = "error: bad data crc (outgoing)";
 757                 goto fail_transfer;
 758         }
 759
 760         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 761                 dbg(host, dbg_err, "bad data crc (incoming)\n");
 762                 cmd->data->error = -EILSEQ;
 763                 host->status = "error: bad data crc (incoming)";
 764                 goto fail_transfer;
 765         }
 766
 767         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 768                 dbg(host, dbg_err, "data timeout\n");
 769                 cmd->data->error = -ETIMEDOUT;
 770                 host->status = "error: data timeout";
 771                 goto fail_transfer;
 772         }
 773
 774         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 775                 if (host->complete_what == COMPLETION_XFERFINISH) {
 776                         host->status = "ok: data transfer completed";
 777                         goto close_transfer;
 778                 }
 779
 780                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 781                         host->complete_what = COMPLETION_RSPFIN;
 782
 783                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 784         }
 785
 786 clear_status_bits:
 787         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 788         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 789
 790         goto irq_out;
 791
 792 fail_transfer:
 793         host->pio_active = XFER_NONE;
 794
 795 close_transfer:
 796         host->complete_what = COMPLETION_FINALIZE;
 797
 798         clear_imask(host);
 799         tasklet_schedule(&host->pio_tasklet);
 800
 801         goto irq_out;
 802
 803 irq_out:
 804         dbg(host, dbg_irq,
 805             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 806             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 807
 808         spin_unlock_irqrestore(&host->complete_lock, iflags);
 809         return IRQ_HANDLED;
 810
 811 }
 812
 813 static void s3cmci_dma_done_callback(void *arg)
 814 {
 815         struct s3cmci_host *host = arg;
 816         unsigned long iflags;
 817
 818         BUG_ON(!host->mrq);
 819         BUG_ON(!host->mrq->data);
 820
 821         spin_lock_irqsave(&host->complete_lock, iflags);
 822
 823         dbg(host, dbg_dma, "DMA FINISHED\n");
 824
 825         host->dma_complete = 1;
 826         host->complete_what = COMPLETION_FINALIZE;
 827
 828         tasklet_schedule(&host->pio_tasklet);
 829         spin_unlock_irqrestore(&host->complete_lock, iflags);
 830
 831 }
 832
 833 static void finalize_request(struct s3cmci_host *host)
 834 {
 835         struct mmc_request *mrq = host->mrq;
 836         struct mmc_command *cmd;
 837         int debug_as_failure = 0;
 838
 839         if (host->complete_what != COMPLETION_FINALIZE)
 840                 return;
 841
 842         if (!mrq)
 843                 return;
 844         cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 845
 846         if (cmd->data && (cmd->error == 0) &&
 847             (cmd->data->error == 0)) {
 848                 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
 849                         dbg(host, dbg_dma, "DMA Missing (%d)!\n",
 850                             host->dma_complete);
 851                         return;
 852                 }
 853         }
 854
 855         /* Read response from controller. */
 856         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 857         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 858         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 859         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 860
 861         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 862
 863         if (cmd->error)
 864                 debug_as_failure = 1;
 865
 866         if (cmd->data && cmd->data->error)
 867                 debug_as_failure = 1;
 868
 869         dbg_dumpcmd(host, cmd, debug_as_failure);
 870
 871         /* Cleanup controller */
 872         writel(0, host->base + S3C2410_SDICMDARG);
 873         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 874         writel(0, host->base + S3C2410_SDICMDCON);
 875         clear_imask(host);
 876
 877         if (cmd->data && cmd->error)
 878                 cmd->data->error = cmd->error;
 879
 880         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 881                 host->cmd_is_stop = 1;
 882                 s3cmci_send_request(host->mmc);
 883                 return;
 884         }
 885
 886         /* If we have no data transfer we are finished here */
 887         if (!mrq->data)
 888                 goto request_done;
 889
 890         /* Calculate the amout of bytes transfer if there was no error */
 891         if (mrq->data->error == 0) {
 892                 mrq->data->bytes_xfered =
 893                         (mrq->data->blocks * mrq->data->blksz);
 894         } else {
 895                 mrq->data->bytes_xfered = 0;
 896         }
 897
 898         /* If we had an error while transferring data we flush the
 899          * DMA channel and the fifo to clear out any garbage. */
 900         if (mrq->data->error != 0) {
 901                 if (s3cmci_host_usedma(host))
 902                         dmaengine_terminate_all(host->dma);
 903
 904                 if (host->is2440) {
 905                         /* Clear failure register and reset fifo. */
 906                         writel(S3C2440_SDIFSTA_FIFORESET |
 907                                S3C2440_SDIFSTA_FIFOFAIL,
 908                                host->base + S3C2410_SDIFSTA);
 909                 } else {
 910                         u32 mci_con;
 911
 912                         /* reset fifo */
 913                         mci_con = readl(host->base + S3C2410_SDICON);
 914                         mci_con |= S3C2410_SDICON_FIFORESET;
 915
 916                         writel(mci_con, host->base + S3C2410_SDICON);
 917                 }
 918         }
 919
 920 request_done:
 921         host->complete_what = COMPLETION_NONE;
 922         host->mrq = NULL;
 923
 924         s3cmci_check_sdio_irq(host);
 925         mmc_request_done(host->mmc, mrq);
 926 }
 927
 928 static void s3cmci_send_command(struct s3cmci_host *host,
 929                                         struct mmc_command *cmd)
 930 {
 931         u32 ccon, imsk;
 932
 933         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
 934                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
 935                 S3C2410_SDIIMSK_RESPONSECRC;
 936
 937         enable_imask(host, imsk);
 938
 939         if (cmd->data)
 940                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
 941         else if (cmd->flags & MMC_RSP_PRESENT)
 942                 host->complete_what = COMPLETION_RSPFIN;
 943         else
 944                 host->complete_what = COMPLETION_CMDSENT;
 945
 946         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
 947
 948         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
 949         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
 950
 951         if (cmd->flags & MMC_RSP_PRESENT)
 952                 ccon |= S3C2410_SDICMDCON_WAITRSP;
 953
 954         if (cmd->flags & MMC_RSP_136)
 955                 ccon |= S3C2410_SDICMDCON_LONGRSP;
 956
 957         writel(ccon, host->base + S3C2410_SDICMDCON);
 958 }
 959
 960 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
 961 {
 962         u32 dcon, imsk, stoptries = 3;
 963
 964         /* write DCON register */
 965
 966         if (!data) {
 967                 writel(0, host->base + S3C2410_SDIDCON);
 968                 return 0;
 969         }
 970
 971         if ((data->blksz & 3) != 0) {
 972                 /* We cannot deal with unaligned blocks with more than
 973                  * one block being transferred. */
 974
 975                 if (data->blocks > 1) {
 976                         pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
 977                                 __func__, data->blksz);
 978                         return -EINVAL;
 979                 }
 980         }
 981
 982         while (readl(host->base + S3C2410_SDIDSTA) &
 983                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
 984
 985                 dbg(host, dbg_err,
 986                     "mci_setup_data() transfer stillin progress.\n");
 987
 988                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 989                 s3cmci_reset(host);
 990
 991                 if ((stoptries--) == 0) {
 992                         dbg_dumpregs(host, "DRF");
 993                         return -EINVAL;
 994                 }
 995         }
 996
 997         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
 998
 999         if (s3cmci_host_usedma(host))
1000                 dcon |= S3C2410_SDIDCON_DMAEN;
1001
1002         if (host->bus_width == MMC_BUS_WIDTH_4)
1003                 dcon |= S3C2410_SDIDCON_WIDEBUS;
1004
1005         dcon |= S3C2410_SDIDCON_BLOCKMODE;
1006
1007         if (data->flags & MMC_DATA_WRITE) {
1008                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1009                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1010         }
1011
1012         if (data->flags & MMC_DATA_READ) {
1013                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1014                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1015         }
1016
1017         if (host->is2440) {
1018                 dcon |= S3C2440_SDIDCON_DS_WORD;
1019                 dcon |= S3C2440_SDIDCON_DATSTART;
1020         }
1021
1022         writel(dcon, host->base + S3C2410_SDIDCON);
1023
1024         /* write BSIZE register */
1025
1026         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1027
1028         /* add to IMASK register */
1029         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1030                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1031
1032         enable_imask(host, imsk);
1033
1034         /* write TIMER register */
1035
1036         if (host->is2440) {
1037                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1038         } else {
1039                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1040
1041                 /* FIX: set slow clock to prevent timeouts on read */
1042                 if (data->flags & MMC_DATA_READ)
1043                         writel(0xFF, host->base + S3C2410_SDIPRE);
1044         }
1045
1046         return 0;
1047 }
1048
1049 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1050
1051 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1052 {
1053         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1054
1055         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1056
1057         host->pio_sgptr = 0;
1058         host->pio_bytes = 0;
1059         host->pio_count = 0;
1060         host->pio_active = rw ? XFER_WRITE : XFER_READ;
1061
1062         if (rw) {
1063                 do_pio_write(host);
1064                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1065         } else {
1066                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1067                              | S3C2410_SDIIMSK_RXFIFOLAST);
1068         }
1069
1070         return 0;
1071 }
1072
1073 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1074 {
1075         int rw = data->flags & MMC_DATA_WRITE;
1076         struct dma_async_tx_descriptor *desc;
1077         struct dma_slave_config conf = {
1078                 .src_addr = host->mem->start + host->sdidata,
1079                 .dst_addr = host->mem->start + host->sdidata,
1080                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1081                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1082         };
1083
1084         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1085
1086         /* Restore prescaler value */
1087         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1088
1089         if (!rw)
1090                 conf.direction = DMA_DEV_TO_MEM;
1091         else
1092                 conf.direction = DMA_MEM_TO_DEV;
1093
1094         dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1095                    mmc_get_dma_dir(data));
1096
1097         dmaengine_slave_config(host->dma, &conf);
1098         desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1099                 conf.direction,
1100                 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1101         if (!desc)
1102                 goto unmap_exit;
1103         desc->callback = s3cmci_dma_done_callback;
1104         desc->callback_param = host;
1105         dmaengine_submit(desc);
1106         dma_async_issue_pending(host->dma);
1107
1108         return 0;
1109
1110 unmap_exit:
1111         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1112                      mmc_get_dma_dir(data));
1113         return -ENOMEM;
1114 }
1115
1116 static void s3cmci_send_request(struct mmc_host *mmc)
1117 {
1118         struct s3cmci_host *host = mmc_priv(mmc);
1119         struct mmc_request *mrq = host->mrq;
1120         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1121
1122         host->ccnt++;
1123         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1124
1125         /* Clear command, data and fifo status registers
1126            Fifo clear only necessary on 2440, but doesn't hurt on 2410
1127         */
1128         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1129         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1130         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1131
1132         if (cmd->data) {
1133                 int res = s3cmci_setup_data(host, cmd->data);
1134
1135                 host->dcnt++;
1136
1137                 if (res) {
1138                         dbg(host, dbg_err, "setup data error %d\n", res);
1139                         cmd->error = res;
1140                         cmd->data->error = res;
1141
1142                         mmc_request_done(mmc, mrq);
1143                         return;
1144                 }
1145
1146                 if (s3cmci_host_usedma(host))
1147                         res = s3cmci_prepare_dma(host, cmd->data);
1148                 else
1149                         res = s3cmci_prepare_pio(host, cmd->data);
1150
1151                 if (res) {
1152                         dbg(host, dbg_err, "data prepare error %d\n", res);
1153                         cmd->error = res;
1154                         cmd->data->error = res;
1155
1156                         mmc_request_done(mmc, mrq);
1157                         return;
1158                 }
1159         }
1160
1161         /* Send command */
1162         s3cmci_send_command(host, cmd);
1163
1164         /* Enable Interrupt */
1165         s3cmci_enable_irq(host, true);
1166 }
1167
1168 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1169 {
1170         struct s3cmci_host *host = mmc_priv(mmc);
1171
1172         host->status = "mmc request";
1173         host->cmd_is_stop = 0;
1174         host->mrq = mrq;
1175
1176         if (mmc_gpio_get_cd(mmc) == 0) {
1177                 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1178                 host->mrq->cmd->error = -ENOMEDIUM;
1179                 mmc_request_done(mmc, mrq);
1180         } else
1181                 s3cmci_send_request(mmc);
1182 }
1183
1184 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1185 {
1186         u32 mci_psc;
1187
1188         /* Set clock */
1189         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1190                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1191
1192                 if (host->real_rate <= ios->clock)
1193                         break;
1194         }
1195
1196         if (mci_psc > 255)
1197                 mci_psc = 255;
1198
1199         host->prescaler = mci_psc;
1200         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1201
1202         /* If requested clock is 0, real_rate will be 0, too */
1203         if (ios->clock == 0)
1204                 host->real_rate = 0;
1205 }
1206
1207 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1208 {
1209         struct s3cmci_host *host = mmc_priv(mmc);
1210         u32 mci_con;
1211
1212         /* Set the power state */
1213
1214         mci_con = readl(host->base + S3C2410_SDICON);
1215
1216         switch (ios->power_mode) {
1217         case MMC_POWER_ON:
1218         case MMC_POWER_UP:
1219                 /* Configure GPE5...GPE10 pins in SD mode */
1220                 if (!host->pdev->dev.of_node)
1221                         s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1222                                               S3C_GPIO_PULL_NONE);
1223
1224                 if (host->pdata->set_power)
1225                         host->pdata->set_power(ios->power_mode, ios->vdd);
1226
1227                 if (!host->is2440)
1228                         mci_con |= S3C2410_SDICON_FIFORESET;
1229
1230                 break;
1231
1232         case MMC_POWER_OFF:
1233         default:
1234                 if (!host->pdev->dev.of_node)
1235                         gpio_direction_output(S3C2410_GPE(5), 0);
1236
1237                 if (host->is2440)
1238                         mci_con |= S3C2440_SDICON_SDRESET;
1239
1240                 if (host->pdata->set_power)
1241                         host->pdata->set_power(ios->power_mode, ios->vdd);
1242
1243                 break;
1244         }
1245
1246         s3cmci_set_clk(host, ios);
1247
1248         /* Set CLOCK_ENABLE */
1249         if (ios->clock)
1250                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1251         else
1252                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1253
1254         writel(mci_con, host->base + S3C2410_SDICON);
1255
1256         if ((ios->power_mode == MMC_POWER_ON) ||
1257             (ios->power_mode == MMC_POWER_UP)) {
1258                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1259                         host->real_rate/1000, ios->clock/1000);
1260         } else {
1261                 dbg(host, dbg_conf, "powered down.\n");
1262         }
1263
1264         host->bus_width = ios->bus_width;
1265 }
1266
1267 static void s3cmci_reset(struct s3cmci_host *host)
1268 {
1269         u32 con = readl(host->base + S3C2410_SDICON);
1270
1271         con |= S3C2440_SDICON_SDRESET;
1272         writel(con, host->base + S3C2410_SDICON);
1273 }
1274
1275 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1276 {
1277         struct s3cmci_host *host = mmc_priv(mmc);
1278         unsigned long flags;
1279         u32 con;
1280
1281         local_irq_save(flags);
1282
1283         con = readl(host->base + S3C2410_SDICON);
1284         host->sdio_irqen = enable;
1285
1286         if (enable == host->sdio_irqen)
1287                 goto same_state;
1288
1289         if (enable) {
1290                 con |= S3C2410_SDICON_SDIOIRQ;
1291                 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1292
1293                 if (!host->irq_state && !host->irq_disabled) {
1294                         host->irq_state = true;
1295                         enable_irq(host->irq);
1296                 }
1297         } else {
1298                 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1299                 con &= ~S3C2410_SDICON_SDIOIRQ;
1300
1301                 if (!host->irq_enabled && host->irq_state) {
1302                         disable_irq_nosync(host->irq);
1303                         host->irq_state = false;
1304                 }
1305         }
1306
1307         writel(con, host->base + S3C2410_SDICON);
1308
1309  same_state:
1310         local_irq_restore(flags);
1311
1312         s3cmci_check_sdio_irq(host);
1313 }
1314
1315 static const struct mmc_host_ops s3cmci_ops = {
1316         .request        = s3cmci_request,
1317         .set_ios        = s3cmci_set_ios,
1318         .get_ro         = mmc_gpio_get_ro,
1319         .get_cd         = mmc_gpio_get_cd,
1320         .enable_sdio_irq = s3cmci_enable_sdio_irq,
1321 };
1322
1323 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1324         /* This is currently here to avoid a number of if (host->pdata)
1325          * checks. Any zero fields to ensure reasonable defaults are picked. */
1326          .no_wprotect = 1,
1327          .no_detect = 1,
1328 };
1329
1330 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1331
1332 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1333                                      unsigned long val, void *data)
1334 {
1335         struct s3cmci_host *host;
1336         struct mmc_host *mmc;
1337         unsigned long newclk;
1338         unsigned long flags;
1339
1340         host = container_of(nb, struct s3cmci_host, freq_transition);
1341         newclk = clk_get_rate(host->clk);
1342         mmc = host->mmc;
1343
1344         if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1345             (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1346                 spin_lock_irqsave(&mmc->lock, flags);
1347
1348                 host->clk_rate = newclk;
1349
1350                 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1351                     mmc->ios.clock != 0)
1352                         s3cmci_set_clk(host, &mmc->ios);
1353
1354                 spin_unlock_irqrestore(&mmc->lock, flags);
1355         }
1356
1357         return 0;
1358 }
1359
1360 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1361 {
1362         host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1363
1364         return cpufreq_register_notifier(&host->freq_transition,
1365                                          CPUFREQ_TRANSITION_NOTIFIER);
1366 }
1367
1368 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1369 {
1370         cpufreq_unregister_notifier(&host->freq_transition,
1371                                     CPUFREQ_TRANSITION_NOTIFIER);
1372 }
1373
1374 #else
1375 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1376 {
1377         return 0;
1378 }
1379
1380 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1381 {
1382 }
1383 #endif
1384
1385
1386 #ifdef CONFIG_DEBUG_FS
1387
1388 static int s3cmci_state_show(struct seq_file *seq, void *v)
1389 {
1390         struct s3cmci_host *host = seq->private;
1391
1392         seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1393         seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1394         seq_printf(seq, "Prescale = %d\n", host->prescaler);
1395         seq_printf(seq, "is2440 = %d\n", host->is2440);
1396         seq_printf(seq, "IRQ = %d\n", host->irq);
1397         seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1398         seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1399         seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1400         seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1401         seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1402         seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1403         seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1404
1405         return 0;
1406 }
1407
1408 DEFINE_SHOW_ATTRIBUTE(s3cmci_state);
1409
1410 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1411
1412 struct s3cmci_reg {
1413         unsigned short  addr;
1414         unsigned char   *name;
1415 };
1416
1417 static const struct s3cmci_reg debug_regs[] = {
1418         DBG_REG(CON),
1419         DBG_REG(PRE),
1420         DBG_REG(CMDARG),
1421         DBG_REG(CMDCON),
1422         DBG_REG(CMDSTAT),
1423         DBG_REG(RSP0),
1424         DBG_REG(RSP1),
1425         DBG_REG(RSP2),
1426         DBG_REG(RSP3),
1427         DBG_REG(TIMER),
1428         DBG_REG(BSIZE),
1429         DBG_REG(DCON),
1430         DBG_REG(DCNT),
1431         DBG_REG(DSTA),
1432         DBG_REG(FSTA),
1433         {}
1434 };
1435
1436 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1437 {
1438         struct s3cmci_host *host = seq->private;
1439         const struct s3cmci_reg *rptr = debug_regs;
1440
1441         for (; rptr->name; rptr++)
1442                 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1443                            readl(host->base + rptr->addr));
1444
1445         seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1446
1447         return 0;
1448 }
1449
1450 DEFINE_SHOW_ATTRIBUTE(s3cmci_regs);
1451
1452 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1453 {
1454         struct device *dev = &host->pdev->dev;
1455
1456         host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1457         if (IS_ERR(host->debug_root)) {
1458                 dev_err(dev, "failed to create debugfs root\n");
1459                 return;
1460         }
1461
1462         host->debug_state = debugfs_create_file("state", 0444,
1463                                                 host->debug_root, host,
1464                                                 &s3cmci_state_fops);
1465
1466         if (IS_ERR(host->debug_state))
1467                 dev_err(dev, "failed to create debug state file\n");
1468
1469         host->debug_regs = debugfs_create_file("regs", 0444,
1470                                                host->debug_root, host,
1471                                                &s3cmci_regs_fops);
1472
1473         if (IS_ERR(host->debug_regs))
1474                 dev_err(dev, "failed to create debug regs file\n");
1475 }
1476
1477 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1478 {
1479         debugfs_remove(host->debug_regs);
1480         debugfs_remove(host->debug_state);
1481         debugfs_remove(host->debug_root);
1482 }
1483
1484 #else
1485 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1486 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1487
1488 #endif /* CONFIG_DEBUG_FS */
1489
1490 static int s3cmci_probe_pdata(struct s3cmci_host *host)
1491 {
1492         struct platform_device *pdev = host->pdev;
1493         struct mmc_host *mmc = host->mmc;
1494         struct s3c24xx_mci_pdata *pdata;
1495         int i, ret;
1496
1497         host->is2440 = platform_get_device_id(pdev)->driver_data;
1498
1499         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1500                 ret = gpio_request(i, dev_name(&pdev->dev));
1501                 if (ret) {
1502                         dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1503
1504                         for (i--; i >= S3C2410_GPE(5); i--)
1505                                 gpio_free(i);
1506
1507                         return ret;
1508                 }
1509         }
1510
1511         if (!pdev->dev.platform_data)
1512                 pdev->dev.platform_data = &s3cmci_def_pdata;
1513
1514         pdata = pdev->dev.platform_data;
1515
1516         if (pdata->no_wprotect)
1517                 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1518
1519         if (pdata->no_detect)
1520                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1521
1522         if (pdata->wprotect_invert)
1523                 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1524
1525         /* If we get -ENOENT we have no card detect GPIO line */
1526         ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
1527         if (ret != -ENOENT) {
1528                 dev_err(&pdev->dev, "error requesting GPIO for CD %d\n",
1529                         ret);
1530                 return ret;
1531         }
1532
1533         ret = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0, NULL);
1534         if (ret != -ENOENT) {
1535                 dev_err(&pdev->dev, "error requesting GPIO for WP %d\n",
1536                         ret);
1537                 return ret;
1538         }
1539
1540         return 0;
1541 }
1542
1543 static int s3cmci_probe_dt(struct s3cmci_host *host)
1544 {
1545         struct platform_device *pdev = host->pdev;
1546         struct s3c24xx_mci_pdata *pdata;
1547         struct mmc_host *mmc = host->mmc;
1548         int ret;
1549
1550         host->is2440 = (int) of_device_get_match_data(&pdev->dev);
1551
1552         ret = mmc_of_parse(mmc);
1553         if (ret)
1554                 return ret;
1555
1556         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1557         if (!pdata)
1558                 return -ENOMEM;
1559
1560         pdev->dev.platform_data = pdata;
1561
1562         return 0;
1563 }
1564
1565 static int s3cmci_probe(struct platform_device *pdev)
1566 {
1567         struct s3cmci_host *host;
1568         struct mmc_host *mmc;
1569         int ret;
1570         int i;
1571
1572         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1573         if (!mmc) {
1574                 ret = -ENOMEM;
1575                 goto probe_out;
1576         }
1577
1578         host = mmc_priv(mmc);
1579         host->mmc       = mmc;
1580         host->pdev      = pdev;
1581
1582         if (pdev->dev.of_node)
1583                 ret = s3cmci_probe_dt(host);
1584         else
1585                 ret = s3cmci_probe_pdata(host);
1586
1587         if (ret)
1588                 goto probe_free_host;
1589
1590         host->pdata = pdev->dev.platform_data;
1591
1592         spin_lock_init(&host->complete_lock);
1593         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1594
1595         if (host->is2440) {
1596                 host->sdiimsk   = S3C2440_SDIIMSK;
1597                 host->sdidata   = S3C2440_SDIDATA;
1598                 host->clk_div   = 1;
1599         } else {
1600                 host->sdiimsk   = S3C2410_SDIIMSK;
1601                 host->sdidata   = S3C2410_SDIDATA;
1602                 host->clk_div   = 2;
1603         }
1604
1605         host->complete_what     = COMPLETION_NONE;
1606         host->pio_active        = XFER_NONE;
1607
1608         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1609         if (!host->mem) {
1610                 dev_err(&pdev->dev,
1611                         "failed to get io memory region resource.\n");
1612
1613                 ret = -ENOENT;
1614                 goto probe_free_gpio;
1615         }
1616
1617         host->mem = request_mem_region(host->mem->start,
1618                                        resource_size(host->mem), pdev->name);
1619
1620         if (!host->mem) {
1621                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1622                 ret = -ENOENT;
1623                 goto probe_free_gpio;
1624         }
1625
1626         host->base = ioremap(host->mem->start, resource_size(host->mem));
1627         if (!host->base) {
1628                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1629                 ret = -EINVAL;
1630                 goto probe_free_mem_region;
1631         }
1632
1633         host->irq = platform_get_irq(pdev, 0);
1634         if (host->irq <= 0) {
1635                 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1636                 ret = -EINVAL;
1637                 goto probe_iounmap;
1638         }
1639
1640         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1641                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1642                 ret = -ENOENT;
1643                 goto probe_iounmap;
1644         }
1645
1646         /* We get spurious interrupts even when we have set the IMSK
1647          * register to ignore everything, so use disable_irq() to make
1648          * ensure we don't lock the system with un-serviceable requests. */
1649
1650         disable_irq(host->irq);
1651         host->irq_state = false;
1652
1653         /* Depending on the dma state, get a DMA channel to use. */
1654
1655         if (s3cmci_host_usedma(host)) {
1656                 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1657                 ret = PTR_ERR_OR_ZERO(host->dma);
1658                 if (ret) {
1659                         dev_err(&pdev->dev, "cannot get DMA channel.\n");
1660                         goto probe_free_irq;
1661                 }
1662         }
1663
1664         host->clk = clk_get(&pdev->dev, "sdi");
1665         if (IS_ERR(host->clk)) {
1666                 dev_err(&pdev->dev, "failed to find clock source.\n");
1667                 ret = PTR_ERR(host->clk);
1668                 host->clk = NULL;
1669                 goto probe_free_dma;
1670         }
1671
1672         ret = clk_prepare_enable(host->clk);
1673         if (ret) {
1674                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1675                 goto clk_free;
1676         }
1677
1678         host->clk_rate = clk_get_rate(host->clk);
1679
1680         mmc->ops        = &s3cmci_ops;
1681         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1682 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1683         mmc->caps       = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1684 #else
1685         mmc->caps       = MMC_CAP_4_BIT_DATA;
1686 #endif
1687         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1688         mmc->f_max      = host->clk_rate / host->clk_div;
1689
1690         if (host->pdata->ocr_avail)
1691                 mmc->ocr_avail = host->pdata->ocr_avail;
1692
1693         mmc->max_blk_count      = 4095;
1694         mmc->max_blk_size       = 4095;
1695         mmc->max_req_size       = 4095 * 512;
1696         mmc->max_seg_size       = mmc->max_req_size;
1697
1698         mmc->max_segs           = 128;
1699
1700         dbg(host, dbg_debug,
1701             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1702             (host->is2440?"2440":""),
1703             host->base, host->irq, host->irq_cd, host->dma);
1704
1705         ret = s3cmci_cpufreq_register(host);
1706         if (ret) {
1707                 dev_err(&pdev->dev, "failed to register cpufreq\n");
1708                 goto free_dmabuf;
1709         }
1710
1711         ret = mmc_add_host(mmc);
1712         if (ret) {
1713                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1714                 goto free_cpufreq;
1715         }
1716
1717         s3cmci_debugfs_attach(host);
1718
1719         platform_set_drvdata(pdev, mmc);
1720         dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1721                  s3cmci_host_usedma(host) ? "dma" : "pio",
1722                  mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1723
1724         return 0;
1725
1726  free_cpufreq:
1727         s3cmci_cpufreq_deregister(host);
1728
1729  free_dmabuf:
1730         clk_disable_unprepare(host->clk);
1731
1732  clk_free:
1733         clk_put(host->clk);
1734
1735  probe_free_dma:
1736         if (s3cmci_host_usedma(host))
1737                 dma_release_channel(host->dma);
1738
1739  probe_free_irq:
1740         free_irq(host->irq, host);
1741
1742  probe_iounmap:
1743         iounmap(host->base);
1744
1745  probe_free_mem_region:
1746         release_mem_region(host->mem->start, resource_size(host->mem));
1747
1748  probe_free_gpio:
1749         if (!pdev->dev.of_node)
1750                 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1751                         gpio_free(i);
1752
1753  probe_free_host:
1754         mmc_free_host(mmc);
1755
1756  probe_out:
1757         return ret;
1758 }
1759
1760 static void s3cmci_shutdown(struct platform_device *pdev)
1761 {
1762         struct mmc_host *mmc = platform_get_drvdata(pdev);
1763         struct s3cmci_host *host = mmc_priv(mmc);
1764
1765         if (host->irq_cd >= 0)
1766                 free_irq(host->irq_cd, host);
1767
1768         s3cmci_debugfs_remove(host);
1769         s3cmci_cpufreq_deregister(host);
1770         mmc_remove_host(mmc);
1771         clk_disable_unprepare(host->clk);
1772 }
1773
1774 static int s3cmci_remove(struct platform_device *pdev)
1775 {
1776         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1777         struct s3cmci_host      *host = mmc_priv(mmc);
1778         int i;
1779
1780         s3cmci_shutdown(pdev);
1781
1782         clk_put(host->clk);
1783
1784         tasklet_disable(&host->pio_tasklet);
1785
1786         if (s3cmci_host_usedma(host))
1787                 dma_release_channel(host->dma);
1788
1789         free_irq(host->irq, host);
1790
1791         if (!pdev->dev.of_node)
1792                 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1793                         gpio_free(i);
1794
1795         iounmap(host->base);
1796         release_mem_region(host->mem->start, resource_size(host->mem));
1797
1798         mmc_free_host(mmc);
1799         return 0;
1800 }
1801
1802 static const struct of_device_id s3cmci_dt_match[] = {
1803         {
1804                 .compatible = "samsung,s3c2410-sdi",
1805                 .data = (void *)0,
1806         },
1807         {
1808                 .compatible = "samsung,s3c2412-sdi",
1809                 .data = (void *)1,
1810         },
1811         {
1812                 .compatible = "samsung,s3c2440-sdi",
1813                 .data = (void *)1,
1814         },
1815         { /* sentinel */ },
1816 };
1817 MODULE_DEVICE_TABLE(of, s3cmci_dt_match);
1818
1819 static const struct platform_device_id s3cmci_driver_ids[] = {
1820         {
1821                 .name   = "s3c2410-sdi",
1822                 .driver_data    = 0,
1823         }, {
1824                 .name   = "s3c2412-sdi",
1825                 .driver_data    = 1,
1826         }, {
1827                 .name   = "s3c2440-sdi",
1828                 .driver_data    = 1,
1829         },
1830         { }
1831 };
1832
1833 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1834
1835 static struct platform_driver s3cmci_driver = {
1836         .driver = {
1837                 .name   = "s3c-sdi",
1838                 .of_match_table = s3cmci_dt_match,
1839         },
1840         .id_table       = s3cmci_driver_ids,
1841         .probe          = s3cmci_probe,
1842         .remove         = s3cmci_remove,
1843         .shutdown       = s3cmci_shutdown,
1844 };
1845
1846 module_platform_driver(s3cmci_driver);
1847
1848 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1849 MODULE_LICENSE("GPL v2");
1850 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");