drivers/mmc/host/s3cmci.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   4  *
   5  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   6  *
   7  * Current driver maintained by Ben Dooks and Simtec Electronics
   8  *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/clk.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/cpufreq.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/gpio.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/mmc/slot-gpio.h>
  27 #include <linux/platform_data/mmc-s3cmci.h>
  28
  29 #include "s3cmci.h"
  30
  31 #define DRIVER_NAME "s3c-mci"
  32
  33 #define S3C2410_SDICON                  (0x00)
  34 #define S3C2410_SDIPRE                  (0x04)
  35 #define S3C2410_SDICMDARG               (0x08)
  36 #define S3C2410_SDICMDCON               (0x0C)
  37 #define S3C2410_SDICMDSTAT              (0x10)
  38 #define S3C2410_SDIRSP0                 (0x14)
  39 #define S3C2410_SDIRSP1                 (0x18)
  40 #define S3C2410_SDIRSP2                 (0x1C)
  41 #define S3C2410_SDIRSP3                 (0x20)
  42 #define S3C2410_SDITIMER                (0x24)
  43 #define S3C2410_SDIBSIZE                (0x28)
  44 #define S3C2410_SDIDCON                 (0x2C)
  45 #define S3C2410_SDIDCNT                 (0x30)
  46 #define S3C2410_SDIDSTA                 (0x34)
  47 #define S3C2410_SDIFSTA                 (0x38)
  48
  49 #define S3C2410_SDIDATA                 (0x3C)
  50 #define S3C2410_SDIIMSK                 (0x40)
  51
  52 #define S3C2440_SDIDATA                 (0x40)
  53 #define S3C2440_SDIIMSK                 (0x3C)
  54
  55 #define S3C2440_SDICON_SDRESET          (1 << 8)
  56 #define S3C2410_SDICON_SDIOIRQ          (1 << 3)
  57 #define S3C2410_SDICON_FIFORESET        (1 << 1)
  58 #define S3C2410_SDICON_CLOCKTYPE        (1 << 0)
  59
  60 #define S3C2410_SDICMDCON_LONGRSP       (1 << 10)
  61 #define S3C2410_SDICMDCON_WAITRSP       (1 << 9)
  62 #define S3C2410_SDICMDCON_CMDSTART      (1 << 8)
  63 #define S3C2410_SDICMDCON_SENDERHOST    (1 << 6)
  64 #define S3C2410_SDICMDCON_INDEX         (0x3f)
  65
  66 #define S3C2410_SDICMDSTAT_CRCFAIL      (1 << 12)
  67 #define S3C2410_SDICMDSTAT_CMDSENT      (1 << 11)
  68 #define S3C2410_SDICMDSTAT_CMDTIMEOUT   (1 << 10)
  69 #define S3C2410_SDICMDSTAT_RSPFIN       (1 << 9)
  70
  71 #define S3C2440_SDIDCON_DS_WORD         (2 << 22)
  72 #define S3C2410_SDIDCON_TXAFTERRESP     (1 << 20)
  73 #define S3C2410_SDIDCON_RXAFTERCMD      (1 << 19)
  74 #define S3C2410_SDIDCON_BLOCKMODE       (1 << 17)
  75 #define S3C2410_SDIDCON_WIDEBUS         (1 << 16)
  76 #define S3C2410_SDIDCON_DMAEN           (1 << 15)
  77 #define S3C2410_SDIDCON_STOP            (1 << 14)
  78 #define S3C2440_SDIDCON_DATSTART        (1 << 14)
  79
  80 #define S3C2410_SDIDCON_XFER_RXSTART    (2 << 12)
  81 #define S3C2410_SDIDCON_XFER_TXSTART    (3 << 12)
  82
  83 #define S3C2410_SDIDCON_BLKNUM_MASK     (0xFFF)
  84
  85 #define S3C2410_SDIDSTA_SDIOIRQDETECT   (1 << 9)
  86 #define S3C2410_SDIDSTA_FIFOFAIL        (1 << 8)
  87 #define S3C2410_SDIDSTA_CRCFAIL         (1 << 7)
  88 #define S3C2410_SDIDSTA_RXCRCFAIL       (1 << 6)
  89 #define S3C2410_SDIDSTA_DATATIMEOUT     (1 << 5)
  90 #define S3C2410_SDIDSTA_XFERFINISH      (1 << 4)
  91 #define S3C2410_SDIDSTA_TXDATAON        (1 << 1)
  92 #define S3C2410_SDIDSTA_RXDATAON        (1 << 0)
  93
  94 #define S3C2440_SDIFSTA_FIFORESET       (1 << 16)
  95 #define S3C2440_SDIFSTA_FIFOFAIL        (3 << 14)
  96 #define S3C2410_SDIFSTA_TFDET           (1 << 13)
  97 #define S3C2410_SDIFSTA_RFDET           (1 << 12)
  98 #define S3C2410_SDIFSTA_COUNTMASK       (0x7f)
  99
 100 #define S3C2410_SDIIMSK_RESPONSECRC     (1 << 17)
 101 #define S3C2410_SDIIMSK_CMDSENT         (1 << 16)
 102 #define S3C2410_SDIIMSK_CMDTIMEOUT      (1 << 15)
 103 #define S3C2410_SDIIMSK_RESPONSEND      (1 << 14)
 104 #define S3C2410_SDIIMSK_SDIOIRQ         (1 << 12)
 105 #define S3C2410_SDIIMSK_FIFOFAIL        (1 << 11)
 106 #define S3C2410_SDIIMSK_CRCSTATUS       (1 << 10)
 107 #define S3C2410_SDIIMSK_DATACRC         (1 << 9)
 108 #define S3C2410_SDIIMSK_DATATIMEOUT     (1 << 8)
 109 #define S3C2410_SDIIMSK_DATAFINISH      (1 << 7)
 110 #define S3C2410_SDIIMSK_TXFIFOHALF      (1 << 4)
 111 #define S3C2410_SDIIMSK_RXFIFOLAST      (1 << 2)
 112 #define S3C2410_SDIIMSK_RXFIFOHALF      (1 << 0)
 113
 114 enum dbg_channels {
 115         dbg_err   = (1 << 0),
 116         dbg_debug = (1 << 1),
 117         dbg_info  = (1 << 2),
 118         dbg_irq   = (1 << 3),
 119         dbg_sg    = (1 << 4),
 120         dbg_dma   = (1 << 5),
 121         dbg_pio   = (1 << 6),
 122         dbg_fail  = (1 << 7),
 123         dbg_conf  = (1 << 8),
 124 };
 125
 126 static const int dbgmap_err   = dbg_fail;
 127 static const int dbgmap_info  = dbg_info | dbg_conf;
 128 static const int dbgmap_debug = dbg_err | dbg_debug;
 129
 130 #define dbg(host, channels, args...)              \
 131         do {                                      \
 132         if (dbgmap_err & channels)                \
 133                 dev_err(&host->pdev->dev, args);  \
 134         else if (dbgmap_info & channels)          \
 135                 dev_info(&host->pdev->dev, args); \
 136         else if (dbgmap_debug & channels)         \
 137                 dev_dbg(&host->pdev->dev, args);  \
 138         } while (0)
 139
 140 static void finalize_request(struct s3cmci_host *host);
 141 static void s3cmci_send_request(struct mmc_host *mmc);
 142 static void s3cmci_reset(struct s3cmci_host *host);
 143
 144 #ifdef CONFIG_MMC_DEBUG
 145
 146 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
 147 {
 148         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
 149         u32 datcon, datcnt, datsta, fsta, imask;
 150
 151         con     = readl(host->base + S3C2410_SDICON);
 152         pre     = readl(host->base + S3C2410_SDIPRE);
 153         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
 154         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
 155         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
 156         r0      = readl(host->base + S3C2410_SDIRSP0);
 157         r1      = readl(host->base + S3C2410_SDIRSP1);
 158         r2      = readl(host->base + S3C2410_SDIRSP2);
 159         r3      = readl(host->base + S3C2410_SDIRSP3);
 160         timer   = readl(host->base + S3C2410_SDITIMER);
 161         bsize   = readl(host->base + S3C2410_SDIBSIZE);
 162         datcon  = readl(host->base + S3C2410_SDIDCON);
 163         datcnt  = readl(host->base + S3C2410_SDIDCNT);
 164         datsta  = readl(host->base + S3C2410_SDIDSTA);
 165         fsta    = readl(host->base + S3C2410_SDIFSTA);
 166         imask   = readl(host->base + host->sdiimsk);
 167
 168         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
 169                                 prefix, con, pre, timer);
 170
 171         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
 172                                 prefix, cmdcon, cmdarg, cmdsta);
 173
 174         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
 175                                " DSTA:[%08x] DCNT:[%08x]\n",
 176                                 prefix, datcon, fsta, datsta, datcnt);
 177
 178         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 179                                "   R2:[%08x]   R3:[%08x]\n",
 180                                 prefix, r0, r1, r2, r3);
 181 }
 182
 183 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 184                            int stop)
 185 {
 186         snprintf(host->dbgmsg_cmd, 300,
 187                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 188                  host->ccnt, (stop ? " (STOP)" : ""),
 189                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 190
 191         if (cmd->data) {
 192                 snprintf(host->dbgmsg_dat, 300,
 193                          "#%u bsize:%u blocks:%u bytes:%u",
 194                          host->dcnt, cmd->data->blksz,
 195                          cmd->data->blocks,
 196                          cmd->data->blocks * cmd->data->blksz);
 197         } else {
 198                 host->dbgmsg_dat[0] = '\0';
 199         }
 200 }
 201
 202 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 203                         int fail)
 204 {
 205         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 206
 207         if (!cmd)
 208                 return;
 209
 210         if (cmd->error == 0) {
 211                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 212                         host->dbgmsg_cmd, cmd->resp[0]);
 213         } else {
 214                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 215                         cmd->error, host->dbgmsg_cmd, host->status);
 216         }
 217
 218         if (!cmd->data)
 219                 return;
 220
 221         if (cmd->data->error == 0) {
 222                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 223         } else {
 224                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 225                         cmd->data->error, host->dbgmsg_dat,
 226                         readl(host->base + S3C2410_SDIDCNT));
 227         }
 228 }
 229 #else
 230 static void dbg_dumpcmd(struct s3cmci_host *host,
 231                         struct mmc_command *cmd, int fail) { }
 232
 233 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 234                            int stop) { }
 235
 236 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 237
 238 #endif /* CONFIG_MMC_DEBUG */
 239
 240 /**
 241  * s3cmci_host_usedma - return whether the host is using dma or pio
 242  * @host: The host state
 243  *
 244  * Return true if the host is using DMA to transfer data, else false
 245  * to use PIO mode. Will return static data depending on the driver
 246  * configuration.
 247  */
 248 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
 249 {
 250 #ifdef CONFIG_MMC_S3C_PIO
 251         return false;
 252 #else /* CONFIG_MMC_S3C_DMA */
 253         return true;
 254 #endif
 255 }
 256
 257 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 258 {
 259         u32 newmask;
 260
 261         newmask = readl(host->base + host->sdiimsk);
 262         newmask |= imask;
 263
 264         writel(newmask, host->base + host->sdiimsk);
 265
 266         return newmask;
 267 }
 268
 269 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 270 {
 271         u32 newmask;
 272
 273         newmask = readl(host->base + host->sdiimsk);
 274         newmask &= ~imask;
 275
 276         writel(newmask, host->base + host->sdiimsk);
 277
 278         return newmask;
 279 }
 280
 281 static inline void clear_imask(struct s3cmci_host *host)
 282 {
 283         u32 mask = readl(host->base + host->sdiimsk);
 284
 285         /* preserve the SDIO IRQ mask state */
 286         mask &= S3C2410_SDIIMSK_SDIOIRQ;
 287         writel(mask, host->base + host->sdiimsk);
 288 }
 289
 290 /**
 291  * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
 292  * @host: The host to check.
 293  *
 294  * Test to see if the SDIO interrupt is being signalled in case the
 295  * controller has failed to re-detect a card interrupt. Read GPE8 and
 296  * see if it is low and if so, signal a SDIO interrupt.
 297  *
 298  * This is currently called if a request is finished (we assume that the
 299  * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
 300  * already being indicated.
 301 */
 302 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
 303 {
 304         if (host->sdio_irqen) {
 305                 if (host->pdata->bus[3] &&
 306                     gpiod_get_value(host->pdata->bus[3]) == 0) {
 307                         pr_debug("%s: signalling irq\n", __func__);
 308                         mmc_signal_sdio_irq(host->mmc);
 309                 }
 310         }
 311 }
 312
 313 static inline int get_data_buffer(struct s3cmci_host *host,
 314                                   u32 *bytes, u32 **pointer)
 315 {
 316         struct scatterlist *sg;
 317
 318         if (host->pio_active == XFER_NONE)
 319                 return -EINVAL;
 320
 321         if ((!host->mrq) || (!host->mrq->data))
 322                 return -EINVAL;
 323
 324         if (host->pio_sgptr >= host->mrq->data->sg_len) {
 325                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 326                       host->pio_sgptr, host->mrq->data->sg_len);
 327                 return -EBUSY;
 328         }
 329         sg = &host->mrq->data->sg[host->pio_sgptr];
 330
 331         *bytes = sg->length;
 332         *pointer = sg_virt(sg);
 333
 334         host->pio_sgptr++;
 335
 336         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 337             host->pio_sgptr, host->mrq->data->sg_len);
 338
 339         return 0;
 340 }
 341
 342 static inline u32 fifo_count(struct s3cmci_host *host)
 343 {
 344         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 345
 346         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 347         return fifostat;
 348 }
 349
 350 static inline u32 fifo_free(struct s3cmci_host *host)
 351 {
 352         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 353
 354         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 355         return 63 - fifostat;
 356 }
 357
 358 /**
 359  * s3cmci_enable_irq - enable IRQ, after having disabled it.
 360  * @host: The device state.
 361  * @more: True if more IRQs are expected from transfer.
 362  *
 363  * Enable the main IRQ if needed after it has been disabled.
 364  *
 365  * The IRQ can be one of the following states:
 366  *      - disabled during IDLE
 367  *      - disabled whilst processing data
 368  *      - enabled during transfer
 369  *      - enabled whilst awaiting SDIO interrupt detection
 370  */
 371 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
 372 {
 373         unsigned long flags;
 374         bool enable = false;
 375
 376         local_irq_save(flags);
 377
 378         host->irq_enabled = more;
 379         host->irq_disabled = false;
 380
 381         enable = more | host->sdio_irqen;
 382
 383         if (host->irq_state != enable) {
 384                 host->irq_state = enable;
 385
 386                 if (enable)
 387                         enable_irq(host->irq);
 388                 else
 389                         disable_irq(host->irq);
 390         }
 391
 392         local_irq_restore(flags);
 393 }
 394
 395 /**
 396  *
 397  */
 398 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
 399 {
 400         unsigned long flags;
 401
 402         local_irq_save(flags);
 403
 404         /* pr_debug("%s: transfer %d\n", __func__, transfer); */
 405
 406         host->irq_disabled = transfer;
 407
 408         if (transfer && host->irq_state) {
 409                 host->irq_state = false;
 410                 disable_irq(host->irq);
 411         }
 412
 413         local_irq_restore(flags);
 414 }
 415
 416 static void do_pio_read(struct s3cmci_host *host)
 417 {
 418         int res;
 419         u32 fifo;
 420         u32 *ptr;
 421         u32 fifo_words;
 422         void __iomem *from_ptr;
 423
 424         /* write real prescaler to host, it might be set slow to fix */
 425         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 426
 427         from_ptr = host->base + host->sdidata;
 428
 429         while ((fifo = fifo_count(host))) {
 430                 if (!host->pio_bytes) {
 431                         res = get_data_buffer(host, &host->pio_bytes,
 432                                               &host->pio_ptr);
 433                         if (res) {
 434                                 host->pio_active = XFER_NONE;
 435                                 host->complete_what = COMPLETION_FINALIZE;
 436
 437                                 dbg(host, dbg_pio, "pio_read(): "
 438                                     "complete (no more data).\n");
 439                                 return;
 440                         }
 441
 442                         dbg(host, dbg_pio,
 443                             "pio_read(): new target: [%i]@[%p]\n",
 444                             host->pio_bytes, host->pio_ptr);
 445                 }
 446
 447                 dbg(host, dbg_pio,
 448                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 449                     fifo, host->pio_bytes,
 450                     readl(host->base + S3C2410_SDIDCNT));
 451
 452                 /* If we have reached the end of the block, we can
 453                  * read a word and get 1 to 3 bytes.  If we in the
 454                  * middle of the block, we have to read full words,
 455                  * otherwise we will write garbage, so round down to
 456                  * an even multiple of 4. */
 457                 if (fifo >= host->pio_bytes)
 458                         fifo = host->pio_bytes;
 459                 else
 460                         fifo -= fifo & 3;
 461
 462                 host->pio_bytes -= fifo;
 463                 host->pio_count += fifo;
 464
 465                 fifo_words = fifo >> 2;
 466                 ptr = host->pio_ptr;
 467                 while (fifo_words--)
 468                         *ptr++ = readl(from_ptr);
 469                 host->pio_ptr = ptr;
 470
 471                 if (fifo & 3) {
 472                         u32 n = fifo & 3;
 473                         u32 data = readl(from_ptr);
 474                         u8 *p = (u8 *)host->pio_ptr;
 475
 476                         while (n--) {
 477                                 *p++ = data;
 478                                 data >>= 8;
 479                         }
 480                 }
 481         }
 482
 483         if (!host->pio_bytes) {
 484                 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
 485                 if (res) {
 486                         dbg(host, dbg_pio,
 487                             "pio_read(): complete (no more buffers).\n");
 488                         host->pio_active = XFER_NONE;
 489                         host->complete_what = COMPLETION_FINALIZE;
 490
 491                         return;
 492                 }
 493         }
 494
 495         enable_imask(host,
 496                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 497 }
 498
 499 static void do_pio_write(struct s3cmci_host *host)
 500 {
 501         void __iomem *to_ptr;
 502         int res;
 503         u32 fifo;
 504         u32 *ptr;
 505
 506         to_ptr = host->base + host->sdidata;
 507
 508         while ((fifo = fifo_free(host)) > 3) {
 509                 if (!host->pio_bytes) {
 510                         res = get_data_buffer(host, &host->pio_bytes,
 511                                                         &host->pio_ptr);
 512                         if (res) {
 513                                 dbg(host, dbg_pio,
 514                                     "pio_write(): complete (no more data).\n");
 515                                 host->pio_active = XFER_NONE;
 516
 517                                 return;
 518                         }
 519
 520                         dbg(host, dbg_pio,
 521                             "pio_write(): new source: [%i]@[%p]\n",
 522                             host->pio_bytes, host->pio_ptr);
 523
 524                 }
 525
 526                 /* If we have reached the end of the block, we have to
 527                  * write exactly the remaining number of bytes.  If we
 528                  * in the middle of the block, we have to write full
 529                  * words, so round down to an even multiple of 4. */
 530                 if (fifo >= host->pio_bytes)
 531                         fifo = host->pio_bytes;
 532                 else
 533                         fifo -= fifo & 3;
 534
 535                 host->pio_bytes -= fifo;
 536                 host->pio_count += fifo;
 537
 538                 fifo = (fifo + 3) >> 2;
 539                 ptr = host->pio_ptr;
 540                 while (fifo--)
 541                         writel(*ptr++, to_ptr);
 542                 host->pio_ptr = ptr;
 543         }
 544
 545         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 546 }
 547
 548 static void pio_tasklet(unsigned long data)
 549 {
 550         struct s3cmci_host *host = (struct s3cmci_host *) data;
 551
 552         s3cmci_disable_irq(host, true);
 553
 554         if (host->pio_active == XFER_WRITE)
 555                 do_pio_write(host);
 556
 557         if (host->pio_active == XFER_READ)
 558                 do_pio_read(host);
 559
 560         if (host->complete_what == COMPLETION_FINALIZE) {
 561                 clear_imask(host);
 562                 if (host->pio_active != XFER_NONE) {
 563                         dbg(host, dbg_err, "unfinished %s "
 564                             "- pio_count:[%u] pio_bytes:[%u]\n",
 565                             (host->pio_active == XFER_READ) ? "read" : "write",
 566                             host->pio_count, host->pio_bytes);
 567
 568                         if (host->mrq->data)
 569                                 host->mrq->data->error = -EINVAL;
 570                 }
 571
 572                 s3cmci_enable_irq(host, false);
 573                 finalize_request(host);
 574         } else
 575                 s3cmci_enable_irq(host, true);
 576 }
 577
 578 /*
 579  * ISR for SDI Interface IRQ
 580  * Communication between driver and ISR works as follows:
 581  *   host->mrq                  points to current request
 582  *   host->complete_what        Indicates when the request is considered done
 583  *     COMPLETION_CMDSENT         when the command was sent
 584  *     COMPLETION_RSPFIN          when a response was received
 585  *     COMPLETION_XFERFINISH      when the data transfer is finished
 586  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 587  *   host->complete_request     is the completion-object the driver waits for
 588  *
 589  * 1) Driver sets up host->mrq and host->complete_what
 590  * 2) Driver prepares the transfer
 591  * 3) Driver enables interrupts
 592  * 4) Driver starts transfer
 593  * 5) Driver waits for host->complete_rquest
 594  * 6) ISR checks for request status (errors and success)
 595  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 596  * 7) ISR completes host->complete_request
 597  * 8) ISR disables interrupts
 598  * 9) Driver wakes up and takes care of the request
 599  *
 600  * Note: "->error"-fields are expected to be set to 0 before the request
 601  *       was issued by mmc.c - therefore they are only set, when an error
 602  *       contition comes up
 603  */
 604
 605 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 606 {
 607         struct s3cmci_host *host = dev_id;
 608         struct mmc_command *cmd;
 609         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 610         u32 mci_cclear = 0, mci_dclear;
 611         unsigned long iflags;
 612
 613         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 614         mci_imsk = readl(host->base + host->sdiimsk);
 615
 616         if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
 617                 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
 618                         mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
 619                         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 620
 621                         mmc_signal_sdio_irq(host->mmc);
 622                         return IRQ_HANDLED;
 623                 }
 624         }
 625
 626         spin_lock_irqsave(&host->complete_lock, iflags);
 627
 628         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 629         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 630         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 631         mci_dclear = 0;
 632
 633         if ((host->complete_what == COMPLETION_NONE) ||
 634             (host->complete_what == COMPLETION_FINALIZE)) {
 635                 host->status = "nothing to complete";
 636                 clear_imask(host);
 637                 goto irq_out;
 638         }
 639
 640         if (!host->mrq) {
 641                 host->status = "no active mrq";
 642                 clear_imask(host);
 643                 goto irq_out;
 644         }
 645
 646         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 647
 648         if (!cmd) {
 649                 host->status = "no active cmd";
 650                 clear_imask(host);
 651                 goto irq_out;
 652         }
 653
 654         if (!s3cmci_host_usedma(host)) {
 655                 if ((host->pio_active == XFER_WRITE) &&
 656                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 657
 658                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 659                         tasklet_schedule(&host->pio_tasklet);
 660                         host->status = "pio tx";
 661                 }
 662
 663                 if ((host->pio_active == XFER_READ) &&
 664                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 665
 666                         disable_imask(host,
 667                                       S3C2410_SDIIMSK_RXFIFOHALF |
 668                                       S3C2410_SDIIMSK_RXFIFOLAST);
 669
 670                         tasklet_schedule(&host->pio_tasklet);
 671                         host->status = "pio rx";
 672                 }
 673         }
 674
 675         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 676                 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
 677                 cmd->error = -ETIMEDOUT;
 678                 host->status = "error: command timeout";
 679                 goto fail_transfer;
 680         }
 681
 682         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 683                 if (host->complete_what == COMPLETION_CMDSENT) {
 684                         host->status = "ok: command sent";
 685                         goto close_transfer;
 686                 }
 687
 688                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 689         }
 690
 691         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 692                 if (cmd->flags & MMC_RSP_CRC) {
 693                         if (host->mrq->cmd->flags & MMC_RSP_136) {
 694                                 dbg(host, dbg_irq,
 695                                     "fixup: ignore CRC fail with long rsp\n");
 696                         } else {
 697                                 /* note, we used to fail the transfer
 698                                  * here, but it seems that this is just
 699                                  * the hardware getting it wrong.
 700                                  *
 701                                  * cmd->error = -EILSEQ;
 702                                  * host->status = "error: bad command crc";
 703                                  * goto fail_transfer;
 704                                 */
 705                         }
 706                 }
 707
 708                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 709         }
 710
 711         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 712                 if (host->complete_what == COMPLETION_RSPFIN) {
 713                         host->status = "ok: command response received";
 714                         goto close_transfer;
 715                 }
 716
 717                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 718                         host->complete_what = COMPLETION_XFERFINISH;
 719
 720                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 721         }
 722
 723         /* errors handled after this point are only relevant
 724            when a data transfer is in progress */
 725
 726         if (!cmd->data)
 727                 goto clear_status_bits;
 728
 729         /* Check for FIFO failure */
 730         if (host->is2440) {
 731                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 732                         dbg(host, dbg_err, "FIFO failure\n");
 733                         host->mrq->data->error = -EILSEQ;
 734                         host->status = "error: 2440 fifo failure";
 735                         goto fail_transfer;
 736                 }
 737         } else {
 738                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 739                         dbg(host, dbg_err, "FIFO failure\n");
 740                         cmd->data->error = -EILSEQ;
 741                         host->status = "error:  fifo failure";
 742                         goto fail_transfer;
 743                 }
 744         }
 745
 746         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 747                 dbg(host, dbg_err, "bad data crc (outgoing)\n");
 748                 cmd->data->error = -EILSEQ;
 749                 host->status = "error: bad data crc (outgoing)";
 750                 goto fail_transfer;
 751         }
 752
 753         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 754                 dbg(host, dbg_err, "bad data crc (incoming)\n");
 755                 cmd->data->error = -EILSEQ;
 756                 host->status = "error: bad data crc (incoming)";
 757                 goto fail_transfer;
 758         }
 759
 760         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 761                 dbg(host, dbg_err, "data timeout\n");
 762                 cmd->data->error = -ETIMEDOUT;
 763                 host->status = "error: data timeout";
 764                 goto fail_transfer;
 765         }
 766
 767         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 768                 if (host->complete_what == COMPLETION_XFERFINISH) {
 769                         host->status = "ok: data transfer completed";
 770                         goto close_transfer;
 771                 }
 772
 773                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 774                         host->complete_what = COMPLETION_RSPFIN;
 775
 776                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 777         }
 778
 779 clear_status_bits:
 780         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 781         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 782
 783         goto irq_out;
 784
 785 fail_transfer:
 786         host->pio_active = XFER_NONE;
 787
 788 close_transfer:
 789         host->complete_what = COMPLETION_FINALIZE;
 790
 791         clear_imask(host);
 792         tasklet_schedule(&host->pio_tasklet);
 793
 794         goto irq_out;
 795
 796 irq_out:
 797         dbg(host, dbg_irq,
 798             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 799             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 800
 801         spin_unlock_irqrestore(&host->complete_lock, iflags);
 802         return IRQ_HANDLED;
 803
 804 }
 805
 806 static void s3cmci_dma_done_callback(void *arg)
 807 {
 808         struct s3cmci_host *host = arg;
 809         unsigned long iflags;
 810
 811         BUG_ON(!host->mrq);
 812         BUG_ON(!host->mrq->data);
 813
 814         spin_lock_irqsave(&host->complete_lock, iflags);
 815
 816         dbg(host, dbg_dma, "DMA FINISHED\n");
 817
 818         host->dma_complete = 1;
 819         host->complete_what = COMPLETION_FINALIZE;
 820
 821         tasklet_schedule(&host->pio_tasklet);
 822         spin_unlock_irqrestore(&host->complete_lock, iflags);
 823
 824 }
 825
 826 static void finalize_request(struct s3cmci_host *host)
 827 {
 828         struct mmc_request *mrq = host->mrq;
 829         struct mmc_command *cmd;
 830         int debug_as_failure = 0;
 831
 832         if (host->complete_what != COMPLETION_FINALIZE)
 833                 return;
 834
 835         if (!mrq)
 836                 return;
 837         cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 838
 839         if (cmd->data && (cmd->error == 0) &&
 840             (cmd->data->error == 0)) {
 841                 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
 842                         dbg(host, dbg_dma, "DMA Missing (%d)!\n",
 843                             host->dma_complete);
 844                         return;
 845                 }
 846         }
 847
 848         /* Read response from controller. */
 849         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 850         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 851         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 852         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 853
 854         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 855
 856         if (cmd->error)
 857                 debug_as_failure = 1;
 858
 859         if (cmd->data && cmd->data->error)
 860                 debug_as_failure = 1;
 861
 862         dbg_dumpcmd(host, cmd, debug_as_failure);
 863
 864         /* Cleanup controller */
 865         writel(0, host->base + S3C2410_SDICMDARG);
 866         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 867         writel(0, host->base + S3C2410_SDICMDCON);
 868         clear_imask(host);
 869
 870         if (cmd->data && cmd->error)
 871                 cmd->data->error = cmd->error;
 872
 873         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 874                 host->cmd_is_stop = 1;
 875                 s3cmci_send_request(host->mmc);
 876                 return;
 877         }
 878
 879         /* If we have no data transfer we are finished here */
 880         if (!mrq->data)
 881                 goto request_done;
 882
 883         /* Calculate the amout of bytes transfer if there was no error */
 884         if (mrq->data->error == 0) {
 885                 mrq->data->bytes_xfered =
 886                         (mrq->data->blocks * mrq->data->blksz);
 887         } else {
 888                 mrq->data->bytes_xfered = 0;
 889         }
 890
 891         /* If we had an error while transferring data we flush the
 892          * DMA channel and the fifo to clear out any garbage. */
 893         if (mrq->data->error != 0) {
 894                 if (s3cmci_host_usedma(host))
 895                         dmaengine_terminate_all(host->dma);
 896
 897                 if (host->is2440) {
 898                         /* Clear failure register and reset fifo. */
 899                         writel(S3C2440_SDIFSTA_FIFORESET |
 900                                S3C2440_SDIFSTA_FIFOFAIL,
 901                                host->base + S3C2410_SDIFSTA);
 902                 } else {
 903                         u32 mci_con;
 904
 905                         /* reset fifo */
 906                         mci_con = readl(host->base + S3C2410_SDICON);
 907                         mci_con |= S3C2410_SDICON_FIFORESET;
 908
 909                         writel(mci_con, host->base + S3C2410_SDICON);
 910                 }
 911         }
 912
 913 request_done:
 914         host->complete_what = COMPLETION_NONE;
 915         host->mrq = NULL;
 916
 917         s3cmci_check_sdio_irq(host);
 918         mmc_request_done(host->mmc, mrq);
 919 }
 920
 921 static void s3cmci_send_command(struct s3cmci_host *host,
 922                                         struct mmc_command *cmd)
 923 {
 924         u32 ccon, imsk;
 925
 926         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
 927                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
 928                 S3C2410_SDIIMSK_RESPONSECRC;
 929
 930         enable_imask(host, imsk);
 931
 932         if (cmd->data)
 933                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
 934         else if (cmd->flags & MMC_RSP_PRESENT)
 935                 host->complete_what = COMPLETION_RSPFIN;
 936         else
 937                 host->complete_what = COMPLETION_CMDSENT;
 938
 939         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
 940
 941         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
 942         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
 943
 944         if (cmd->flags & MMC_RSP_PRESENT)
 945                 ccon |= S3C2410_SDICMDCON_WAITRSP;
 946
 947         if (cmd->flags & MMC_RSP_136)
 948                 ccon |= S3C2410_SDICMDCON_LONGRSP;
 949
 950         writel(ccon, host->base + S3C2410_SDICMDCON);
 951 }
 952
 953 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
 954 {
 955         u32 dcon, imsk, stoptries = 3;
 956
 957         if ((data->blksz & 3) != 0) {
 958                 /* We cannot deal with unaligned blocks with more than
 959                  * one block being transferred. */
 960
 961                 if (data->blocks > 1) {
 962                         pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
 963                                 __func__, data->blksz);
 964                         return -EINVAL;
 965                 }
 966         }
 967
 968         while (readl(host->base + S3C2410_SDIDSTA) &
 969                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
 970
 971                 dbg(host, dbg_err,
 972                     "mci_setup_data() transfer stillin progress.\n");
 973
 974                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 975                 s3cmci_reset(host);
 976
 977                 if ((stoptries--) == 0) {
 978                         dbg_dumpregs(host, "DRF");
 979                         return -EINVAL;
 980                 }
 981         }
 982
 983         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
 984
 985         if (s3cmci_host_usedma(host))
 986                 dcon |= S3C2410_SDIDCON_DMAEN;
 987
 988         if (host->bus_width == MMC_BUS_WIDTH_4)
 989                 dcon |= S3C2410_SDIDCON_WIDEBUS;
 990
 991         dcon |= S3C2410_SDIDCON_BLOCKMODE;
 992
 993         if (data->flags & MMC_DATA_WRITE) {
 994                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
 995                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
 996         }
 997
 998         if (data->flags & MMC_DATA_READ) {
 999                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1000                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1001         }
1002
1003         if (host->is2440) {
1004                 dcon |= S3C2440_SDIDCON_DS_WORD;
1005                 dcon |= S3C2440_SDIDCON_DATSTART;
1006         }
1007
1008         writel(dcon, host->base + S3C2410_SDIDCON);
1009
1010         /* write BSIZE register */
1011
1012         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1013
1014         /* add to IMASK register */
1015         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1016                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1017
1018         enable_imask(host, imsk);
1019
1020         /* write TIMER register */
1021
1022         if (host->is2440) {
1023                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1024         } else {
1025                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1026
1027                 /* FIX: set slow clock to prevent timeouts on read */
1028                 if (data->flags & MMC_DATA_READ)
1029                         writel(0xFF, host->base + S3C2410_SDIPRE);
1030         }
1031
1032         return 0;
1033 }
1034
1035 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1036
1037 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1038 {
1039         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1040
1041         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1042
1043         host->pio_sgptr = 0;
1044         host->pio_bytes = 0;
1045         host->pio_count = 0;
1046         host->pio_active = rw ? XFER_WRITE : XFER_READ;
1047
1048         if (rw) {
1049                 do_pio_write(host);
1050                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1051         } else {
1052                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1053                              | S3C2410_SDIIMSK_RXFIFOLAST);
1054         }
1055
1056         return 0;
1057 }
1058
1059 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1060 {
1061         int rw = data->flags & MMC_DATA_WRITE;
1062         struct dma_async_tx_descriptor *desc;
1063         struct dma_slave_config conf = {
1064                 .src_addr = host->mem->start + host->sdidata,
1065                 .dst_addr = host->mem->start + host->sdidata,
1066                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1067                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1068         };
1069
1070         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1071
1072         /* Restore prescaler value */
1073         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1074
1075         if (!rw)
1076                 conf.direction = DMA_DEV_TO_MEM;
1077         else
1078                 conf.direction = DMA_MEM_TO_DEV;
1079
1080         dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1081                    mmc_get_dma_dir(data));
1082
1083         dmaengine_slave_config(host->dma, &conf);
1084         desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1085                 conf.direction,
1086                 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1087         if (!desc)
1088                 goto unmap_exit;
1089         desc->callback = s3cmci_dma_done_callback;
1090         desc->callback_param = host;
1091         dmaengine_submit(desc);
1092         dma_async_issue_pending(host->dma);
1093
1094         return 0;
1095
1096 unmap_exit:
1097         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1098                      mmc_get_dma_dir(data));
1099         return -ENOMEM;
1100 }
1101
1102 static void s3cmci_send_request(struct mmc_host *mmc)
1103 {
1104         struct s3cmci_host *host = mmc_priv(mmc);
1105         struct mmc_request *mrq = host->mrq;
1106         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1107
1108         host->ccnt++;
1109         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1110
1111         /* Clear command, data and fifo status registers
1112            Fifo clear only necessary on 2440, but doesn't hurt on 2410
1113         */
1114         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1115         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1116         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1117
1118         if (cmd->data) {
1119                 int res = s3cmci_setup_data(host, cmd->data);
1120
1121                 host->dcnt++;
1122
1123                 if (res) {
1124                         dbg(host, dbg_err, "setup data error %d\n", res);
1125                         cmd->error = res;
1126                         cmd->data->error = res;
1127
1128                         mmc_request_done(mmc, mrq);
1129                         return;
1130                 }
1131
1132                 if (s3cmci_host_usedma(host))
1133                         res = s3cmci_prepare_dma(host, cmd->data);
1134                 else
1135                         res = s3cmci_prepare_pio(host, cmd->data);
1136
1137                 if (res) {
1138                         dbg(host, dbg_err, "data prepare error %d\n", res);
1139                         cmd->error = res;
1140                         cmd->data->error = res;
1141
1142                         mmc_request_done(mmc, mrq);
1143                         return;
1144                 }
1145         }
1146
1147         /* Send command */
1148         s3cmci_send_command(host, cmd);
1149
1150         /* Enable Interrupt */
1151         s3cmci_enable_irq(host, true);
1152 }
1153
1154 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1155 {
1156         struct s3cmci_host *host = mmc_priv(mmc);
1157
1158         host->status = "mmc request";
1159         host->cmd_is_stop = 0;
1160         host->mrq = mrq;
1161
1162         if (mmc_gpio_get_cd(mmc) == 0) {
1163                 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1164                 host->mrq->cmd->error = -ENOMEDIUM;
1165                 mmc_request_done(mmc, mrq);
1166         } else
1167                 s3cmci_send_request(mmc);
1168 }
1169
1170 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1171 {
1172         u32 mci_psc;
1173
1174         /* Set clock */
1175         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1176                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1177
1178                 if (host->real_rate <= ios->clock)
1179                         break;
1180         }
1181
1182         if (mci_psc > 255)
1183                 mci_psc = 255;
1184
1185         host->prescaler = mci_psc;
1186         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1187
1188         /* If requested clock is 0, real_rate will be 0, too */
1189         if (ios->clock == 0)
1190                 host->real_rate = 0;
1191 }
1192
1193 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1194 {
1195         struct s3cmci_host *host = mmc_priv(mmc);
1196         u32 mci_con;
1197
1198         /* Set the power state */
1199
1200         mci_con = readl(host->base + S3C2410_SDICON);
1201
1202         switch (ios->power_mode) {
1203         case MMC_POWER_ON:
1204         case MMC_POWER_UP:
1205                 if (!host->is2440)
1206                         mci_con |= S3C2410_SDICON_FIFORESET;
1207                 break;
1208
1209         case MMC_POWER_OFF:
1210         default:
1211                 if (host->is2440)
1212                         mci_con |= S3C2440_SDICON_SDRESET;
1213                 break;
1214         }
1215
1216         if (host->pdata->set_power)
1217                 host->pdata->set_power(ios->power_mode, ios->vdd);
1218
1219         s3cmci_set_clk(host, ios);
1220
1221         /* Set CLOCK_ENABLE */
1222         if (ios->clock)
1223                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1224         else
1225                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1226
1227         writel(mci_con, host->base + S3C2410_SDICON);
1228
1229         if ((ios->power_mode == MMC_POWER_ON) ||
1230             (ios->power_mode == MMC_POWER_UP)) {
1231                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1232                         host->real_rate/1000, ios->clock/1000);
1233         } else {
1234                 dbg(host, dbg_conf, "powered down.\n");
1235         }
1236
1237         host->bus_width = ios->bus_width;
1238 }
1239
1240 static void s3cmci_reset(struct s3cmci_host *host)
1241 {
1242         u32 con = readl(host->base + S3C2410_SDICON);
1243
1244         con |= S3C2440_SDICON_SDRESET;
1245         writel(con, host->base + S3C2410_SDICON);
1246 }
1247
1248 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1249 {
1250         struct s3cmci_host *host = mmc_priv(mmc);
1251         unsigned long flags;
1252         u32 con;
1253
1254         local_irq_save(flags);
1255
1256         con = readl(host->base + S3C2410_SDICON);
1257         host->sdio_irqen = enable;
1258
1259         if (enable == host->sdio_irqen)
1260                 goto same_state;
1261
1262         if (enable) {
1263                 con |= S3C2410_SDICON_SDIOIRQ;
1264                 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1265
1266                 if (!host->irq_state && !host->irq_disabled) {
1267                         host->irq_state = true;
1268                         enable_irq(host->irq);
1269                 }
1270         } else {
1271                 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1272                 con &= ~S3C2410_SDICON_SDIOIRQ;
1273
1274                 if (!host->irq_enabled && host->irq_state) {
1275                         disable_irq_nosync(host->irq);
1276                         host->irq_state = false;
1277                 }
1278         }
1279
1280         writel(con, host->base + S3C2410_SDICON);
1281
1282  same_state:
1283         local_irq_restore(flags);
1284
1285         s3cmci_check_sdio_irq(host);
1286 }
1287
1288 static const struct mmc_host_ops s3cmci_ops = {
1289         .request        = s3cmci_request,
1290         .set_ios        = s3cmci_set_ios,
1291         .get_ro         = mmc_gpio_get_ro,
1292         .get_cd         = mmc_gpio_get_cd,
1293         .enable_sdio_irq = s3cmci_enable_sdio_irq,
1294 };
1295
1296 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1297
1298 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1299                                      unsigned long val, void *data)
1300 {
1301         struct s3cmci_host *host;
1302         struct mmc_host *mmc;
1303         unsigned long newclk;
1304         unsigned long flags;
1305
1306         host = container_of(nb, struct s3cmci_host, freq_transition);
1307         newclk = clk_get_rate(host->clk);
1308         mmc = host->mmc;
1309
1310         if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1311             (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1312                 spin_lock_irqsave(&mmc->lock, flags);
1313
1314                 host->clk_rate = newclk;
1315
1316                 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1317                     mmc->ios.clock != 0)
1318                         s3cmci_set_clk(host, &mmc->ios);
1319
1320                 spin_unlock_irqrestore(&mmc->lock, flags);
1321         }
1322
1323         return 0;
1324 }
1325
1326 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1327 {
1328         host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1329
1330         return cpufreq_register_notifier(&host->freq_transition,
1331                                          CPUFREQ_TRANSITION_NOTIFIER);
1332 }
1333
1334 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1335 {
1336         cpufreq_unregister_notifier(&host->freq_transition,
1337                                     CPUFREQ_TRANSITION_NOTIFIER);
1338 }
1339
1340 #else
1341 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1342 {
1343         return 0;
1344 }
1345
1346 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1347 {
1348 }
1349 #endif
1350
1351
1352 #ifdef CONFIG_DEBUG_FS
1353
1354 static int s3cmci_state_show(struct seq_file *seq, void *v)
1355 {
1356         struct s3cmci_host *host = seq->private;
1357
1358         seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1359         seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1360         seq_printf(seq, "Prescale = %d\n", host->prescaler);
1361         seq_printf(seq, "is2440 = %d\n", host->is2440);
1362         seq_printf(seq, "IRQ = %d\n", host->irq);
1363         seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1364         seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1365         seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1366         seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1367         seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1368         seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1369         seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1370
1371         return 0;
1372 }
1373
1374 DEFINE_SHOW_ATTRIBUTE(s3cmci_state);
1375
1376 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1377
1378 struct s3cmci_reg {
1379         unsigned short  addr;
1380         unsigned char   *name;
1381 };
1382
1383 static const struct s3cmci_reg debug_regs[] = {
1384         DBG_REG(CON),
1385         DBG_REG(PRE),
1386         DBG_REG(CMDARG),
1387         DBG_REG(CMDCON),
1388         DBG_REG(CMDSTAT),
1389         DBG_REG(RSP0),
1390         DBG_REG(RSP1),
1391         DBG_REG(RSP2),
1392         DBG_REG(RSP3),
1393         DBG_REG(TIMER),
1394         DBG_REG(BSIZE),
1395         DBG_REG(DCON),
1396         DBG_REG(DCNT),
1397         DBG_REG(DSTA),
1398         DBG_REG(FSTA),
1399         {}
1400 };
1401
1402 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1403 {
1404         struct s3cmci_host *host = seq->private;
1405         const struct s3cmci_reg *rptr = debug_regs;
1406
1407         for (; rptr->name; rptr++)
1408                 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1409                            readl(host->base + rptr->addr));
1410
1411         seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1412
1413         return 0;
1414 }
1415
1416 DEFINE_SHOW_ATTRIBUTE(s3cmci_regs);
1417
1418 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1419 {
1420         struct device *dev = &host->pdev->dev;
1421         struct dentry *root;
1422
1423         root = debugfs_create_dir(dev_name(dev), NULL);
1424         host->debug_root = root;
1425
1426         debugfs_create_file("state", 0444, root, host, &s3cmci_state_fops);
1427         debugfs_create_file("regs", 0444, root, host, &s3cmci_regs_fops);
1428 }
1429
1430 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1431 {
1432         debugfs_remove_recursive(host->debug_root);
1433 }
1434
1435 #else
1436 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1437 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1438
1439 #endif /* CONFIG_DEBUG_FS */
1440
1441 static int s3cmci_probe_pdata(struct s3cmci_host *host)
1442 {
1443         struct platform_device *pdev = host->pdev;
1444         struct mmc_host *mmc = host->mmc;
1445         struct s3c24xx_mci_pdata *pdata;
1446         int i, ret;
1447
1448         host->is2440 = platform_get_device_id(pdev)->driver_data;
1449         pdata = pdev->dev.platform_data;
1450         if (!pdata) {
1451                 dev_err(&pdev->dev, "need platform data");
1452                 return -ENXIO;
1453         }
1454
1455         for (i = 0; i < 6; i++) {
1456                 pdata->bus[i] = devm_gpiod_get_index(&pdev->dev, "bus", i,
1457                                                      GPIOD_OUT_LOW);
1458                 if (IS_ERR(pdata->bus[i])) {
1459                         dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1460                         return PTR_ERR(pdata->bus[i]);
1461                 }
1462         }
1463
1464         if (pdata->no_wprotect)
1465                 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1466
1467         if (pdata->no_detect)
1468                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1469
1470         if (pdata->wprotect_invert)
1471                 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1472
1473         /* If we get -ENOENT we have no card detect GPIO line */
1474         ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
1475         if (ret != -ENOENT) {
1476                 dev_err(&pdev->dev, "error requesting GPIO for CD %d\n",
1477                         ret);
1478                 return ret;
1479         }
1480
1481         ret = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
1482         if (ret != -ENOENT) {
1483                 dev_err(&pdev->dev, "error requesting GPIO for WP %d\n",
1484                         ret);
1485                 return ret;
1486         }
1487
1488         return 0;
1489 }
1490
1491 static int s3cmci_probe_dt(struct s3cmci_host *host)
1492 {
1493         struct platform_device *pdev = host->pdev;
1494         struct s3c24xx_mci_pdata *pdata;
1495         struct mmc_host *mmc = host->mmc;
1496         int ret;
1497
1498         host->is2440 = (int) of_device_get_match_data(&pdev->dev);
1499
1500         ret = mmc_of_parse(mmc);
1501         if (ret)
1502                 return ret;
1503
1504         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1505         if (!pdata)
1506                 return -ENOMEM;
1507
1508         pdev->dev.platform_data = pdata;
1509
1510         return 0;
1511 }
1512
1513 static int s3cmci_probe(struct platform_device *pdev)
1514 {
1515         struct s3cmci_host *host;
1516         struct mmc_host *mmc;
1517         int ret;
1518
1519         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1520         if (!mmc) {
1521                 ret = -ENOMEM;
1522                 goto probe_out;
1523         }
1524
1525         host = mmc_priv(mmc);
1526         host->mmc       = mmc;
1527         host->pdev      = pdev;
1528
1529         if (pdev->dev.of_node)
1530                 ret = s3cmci_probe_dt(host);
1531         else
1532                 ret = s3cmci_probe_pdata(host);
1533
1534         if (ret)
1535                 goto probe_free_host;
1536
1537         host->pdata = pdev->dev.platform_data;
1538
1539         spin_lock_init(&host->complete_lock);
1540         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1541
1542         if (host->is2440) {
1543                 host->sdiimsk   = S3C2440_SDIIMSK;
1544                 host->sdidata   = S3C2440_SDIDATA;
1545                 host->clk_div   = 1;
1546         } else {
1547                 host->sdiimsk   = S3C2410_SDIIMSK;
1548                 host->sdidata   = S3C2410_SDIDATA;
1549                 host->clk_div   = 2;
1550         }
1551
1552         host->complete_what     = COMPLETION_NONE;
1553         host->pio_active        = XFER_NONE;
1554
1555         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1556         if (!host->mem) {
1557                 dev_err(&pdev->dev,
1558                         "failed to get io memory region resource.\n");
1559
1560                 ret = -ENOENT;
1561                 goto probe_free_host;
1562         }
1563
1564         host->mem = request_mem_region(host->mem->start,
1565                                        resource_size(host->mem), pdev->name);
1566
1567         if (!host->mem) {
1568                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1569                 ret = -ENOENT;
1570                 goto probe_free_host;
1571         }
1572
1573         host->base = ioremap(host->mem->start, resource_size(host->mem));
1574         if (!host->base) {
1575                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1576                 ret = -EINVAL;
1577                 goto probe_free_mem_region;
1578         }
1579
1580         host->irq = platform_get_irq(pdev, 0);
1581         if (host->irq <= 0) {
1582                 ret = -EINVAL;
1583                 goto probe_iounmap;
1584         }
1585
1586         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1587                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1588                 ret = -ENOENT;
1589                 goto probe_iounmap;
1590         }
1591
1592         /* We get spurious interrupts even when we have set the IMSK
1593          * register to ignore everything, so use disable_irq() to make
1594          * ensure we don't lock the system with un-serviceable requests. */
1595
1596         disable_irq(host->irq);
1597         host->irq_state = false;
1598
1599         /* Depending on the dma state, get a DMA channel to use. */
1600
1601         if (s3cmci_host_usedma(host)) {
1602                 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1603                 ret = PTR_ERR_OR_ZERO(host->dma);
1604                 if (ret) {
1605                         dev_err(&pdev->dev, "cannot get DMA channel.\n");
1606                         goto probe_free_irq;
1607                 }
1608         }
1609
1610         host->clk = clk_get(&pdev->dev, "sdi");
1611         if (IS_ERR(host->clk)) {
1612                 dev_err(&pdev->dev, "failed to find clock source.\n");
1613                 ret = PTR_ERR(host->clk);
1614                 host->clk = NULL;
1615                 goto probe_free_dma;
1616         }
1617
1618         ret = clk_prepare_enable(host->clk);
1619         if (ret) {
1620                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1621                 goto clk_free;
1622         }
1623
1624         host->clk_rate = clk_get_rate(host->clk);
1625
1626         mmc->ops        = &s3cmci_ops;
1627         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1628 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1629         mmc->caps       = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1630 #else
1631         mmc->caps       = MMC_CAP_4_BIT_DATA;
1632 #endif
1633         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1634         mmc->f_max      = host->clk_rate / host->clk_div;
1635
1636         if (host->pdata->ocr_avail)
1637                 mmc->ocr_avail = host->pdata->ocr_avail;
1638
1639         mmc->max_blk_count      = 4095;
1640         mmc->max_blk_size       = 4095;
1641         mmc->max_req_size       = 4095 * 512;
1642         mmc->max_seg_size       = mmc->max_req_size;
1643
1644         mmc->max_segs           = 128;
1645
1646         dbg(host, dbg_debug,
1647             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1648             (host->is2440?"2440":""),
1649             host->base, host->irq, host->irq_cd, host->dma);
1650
1651         ret = s3cmci_cpufreq_register(host);
1652         if (ret) {
1653                 dev_err(&pdev->dev, "failed to register cpufreq\n");
1654                 goto free_dmabuf;
1655         }
1656
1657         ret = mmc_add_host(mmc);
1658         if (ret) {
1659                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1660                 goto free_cpufreq;
1661         }
1662
1663         s3cmci_debugfs_attach(host);
1664
1665         platform_set_drvdata(pdev, mmc);
1666         dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1667                  s3cmci_host_usedma(host) ? "dma" : "pio",
1668                  mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1669
1670         return 0;
1671
1672  free_cpufreq:
1673         s3cmci_cpufreq_deregister(host);
1674
1675  free_dmabuf:
1676         clk_disable_unprepare(host->clk);
1677
1678  clk_free:
1679         clk_put(host->clk);
1680
1681  probe_free_dma:
1682         if (s3cmci_host_usedma(host))
1683                 dma_release_channel(host->dma);
1684
1685  probe_free_irq:
1686         free_irq(host->irq, host);
1687
1688  probe_iounmap:
1689         iounmap(host->base);
1690
1691  probe_free_mem_region:
1692         release_mem_region(host->mem->start, resource_size(host->mem));
1693
1694  probe_free_host:
1695         mmc_free_host(mmc);
1696
1697  probe_out:
1698         return ret;
1699 }
1700
1701 static void s3cmci_shutdown(struct platform_device *pdev)
1702 {
1703         struct mmc_host *mmc = platform_get_drvdata(pdev);
1704         struct s3cmci_host *host = mmc_priv(mmc);
1705
1706         if (host->irq_cd >= 0)
1707                 free_irq(host->irq_cd, host);
1708
1709         s3cmci_debugfs_remove(host);
1710         s3cmci_cpufreq_deregister(host);
1711         mmc_remove_host(mmc);
1712         clk_disable_unprepare(host->clk);
1713 }
1714
1715 static int s3cmci_remove(struct platform_device *pdev)
1716 {
1717         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1718         struct s3cmci_host      *host = mmc_priv(mmc);
1719
1720         s3cmci_shutdown(pdev);
1721
1722         clk_put(host->clk);
1723
1724         tasklet_disable(&host->pio_tasklet);
1725
1726         if (s3cmci_host_usedma(host))
1727                 dma_release_channel(host->dma);
1728
1729         free_irq(host->irq, host);
1730
1731         iounmap(host->base);
1732         release_mem_region(host->mem->start, resource_size(host->mem));
1733
1734         mmc_free_host(mmc);
1735         return 0;
1736 }
1737
1738 static const struct of_device_id s3cmci_dt_match[] = {
1739         {
1740                 .compatible = "samsung,s3c2410-sdi",
1741                 .data = (void *)0,
1742         },
1743         {
1744                 .compatible = "samsung,s3c2412-sdi",
1745                 .data = (void *)1,
1746         },
1747         {
1748                 .compatible = "samsung,s3c2440-sdi",
1749                 .data = (void *)1,
1750         },
1751         { /* sentinel */ },
1752 };
1753 MODULE_DEVICE_TABLE(of, s3cmci_dt_match);
1754
1755 static const struct platform_device_id s3cmci_driver_ids[] = {
1756         {
1757                 .name   = "s3c2410-sdi",
1758                 .driver_data    = 0,
1759         }, {
1760                 .name   = "s3c2412-sdi",
1761                 .driver_data    = 1,
1762         }, {
1763                 .name   = "s3c2440-sdi",
1764                 .driver_data    = 1,
1765         },
1766         { }
1767 };
1768
1769 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1770
1771 static struct platform_driver s3cmci_driver = {
1772         .driver = {
1773                 .name   = "s3c-sdi",
1774                 .of_match_table = s3cmci_dt_match,
1775         },
1776         .id_table       = s3cmci_driver_ids,
1777         .probe          = s3cmci_probe,
1778         .remove         = s3cmci_remove,
1779         .shutdown       = s3cmci_shutdown,
1780 };
1781
1782 module_platform_driver(s3cmci_driver);
1783
1784 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1785 MODULE_LICENSE("GPL v2");
1786 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");