drivers/mmc/host/renesas_sdhi_internal_dmac.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * DMA support for Internal DMAC with SDHI SD/SDIO controller
   4  *
   5  * Copyright (C) 2016-17 Renesas Electronics Corporation
   6  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   7  */
   8
   9 #include <linux/bitops.h>
  10 #include <linux/device.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/io-64-nonatomic-hi-lo.h>
  13 #include <linux/mfd/tmio.h>
  14 #include <linux/mmc/host.h>
  15 #include <linux/mod_devicetable.h>
  16 #include <linux/module.h>
  17 #include <linux/pagemap.h>
  18 #include <linux/scatterlist.h>
  19 #include <linux/sys_soc.h>
  20
  21 #include "renesas_sdhi.h"
  22 #include "tmio_mmc.h"
  23
  24 #define DM_CM_DTRAN_MODE        0x820
  25 #define DM_CM_DTRAN_CTRL        0x828
  26 #define DM_CM_RST               0x830
  27 #define DM_CM_INFO1             0x840
  28 #define DM_CM_INFO1_MASK        0x848
  29 #define DM_CM_INFO2             0x850
  30 #define DM_CM_INFO2_MASK        0x858
  31 #define DM_DTRAN_ADDR           0x880
  32
  33 /* DM_CM_DTRAN_MODE */
  34 #define DTRAN_MODE_CH_NUM_CH0   0       /* "downstream" = for write commands */
  35 #define DTRAN_MODE_CH_NUM_CH1   BIT(16) /* "upstream" = for read commands */
  36 #define DTRAN_MODE_BUS_WIDTH    (BIT(5) | BIT(4))
  37 #define DTRAN_MODE_ADDR_MODE    BIT(0)  /* 1 = Increment address, 0 = Fixed */
  38
  39 /* DM_CM_DTRAN_CTRL */
  40 #define DTRAN_CTRL_DM_START     BIT(0)
  41
  42 /* DM_CM_RST */
  43 #define RST_DTRANRST1           BIT(9)
  44 #define RST_DTRANRST0           BIT(8)
  45 #define RST_RESERVED_BITS       GENMASK_ULL(31, 0)
  46
  47 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
  48 #define INFO1_CLEAR             0
  49 #define INFO1_MASK_CLEAR        GENMASK_ULL(31, 0)
  50 #define INFO1_DTRANEND1         BIT(17)
  51 #define INFO1_DTRANEND0         BIT(16)
  52
  53 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
  54 #define INFO2_MASK_CLEAR        GENMASK_ULL(31, 0)
  55 #define INFO2_DTRANERR1         BIT(17)
  56 #define INFO2_DTRANERR0         BIT(16)
  57
  58 /*
  59  * Specification of this driver:
  60  * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
  61  * - Since this SDHI DMAC register set has 16 but 32-bit width, we
  62  *   need a custom accessor.
  63  */
  64
  65 static unsigned long global_flags;
  66 /*
  67  * Workaround for avoiding to use RX DMAC by multiple channels.
  68  * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
  69  * RX DMAC simultaneously, sometimes hundreds of bytes data are not
  70  * stored into the system memory even if the DMAC interrupt happened.
  71  * So, this driver then uses one RX DMAC channel only.
  72  */
  73 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY  0
  74 #define SDHI_INTERNAL_DMAC_RX_IN_USE    1
  75
  76 /* RZ/A2 does not have the ADRR_MODE bit */
  77 #define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2
  78
  79 /* Definitions for sampling clocks */
  80 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
  81         {
  82                 .clk_rate = 0,
  83                 .tap = 0x00000300,
  84                 .tap_hs400 = 0x00000704,
  85         },
  86 };
  87
  88 static const struct renesas_sdhi_of_data of_rza2_compatible = {
  89         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  90                           TMIO_MMC_HAVE_CBSY,
  91         .tmio_ocr_mask  = MMC_VDD_32_33,
  92         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  93                           MMC_CAP_CMD23,
  94         .bus_shift      = 2,
  95         .scc_offset     = 0 - 0x1000,
  96         .taps           = rcar_gen3_scc_taps,
  97         .taps_num       = ARRAY_SIZE(rcar_gen3_scc_taps),
  98         /* DMAC can handle 0xffffffff blk count but only 1 segment */
  99         .max_blk_count  = 0xffffffff,
 100         .max_segs       = 1,
 101 };
 102
 103 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
 104         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
 105                           TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
 106         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 107                           MMC_CAP_CMD23,
 108         .capabilities2  = MMC_CAP2_NO_WRITE_PROTECT,
 109         .bus_shift      = 2,
 110         .scc_offset     = 0x1000,
 111         .taps           = rcar_gen3_scc_taps,
 112         .taps_num       = ARRAY_SIZE(rcar_gen3_scc_taps),
 113         /* DMAC can handle 0xffffffff blk count but only 1 segment */
 114         .max_blk_count  = 0xffffffff,
 115         .max_segs       = 1,
 116 };
 117
 118 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
 119         { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, },
 120         { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
 121         { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
 122         { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
 123         { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
 124         {},
 125 };
 126 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
 127
 128 static void
 129 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
 130                                     int addr, u64 val)
 131 {
 132         writeq(val, host->ctl + addr);
 133 }
 134
 135 static void
 136 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
 137 {
 138         struct renesas_sdhi *priv = host_to_priv(host);
 139
 140         if (!host->chan_tx || !host->chan_rx)
 141                 return;
 142
 143         if (!enable)
 144                 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
 145                                                     INFO1_CLEAR);
 146
 147         if (priv->dma_priv.enable)
 148                 priv->dma_priv.enable(host, enable);
 149 }
 150
 151 static void
 152 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
 153         u64 val = RST_DTRANRST1 | RST_DTRANRST0;
 154
 155         renesas_sdhi_internal_dmac_enable_dma(host, false);
 156
 157         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
 158                                             RST_RESERVED_BITS & ~val);
 159         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
 160                                             RST_RESERVED_BITS | val);
 161
 162         clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
 163
 164         renesas_sdhi_internal_dmac_enable_dma(host, true);
 165 }
 166
 167 static void
 168 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
 169         struct renesas_sdhi *priv = host_to_priv(host);
 170
 171         tasklet_schedule(&priv->dma_priv.dma_complete);
 172 }
 173
 174 static void
 175 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
 176                                      struct mmc_data *data)
 177 {
 178         struct scatterlist *sg = host->sg_ptr;
 179         u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
 180
 181         if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, &global_flags))
 182                 dtran_mode |= DTRAN_MODE_ADDR_MODE;
 183
 184         if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len,
 185                         mmc_get_dma_dir(data)))
 186                 goto force_pio;
 187
 188         /* This DMAC cannot handle if buffer is not 8-bytes alignment */
 189         if (!IS_ALIGNED(sg_dma_address(sg), 8))
 190                 goto force_pio_with_unmap;
 191
 192         if (data->flags & MMC_DATA_READ) {
 193                 dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
 194                 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
 195                     test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
 196                         goto force_pio_with_unmap;
 197         } else {
 198                 dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
 199         }
 200
 201         renesas_sdhi_internal_dmac_enable_dma(host, true);
 202
 203         /* set dma parameters */
 204         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
 205                                             dtran_mode);
 206         renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
 207                                             sg_dma_address(sg));
 208
 209         host->dma_on = true;
 210
 211         return;
 212
 213 force_pio_with_unmap:
 214         dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data));
 215
 216 force_pio:
 217         renesas_sdhi_internal_dmac_enable_dma(host, false);
 218 }
 219
 220 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
 221 {
 222         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
 223
 224         tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
 225
 226         /* start the DMAC */
 227         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
 228                                             DTRAN_CTRL_DM_START);
 229 }
 230
 231 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
 232 {
 233         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
 234         enum dma_data_direction dir;
 235
 236         spin_lock_irq(&host->lock);
 237
 238         if (!host->data)
 239                 goto out;
 240
 241         if (host->data->flags & MMC_DATA_READ)
 242                 dir = DMA_FROM_DEVICE;
 243         else
 244                 dir = DMA_TO_DEVICE;
 245
 246         renesas_sdhi_internal_dmac_enable_dma(host, false);
 247         dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
 248
 249         if (dir == DMA_FROM_DEVICE)
 250                 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
 251
 252         tmio_mmc_do_data_irq(host);
 253 out:
 254         spin_unlock_irq(&host->lock);
 255 }
 256
 257 static void
 258 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
 259                                        struct tmio_mmc_data *pdata)
 260 {
 261         struct renesas_sdhi *priv = host_to_priv(host);
 262
 263         /* Disable DMAC interrupts, we don't use them */
 264         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK,
 265                                             INFO1_MASK_CLEAR);
 266         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK,
 267                                             INFO2_MASK_CLEAR);
 268
 269         /* Each value is set to non-zero to assume "enabling" each DMA */
 270         host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
 271
 272         tasklet_init(&priv->dma_priv.dma_complete,
 273                      renesas_sdhi_internal_dmac_complete_tasklet_fn,
 274                      (unsigned long)host);
 275         tasklet_init(&host->dma_issue,
 276                      renesas_sdhi_internal_dmac_issue_tasklet_fn,
 277                      (unsigned long)host);
 278 }
 279
 280 static void
 281 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
 282 {
 283         /* Each value is set to zero to assume "disabling" each DMA */
 284         host->chan_rx = host->chan_tx = NULL;
 285 }
 286
 287 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
 288         .start = renesas_sdhi_internal_dmac_start_dma,
 289         .enable = renesas_sdhi_internal_dmac_enable_dma,
 290         .request = renesas_sdhi_internal_dmac_request_dma,
 291         .release = renesas_sdhi_internal_dmac_release_dma,
 292         .abort = renesas_sdhi_internal_dmac_abort_dma,
 293         .dataend = renesas_sdhi_internal_dmac_dataend_dma,
 294 };
 295
 296 /*
 297  * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
 298  * implementation as others may use a different implementation.
 299  */
 300 static const struct soc_device_attribute soc_whitelist[] = {
 301         /* specific ones */
 302         { .soc_id = "r7s9210",
 303           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) },
 304         { .soc_id = "r8a7795", .revision = "ES1.*",
 305           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 306         { .soc_id = "r8a7796", .revision = "ES1.0",
 307           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 308         /* generic ones */
 309         { .soc_id = "r8a774a1" },
 310         { .soc_id = "r8a774c0" },
 311         { .soc_id = "r8a77470" },
 312         { .soc_id = "r8a7795" },
 313         { .soc_id = "r8a7796" },
 314         { .soc_id = "r8a77965" },
 315         { .soc_id = "r8a77970" },
 316         { .soc_id = "r8a77980" },
 317         { .soc_id = "r8a77990" },
 318         { .soc_id = "r8a77995" },
 319         { /* sentinel */ }
 320 };
 321
 322 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
 323 {
 324         const struct soc_device_attribute *soc = soc_device_match(soc_whitelist);
 325         struct device *dev = &pdev->dev;
 326
 327         if (!soc)
 328                 return -ENODEV;
 329
 330         global_flags |= (unsigned long)soc->data;
 331
 332         dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
 333         if (!dev->dma_parms)
 334                 return -ENOMEM;
 335
 336         /* value is max of SD_SECCNT. Confirmed by HW engineers */
 337         dma_set_max_seg_size(dev, 0xffffffff);
 338
 339         return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
 340 }
 341
 342 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
 343         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 344                                 pm_runtime_force_resume)
 345         SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
 346                            tmio_mmc_host_runtime_resume,
 347                            NULL)
 348 };
 349
 350 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
 351         .driver         = {
 352                 .name   = "renesas_sdhi_internal_dmac",
 353                 .pm     = &renesas_sdhi_internal_dmac_dev_pm_ops,
 354                 .of_match_table = renesas_sdhi_internal_dmac_of_match,
 355         },
 356         .probe          = renesas_sdhi_internal_dmac_probe,
 357         .remove         = renesas_sdhi_remove,
 358 };
 359
 360 module_platform_driver(renesas_internal_dmac_sdhi_driver);
 361
 362 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
 363 MODULE_AUTHOR("Yoshihiro Shimoda");
 364 MODULE_LICENSE("GPL v2");