drivers/mmc/host/renesas_sdhi_internal_dmac.c

   1 /*
   2  * DMA support for Internal DMAC with SDHI SD/SDIO controller
   3  *
   4  * Copyright (C) 2016-17 Renesas Electronics Corporation
   5  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/io-64-nonatomic-hi-lo.h>
  16 #include <linux/mfd/tmio.h>
  17 #include <linux/mmc/host.h>
  18 #include <linux/mod_devicetable.h>
  19 #include <linux/module.h>
  20 #include <linux/pagemap.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/sys_soc.h>
  23
  24 #include "renesas_sdhi.h"
  25 #include "tmio_mmc.h"
  26
  27 #define DM_CM_DTRAN_MODE        0x820
  28 #define DM_CM_DTRAN_CTRL        0x828
  29 #define DM_CM_RST               0x830
  30 #define DM_CM_INFO1             0x840
  31 #define DM_CM_INFO1_MASK        0x848
  32 #define DM_CM_INFO2             0x850
  33 #define DM_CM_INFO2_MASK        0x858
  34 #define DM_DTRAN_ADDR           0x880
  35
  36 /* DM_CM_DTRAN_MODE */
  37 #define DTRAN_MODE_CH_NUM_CH0   0       /* "downstream" = for write commands */
  38 #define DTRAN_MODE_CH_NUM_CH1   BIT(16) /* "uptream" = for read commands */
  39 #define DTRAN_MODE_BUS_WID_TH   (BIT(5) | BIT(4))
  40 #define DTRAN_MODE_ADDR_MODE    BIT(0)  /* 1 = Increment address */
  41
  42 /* DM_CM_DTRAN_CTRL */
  43 #define DTRAN_CTRL_DM_START     BIT(0)
  44
  45 /* DM_CM_RST */
  46 #define RST_DTRANRST1           BIT(9)
  47 #define RST_DTRANRST0           BIT(8)
  48 #define RST_RESERVED_BITS       GENMASK_ULL(32, 0)
  49
  50 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
  51 #define INFO1_CLEAR             0
  52 #define INFO1_DTRANEND1         BIT(17)
  53 #define INFO1_DTRANEND0         BIT(16)
  54
  55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
  56 #define INFO2_DTRANERR1         BIT(17)
  57 #define INFO2_DTRANERR0         BIT(16)
  58
  59 /*
  60  * Specification of this driver:
  61  * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
  62  * - Since this SDHI DMAC register set has 16 but 32-bit width, we
  63  *   need a custom accessor.
  64  */
  65
  66 static unsigned long global_flags;
  67 /*
  68  * Workaround for avoiding to use RX DMAC by multiple channels.
  69  * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
  70  * RX DMAC simultaneously, sometimes hundreds of bytes data are not
  71  * stored into the system memory even if the DMAC interrupt happened.
  72  * So, this driver then uses one RX DMAC channel only.
  73  */
  74 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY  0
  75 #define SDHI_INTERNAL_DMAC_RX_IN_USE    1
  76
  77 /* Definitions for sampling clocks */
  78 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
  79         {
  80                 .clk_rate = 0,
  81                 .tap = 0x00000300,
  82         },
  83 };
  84
  85 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
  86         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  87                           TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  88         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  89                           MMC_CAP_CMD23,
  90         .bus_shift      = 2,
  91         .scc_offset     = 0x1000,
  92         .taps           = rcar_gen3_scc_taps,
  93         .taps_num       = ARRAY_SIZE(rcar_gen3_scc_taps),
  94         /* Gen3 SDHI DMAC can handle 0xffffffff blk count, but seg = 1 */
  95         .max_blk_count  = 0xffffffff,
  96         .max_segs       = 1,
  97 };
  98
  99 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
 100         { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
 101         { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
 102         { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
 103         {},
 104 };
 105 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
 106
 107 static void
 108 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
 109                                     int addr, u64 val)
 110 {
 111         writeq(val, host->ctl + addr);
 112 }
 113
 114 static void
 115 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
 116 {
 117         struct renesas_sdhi *priv = host_to_priv(host);
 118
 119         if (!host->chan_tx || !host->chan_rx)
 120                 return;
 121
 122         if (!enable)
 123                 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
 124                                                     INFO1_CLEAR);
 125
 126         if (priv->dma_priv.enable)
 127                 priv->dma_priv.enable(host, enable);
 128 }
 129
 130 static void
 131 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
 132         u64 val = RST_DTRANRST1 | RST_DTRANRST0;
 133
 134         renesas_sdhi_internal_dmac_enable_dma(host, false);
 135
 136         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
 137                                             RST_RESERVED_BITS & ~val);
 138         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
 139                                             RST_RESERVED_BITS | val);
 140
 141         if (host->data && host->data->flags & MMC_DATA_READ)
 142                 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
 143
 144         renesas_sdhi_internal_dmac_enable_dma(host, true);
 145 }
 146
 147 static void
 148 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
 149         struct renesas_sdhi *priv = host_to_priv(host);
 150
 151         tasklet_schedule(&priv->dma_priv.dma_complete);
 152 }
 153
 154 static void
 155 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
 156                                      struct mmc_data *data)
 157 {
 158         struct scatterlist *sg = host->sg_ptr;
 159         u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
 160         enum dma_data_direction dir;
 161         int ret;
 162
 163         /* This DMAC cannot handle if sg_len is not 1 */
 164         WARN_ON(host->sg_len > 1);
 165
 166         /* This DMAC cannot handle if buffer is not 8-bytes alignment */
 167         if (!IS_ALIGNED(sg->offset, 8))
 168                 goto force_pio;
 169
 170         if (data->flags & MMC_DATA_READ) {
 171                 dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
 172                 dir = DMA_FROM_DEVICE;
 173                 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
 174                     test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
 175                         goto force_pio;
 176         } else {
 177                 dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
 178                 dir = DMA_TO_DEVICE;
 179         }
 180
 181         ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
 182         if (ret == 0)
 183                 goto force_pio;
 184
 185         renesas_sdhi_internal_dmac_enable_dma(host, true);
 186
 187         /* set dma parameters */
 188         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
 189                                             dtran_mode);
 190         renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
 191                                             sg->dma_address);
 192
 193         return;
 194
 195 force_pio:
 196         host->force_pio = true;
 197         renesas_sdhi_internal_dmac_enable_dma(host, false);
 198 }
 199
 200 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
 201 {
 202         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
 203
 204         tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
 205
 206         /* start the DMAC */
 207         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
 208                                             DTRAN_CTRL_DM_START);
 209 }
 210
 211 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
 212 {
 213         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
 214         enum dma_data_direction dir;
 215
 216         spin_lock_irq(&host->lock);
 217
 218         if (!host->data)
 219                 goto out;
 220
 221         if (host->data->flags & MMC_DATA_READ)
 222                 dir = DMA_FROM_DEVICE;
 223         else
 224                 dir = DMA_TO_DEVICE;
 225
 226         renesas_sdhi_internal_dmac_enable_dma(host, false);
 227         dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
 228
 229         if (dir == DMA_FROM_DEVICE)
 230                 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
 231
 232         tmio_mmc_do_data_irq(host);
 233 out:
 234         spin_unlock_irq(&host->lock);
 235 }
 236
 237 static void
 238 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
 239                                        struct tmio_mmc_data *pdata)
 240 {
 241         struct renesas_sdhi *priv = host_to_priv(host);
 242
 243         /* Each value is set to non-zero to assume "enabling" each DMA */
 244         host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
 245
 246         tasklet_init(&priv->dma_priv.dma_complete,
 247                      renesas_sdhi_internal_dmac_complete_tasklet_fn,
 248                      (unsigned long)host);
 249         tasklet_init(&host->dma_issue,
 250                      renesas_sdhi_internal_dmac_issue_tasklet_fn,
 251                      (unsigned long)host);
 252 }
 253
 254 static void
 255 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
 256 {
 257         /* Each value is set to zero to assume "disabling" each DMA */
 258         host->chan_rx = host->chan_tx = NULL;
 259 }
 260
 261 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
 262         .start = renesas_sdhi_internal_dmac_start_dma,
 263         .enable = renesas_sdhi_internal_dmac_enable_dma,
 264         .request = renesas_sdhi_internal_dmac_request_dma,
 265         .release = renesas_sdhi_internal_dmac_release_dma,
 266         .abort = renesas_sdhi_internal_dmac_abort_dma,
 267         .dataend = renesas_sdhi_internal_dmac_dataend_dma,
 268 };
 269
 270 /*
 271  * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
 272  * implementation as others may use a different implementation.
 273  */
 274 static const struct soc_device_attribute gen3_soc_whitelist[] = {
 275         { .soc_id = "r8a7795", .revision = "ES1.*",
 276           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 277         { .soc_id = "r8a7795", .revision = "ES2.0" },
 278         { .soc_id = "r8a7796", .revision = "ES1.0",
 279           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 280         { .soc_id = "r8a77995", .revision = "ES1.0" },
 281         { /* sentinel */ }
 282 };
 283
 284 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
 285 {
 286         const struct soc_device_attribute *soc = soc_device_match(gen3_soc_whitelist);
 287
 288         if (!soc)
 289                 return -ENODEV;
 290
 291         global_flags |= (unsigned long)soc->data;
 292
 293         return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
 294 }
 295
 296 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
 297         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 298                                 pm_runtime_force_resume)
 299         SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
 300                            tmio_mmc_host_runtime_resume,
 301                            NULL)
 302 };
 303
 304 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
 305         .driver         = {
 306                 .name   = "renesas_sdhi_internal_dmac",
 307                 .pm     = &renesas_sdhi_internal_dmac_dev_pm_ops,
 308                 .of_match_table = renesas_sdhi_internal_dmac_of_match,
 309         },
 310         .probe          = renesas_sdhi_internal_dmac_probe,
 311         .remove         = renesas_sdhi_remove,
 312 };
 313
 314 module_platform_driver(renesas_internal_dmac_sdhi_driver);
 315
 316 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
 317 MODULE_AUTHOR("Yoshihiro Shimoda");
 318 MODULE_LICENSE("GPL v2");