drivers/mmc/host/renesas_sdhi_core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas SDHI
   4  *
   5  * Copyright (C) 2015-19 Renesas Electronics Corporation
   6  * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
   7  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   8  * Copyright (C) 2009 Magnus Damm
   9  *
  10  * Based on "Compaq ASIC3 support":
  11  *
  12  * Copyright 2001 Compaq Computer Corporation.
  13  * Copyright 2004-2005 Phil Blundell
  14  * Copyright 2007-2008 OpenedHand Ltd.
  15  *
  16  * Authors: Phil Blundell <pb@handhelds.org>,
  17  *          Samuel Ortiz <sameo@openedhand.com>
  18  *
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/mmc/slot-gpio.h>
  29 #include <linux/mfd/tmio.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/delay.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #include <linux/pinctrl/pinctrl-state.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/sys_soc.h>
  36
  37 #include "renesas_sdhi.h"
  38 #include "tmio_mmc.h"
  39
  40 #define HOST_MODE               0xe4
  41
  42 #define SDHI_VER_GEN2_SDR50     0x490c
  43 #define SDHI_VER_RZ_A1          0x820b
  44 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  45 #define SDHI_VER_GEN2_SDR104    0xcb0d
  46 #define SDHI_VER_GEN3_SD        0xcc10
  47 #define SDHI_VER_GEN3_SDMMC     0xcd10
  48
  49 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  50 {
  51         u32 val;
  52
  53         /*
  54          * see also
  55          *      renesas_sdhi_of_data :: dma_buswidth
  56          */
  57         switch (sd_ctrl_read16(host, CTL_VERSION)) {
  58         case SDHI_VER_GEN2_SDR50:
  59                 val = (width == 32) ? 0x0001 : 0x0000;
  60                 break;
  61         case SDHI_VER_GEN2_SDR104:
  62                 val = (width == 32) ? 0x0000 : 0x0001;
  63                 break;
  64         case SDHI_VER_GEN3_SD:
  65         case SDHI_VER_GEN3_SDMMC:
  66                 if (width == 64)
  67                         val = 0x0000;
  68                 else if (width == 32)
  69                         val = 0x0101;
  70                 else
  71                         val = 0x0001;
  72                 break;
  73         default:
  74                 /* nothing to do */
  75                 return;
  76         }
  77
  78         sd_ctrl_write16(host, HOST_MODE, val);
  79 }
  80
  81 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  82 {
  83         struct mmc_host *mmc = host->mmc;
  84         struct renesas_sdhi *priv = host_to_priv(host);
  85         int ret = clk_prepare_enable(priv->clk);
  86
  87         if (ret < 0)
  88                 return ret;
  89
  90         ret = clk_prepare_enable(priv->clk_cd);
  91         if (ret < 0) {
  92                 clk_disable_unprepare(priv->clk);
  93                 return ret;
  94         }
  95
  96         /*
  97          * The clock driver may not know what maximum frequency
  98          * actually works, so it should be set with the max-frequency
  99          * property which will already have been read to f_max.  If it
 100          * was missing, assume the current frequency is the maximum.
 101          */
 102         if (!mmc->f_max)
 103                 mmc->f_max = clk_get_rate(priv->clk);
 104
 105         /*
 106          * Minimum frequency is the minimum input clock frequency
 107          * divided by our maximum divider.
 108          */
 109         mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 110
 111         /* enable 16bit data access on SDBUF as default */
 112         renesas_sdhi_sdbuf_width(host, 16);
 113
 114         return 0;
 115 }
 116
 117 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 118                                             unsigned int new_clock)
 119 {
 120         struct renesas_sdhi *priv = host_to_priv(host);
 121         unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 122         int i;
 123
 124         /* tested only on R-Car Gen2+ currently; may work for others */
 125         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 126                 return clk_get_rate(priv->clk);
 127
 128         /*
 129          * We want the bus clock to be as close as possible to, but no
 130          * greater than, new_clock.  As we can divide by 1 << i for
 131          * any i in [0, 9] we want the input clock to be as close as
 132          * possible, but no greater than, new_clock << i.
 133          */
 134         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 135                 freq = clk_round_rate(priv->clk, new_clock << i);
 136                 if (freq > (new_clock << i)) {
 137                         /* Too fast; look for a slightly slower option */
 138                         freq = clk_round_rate(priv->clk,
 139                                               (new_clock << i) / 4 * 3);
 140                         if (freq > (new_clock << i))
 141                                 continue;
 142                 }
 143
 144                 diff = new_clock - (freq >> i);
 145                 if (diff <= diff_min) {
 146                         best_freq = freq;
 147                         diff_min = diff;
 148                 }
 149         }
 150
 151         clk_set_rate(priv->clk, best_freq);
 152
 153         return clk_get_rate(priv->clk);
 154 }
 155
 156 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
 157                                    unsigned int new_clock)
 158 {
 159         u32 clk = 0, clock;
 160
 161         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 162                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 163
 164         if (new_clock == 0) {
 165                 host->mmc->actual_clock = 0;
 166                 goto out;
 167         }
 168
 169         host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
 170         clock = host->mmc->actual_clock / 512;
 171
 172         for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
 173                 clock <<= 1;
 174
 175         /* 1/1 clock is option */
 176         if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
 177                 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
 178                         clk |= 0xff;
 179                 else
 180                         clk &= ~0xff;
 181         }
 182
 183         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
 184         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 185                 usleep_range(10000, 11000);
 186
 187         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 188                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 189
 190 out:
 191         /* HW engineers overrode docs: no sleep needed on R-Car2+ */
 192         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 193                 usleep_range(10000, 11000);
 194 }
 195
 196 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
 197 {
 198         struct renesas_sdhi *priv = host_to_priv(host);
 199
 200         clk_disable_unprepare(priv->clk);
 201         clk_disable_unprepare(priv->clk_cd);
 202 }
 203
 204 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
 205 {
 206         struct tmio_mmc_host *host = mmc_priv(mmc);
 207
 208         return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
 209                  TMIO_STAT_DAT0);
 210 }
 211
 212 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 213                                                     struct mmc_ios *ios)
 214 {
 215         struct tmio_mmc_host *host = mmc_priv(mmc);
 216         struct renesas_sdhi *priv = host_to_priv(host);
 217         struct pinctrl_state *pin_state;
 218         int ret;
 219
 220         switch (ios->signal_voltage) {
 221         case MMC_SIGNAL_VOLTAGE_330:
 222                 pin_state = priv->pins_default;
 223                 break;
 224         case MMC_SIGNAL_VOLTAGE_180:
 225                 pin_state = priv->pins_uhs;
 226                 break;
 227         default:
 228                 return -EINVAL;
 229         }
 230
 231         /*
 232          * If anything is missing, assume signal voltage is fixed at
 233          * 3.3V and succeed/fail accordingly.
 234          */
 235         if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 236                 return ios->signal_voltage ==
 237                         MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 238
 239         ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 240         if (ret)
 241                 return ret;
 242
 243         return pinctrl_select_state(priv->pinctrl, pin_state);
 244 }
 245
 246 /* SCC registers */
 247 #define SH_MOBILE_SDHI_SCC_DTCNTL       0x000
 248 #define SH_MOBILE_SDHI_SCC_TAPSET       0x002
 249 #define SH_MOBILE_SDHI_SCC_DT2FF        0x004
 250 #define SH_MOBILE_SDHI_SCC_CKSEL        0x006
 251 #define SH_MOBILE_SDHI_SCC_RVSCNTL      0x008
 252 #define SH_MOBILE_SDHI_SCC_RVSREQ       0x00A
 253 #define SH_MOBILE_SDHI_SCC_SMPCMP       0x00C
 254 #define SH_MOBILE_SDHI_SCC_TMPPORT2     0x00E
 255
 256 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
 257 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
 258 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
 259
 260 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL          BIT(0)
 261
 262 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN        BIT(0)
 263
 264 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN    BIT(0)
 265 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP      BIT(1)
 266 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR        BIT(2)
 267
 268 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN   BIT(8)
 269 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP     BIT(24)
 270 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR       (BIT(8) | BIT(24))
 271
 272 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL   BIT(4)
 273 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN     BIT(31)
 274
 275 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 276                                 struct renesas_sdhi *priv, int addr)
 277 {
 278         return readl(priv->scc_ctl + (addr << host->bus_shift));
 279 }
 280
 281 static inline void sd_scc_write32(struct tmio_mmc_host *host,
 282                                   struct renesas_sdhi *priv,
 283                                   int addr, u32 val)
 284 {
 285         writel(val, priv->scc_ctl + (addr << host->bus_shift));
 286 }
 287
 288 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
 289 {
 290         struct renesas_sdhi *priv;
 291
 292         priv = host_to_priv(host);
 293
 294         /* Initialize SCC */
 295         sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 296
 297         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 298                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 299
 300         /* set sampling clock selection range */
 301         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 302                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 303                        0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 304
 305         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 306                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 307                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 308
 309         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 310                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 311                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 312
 313         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 314
 315         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 316                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 317
 318         /* Read TAPNUM */
 319         return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 320                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 321                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 322 }
 323
 324 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
 325 {
 326         struct tmio_mmc_host *host = mmc_priv(mmc);
 327         struct renesas_sdhi *priv = host_to_priv(host);
 328
 329         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 330                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 331
 332         /* Set HS400 mode */
 333         sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
 334                         sd_ctrl_read16(host, CTL_SDIF_MODE));
 335
 336         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
 337                        priv->scc_tappos_hs400);
 338
 339         /* Gen3 can't do automatic tap correction with HS400, so disable it */
 340         if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
 341                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 342                                ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 343                                sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 344
 345         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 346                        (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 347                         SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
 348                         sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 349
 350         /* Set the sampling clock selection range of HS400 mode */
 351         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 352                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 353                        0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 354
 355
 356         if (priv->quirks && priv->quirks->hs400_4taps)
 357                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 358                                priv->tap_set / 2);
 359
 360         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 361                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 362                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 363
 364         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 365                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 366 }
 367
 368 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
 369                                    struct renesas_sdhi *priv)
 370 {
 371         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 372                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 373
 374         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 375                        ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 376                        sd_scc_read32(host, priv,
 377                                      SH_MOBILE_SDHI_SCC_CKSEL));
 378 }
 379
 380 static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
 381 {
 382         struct tmio_mmc_host *host = mmc_priv(mmc);
 383         struct renesas_sdhi *priv = host_to_priv(host);
 384
 385         renesas_sdhi_reset_scc(host, priv);
 386
 387         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 388                        ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
 389                        sd_scc_read32(host, priv,
 390                                      SH_MOBILE_SDHI_SCC_DTCNTL));
 391
 392         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 393                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 394 }
 395
 396 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
 397                                           struct renesas_sdhi *priv)
 398 {
 399         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 400                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 401
 402         /* Reset HS400 mode */
 403         sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
 404                         sd_ctrl_read16(host, CTL_SDIF_MODE));
 405
 406         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 407
 408         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 409                        ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 410                          SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
 411                         sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 412
 413         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 414                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 415 }
 416
 417 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
 418 {
 419         struct tmio_mmc_host *host = mmc_priv(mmc);
 420
 421         renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
 422         return 0;
 423 }
 424
 425 #define SH_MOBILE_SDHI_MAX_TAP 3
 426
 427 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
 428 {
 429         struct renesas_sdhi *priv = host_to_priv(host);
 430         unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
 431         unsigned int taps_size = priv->tap_num * 2;
 432
 433         priv->doing_tune = false;
 434         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 435
 436         /*
 437          * When tuning CMD19 is issued twice for each tap, merge the
 438          * result requiring the tap to be good in both runs before
 439          * considering it for tuning selection.
 440          */
 441         for (i = 0; i < taps_size; i++) {
 442                 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
 443
 444                 if (!test_bit(i, priv->taps))
 445                         clear_bit(i + offset, priv->taps);
 446         }
 447
 448         /*
 449          * Find the longest consecutive run of successful probes.  If that
 450          * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
 451          * center index as the tap.
 452          */
 453         bitmap_for_each_set_region(priv->taps, rs, re, 0, taps_size) {
 454                 if (re - rs > tap_cnt) {
 455                         tap_end = re;
 456                         tap_start = rs;
 457                         tap_cnt = tap_end - tap_start;
 458                 }
 459         }
 460
 461         if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
 462                 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
 463         else
 464                 return -EIO;
 465
 466         /* Set SCC */
 467         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
 468
 469         /* Enable auto re-tuning */
 470         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 471                        SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 472                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 473
 474         return 0;
 475 }
 476
 477 static int renesas_sdhi_execute_tuning(struct tmio_mmc_host *host, u32 opcode)
 478 {
 479         struct renesas_sdhi *priv = host_to_priv(host);
 480         int i;
 481
 482         priv->tap_num = renesas_sdhi_init_tuning(host);
 483         if (!priv->tap_num)
 484                 return 0; /* Tuning is not supported */
 485
 486         if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
 487                 dev_err(&host->pdev->dev,
 488                         "Too many taps, please update 'taps' in tmio_mmc_host!\n");
 489                 return -EINVAL;
 490         }
 491
 492         priv->doing_tune = true;
 493         bitmap_zero(priv->taps, priv->tap_num * 2);
 494
 495         /* Issue CMD19 twice for each tap */
 496         for (i = 0; i < 2 * priv->tap_num; i++) {
 497                 /* Set sampling clock position */
 498                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
 499
 500                 if (mmc_send_tuning(host->mmc, opcode, NULL) == 0)
 501                         set_bit(i, priv->taps);
 502         }
 503
 504         return renesas_sdhi_select_tuning(host);
 505 }
 506
 507 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
 508 {
 509         struct renesas_sdhi *priv = host_to_priv(host);
 510         unsigned long new_tap = priv->tap_set;
 511         u32 val;
 512
 513         val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
 514         if (!val)
 515                 return false;
 516
 517         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 518
 519         /* Change TAP position according to correction status */
 520         if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
 521             host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
 522                 /*
 523                  * With HS400, the DAT signal is based on DS, not CLK.
 524                  * Therefore, use only CMD status.
 525                  */
 526                 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
 527                                            SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
 528                 if (!smpcmp)
 529                         return false;   /* no error in CMD signal */
 530                 else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP)
 531                         new_tap++;
 532                 else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN)
 533                         new_tap--;
 534                 else
 535                         return true;    /* need retune */
 536         } else {
 537                 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
 538                         return true;    /* need retune */
 539                 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
 540                         new_tap++;
 541                 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
 542                         new_tap--;
 543                 else
 544                         return false;
 545         }
 546
 547         priv->tap_set = (new_tap % priv->tap_num);
 548         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 549                        priv->tap_set / (use_4tap ? 2 : 1));
 550
 551         return false;
 552 }
 553
 554 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
 555 {
 556         struct renesas_sdhi *priv = host_to_priv(host);
 557
 558         /* Check SCC error */
 559         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 560             SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 561                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 562                 return true;
 563         }
 564
 565         return false;
 566 }
 567
 568 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
 569 {
 570         struct renesas_sdhi *priv = host_to_priv(host);
 571         bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
 572
 573         /*
 574          * Skip checking SCC errors when running on 4 taps in HS400 mode as
 575          * any retuning would still result in the same 4 taps being used.
 576          */
 577         if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
 578             !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
 579             !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
 580                 return false;
 581
 582         if (mmc_doing_retune(host->mmc) || priv->doing_tune)
 583                 return false;
 584
 585         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 586             SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
 587                 return renesas_sdhi_auto_correction(host);
 588
 589         return renesas_sdhi_manual_correction(host, use_4tap);
 590 }
 591
 592 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
 593 {
 594         struct renesas_sdhi *priv;
 595
 596         priv = host_to_priv(host);
 597
 598         renesas_sdhi_reset_scc(host, priv);
 599         renesas_sdhi_reset_hs400_mode(host, priv);
 600
 601         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 602                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 603
 604         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 605                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 606                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 607
 608         if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
 609                 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK,
 610                                              TMIO_MASK_INIT_RCAR2);
 611 }
 612
 613 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
 614 {
 615         int timeout = 1000;
 616         /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
 617         u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
 618
 619         while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 620                               & bit) == wait_state)
 621                 udelay(1);
 622
 623         if (!timeout) {
 624                 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 625                 return -EBUSY;
 626         }
 627
 628         return 0;
 629 }
 630
 631 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 632 {
 633         u32 bit = TMIO_STAT_SCLKDIVEN;
 634
 635         switch (addr) {
 636         case CTL_SD_CMD:
 637         case CTL_STOP_INTERNAL_ACTION:
 638         case CTL_XFER_BLK_COUNT:
 639         case CTL_SD_XFER_LEN:
 640         case CTL_SD_MEM_CARD_OPT:
 641         case CTL_TRANSACTION_CTL:
 642         case CTL_DMA_ENABLE:
 643         case HOST_MODE:
 644                 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
 645                         bit = TMIO_STAT_CMD_BUSY;
 646                 /* fallthrough */
 647         case CTL_SD_CARD_CLK_CTL:
 648                 return renesas_sdhi_wait_idle(host, bit);
 649         }
 650
 651         return 0;
 652 }
 653
 654 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
 655                                        unsigned int direction, int blk_size)
 656 {
 657         /*
 658          * In Renesas controllers, when performing a
 659          * multiple block read of one or two blocks,
 660          * depending on the timing with which the
 661          * response register is read, the response
 662          * value may not be read properly.
 663          * Use single block read for this HW bug
 664          */
 665         if ((direction == MMC_DATA_READ) &&
 666             blk_size == 2)
 667                 return 1;
 668
 669         return blk_size;
 670 }
 671
 672 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 673 {
 674         /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
 675         int width = (host->bus_shift == 2) ? 64 : 32;
 676
 677         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
 678         renesas_sdhi_sdbuf_width(host, enable ? width : 16);
 679 }
 680
 681 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
 682         .hs400_disabled = true,
 683         .hs400_4taps = true,
 684 };
 685
 686 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
 687         .hs400_4taps = true,
 688 };
 689
 690 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
 691         .hs400_disabled = true,
 692 };
 693
 694 static const struct soc_device_attribute sdhi_quirks_match[]  = {
 695         { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
 696         { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
 697         { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
 698         { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
 699         { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
 700         { /* Sentinel. */ },
 701 };
 702
 703 int renesas_sdhi_probe(struct platform_device *pdev,
 704                        const struct tmio_mmc_dma_ops *dma_ops)
 705 {
 706         struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 707         const struct renesas_sdhi_quirks *quirks = NULL;
 708         const struct renesas_sdhi_of_data *of_data;
 709         const struct soc_device_attribute *attr;
 710         struct tmio_mmc_data *mmc_data;
 711         struct tmio_mmc_dma *dma_priv;
 712         struct tmio_mmc_host *host;
 713         struct renesas_sdhi *priv;
 714         int num_irqs, irq, ret, i;
 715         struct resource *res;
 716         u16 ver;
 717
 718         of_data = of_device_get_match_data(&pdev->dev);
 719
 720         attr = soc_device_match(sdhi_quirks_match);
 721         if (attr)
 722                 quirks = attr->data;
 723
 724         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 725         if (!res)
 726                 return -EINVAL;
 727
 728         priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
 729                             GFP_KERNEL);
 730         if (!priv)
 731                 return -ENOMEM;
 732
 733         priv->quirks = quirks;
 734         mmc_data = &priv->mmc_data;
 735         dma_priv = &priv->dma_priv;
 736
 737         priv->clk = devm_clk_get(&pdev->dev, NULL);
 738         if (IS_ERR(priv->clk)) {
 739                 ret = PTR_ERR(priv->clk);
 740                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
 741                 return ret;
 742         }
 743
 744         /*
 745          * Some controllers provide a 2nd clock just to run the internal card
 746          * detection logic. Unfortunately, the existing driver architecture does
 747          * not support a separation of clocks for runtime PM usage. When
 748          * native hotplug is used, the tmio driver assumes that the core
 749          * must continue to run for card detect to stay active, so we cannot
 750          * disable it.
 751          * Additionally, it is prohibited to supply a clock to the core but not
 752          * to the card detect circuit. That leaves us with if separate clocks
 753          * are presented, we must treat them both as virtually 1 clock.
 754          */
 755         priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
 756         if (IS_ERR(priv->clk_cd))
 757                 priv->clk_cd = NULL;
 758
 759         priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 760         if (!IS_ERR(priv->pinctrl)) {
 761                 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
 762                                                 PINCTRL_STATE_DEFAULT);
 763                 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
 764                                                 "state_uhs");
 765         }
 766
 767         host = tmio_mmc_host_alloc(pdev, mmc_data);
 768         if (IS_ERR(host))
 769                 return PTR_ERR(host);
 770
 771         if (of_data) {
 772                 mmc_data->flags |= of_data->tmio_flags;
 773                 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
 774                 mmc_data->capabilities |= of_data->capabilities;
 775                 mmc_data->capabilities2 |= of_data->capabilities2;
 776                 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
 777                 mmc_data->max_blk_count = of_data->max_blk_count;
 778                 mmc_data->max_segs = of_data->max_segs;
 779                 dma_priv->dma_buswidth = of_data->dma_buswidth;
 780                 host->bus_shift = of_data->bus_shift;
 781         }
 782
 783         host->write16_hook      = renesas_sdhi_write16_hook;
 784         host->clk_enable        = renesas_sdhi_clk_enable;
 785         host->clk_disable       = renesas_sdhi_clk_disable;
 786         host->set_clock         = renesas_sdhi_set_clock;
 787         host->multi_io_quirk    = renesas_sdhi_multi_io_quirk;
 788         host->dma_ops           = dma_ops;
 789
 790         if (quirks && quirks->hs400_disabled)
 791                 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
 792
 793         /* For some SoC, we disable internal WP. GPIO may override this */
 794         if (mmc_can_gpio_ro(host->mmc))
 795                 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
 796
 797         /* SDR speeds are only available on Gen2+ */
 798         if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
 799                 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
 800                 host->ops.card_busy = renesas_sdhi_card_busy;
 801                 host->ops.start_signal_voltage_switch =
 802                         renesas_sdhi_start_signal_voltage_switch;
 803                 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
 804
 805                 /* SDR and HS200/400 registers requires HW reset */
 806                 if (of_data && of_data->scc_offset) {
 807                         priv->scc_ctl = host->ctl + of_data->scc_offset;
 808                         host->mmc->caps |= MMC_CAP_HW_RESET;
 809                         host->hw_reset = renesas_sdhi_hw_reset;
 810                 }
 811         }
 812
 813         /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
 814         if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
 815                 host->bus_shift = 1;
 816
 817         if (mmd)
 818                 *mmc_data = *mmd;
 819
 820         dma_priv->filter = shdma_chan_filter;
 821         dma_priv->enable = renesas_sdhi_enable_dma;
 822
 823         mmc_data->alignment_shift = 1; /* 2-byte alignment */
 824         mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
 825
 826         /*
 827          * All SDHI blocks support 2-byte and larger block sizes in 4-bit
 828          * bus width mode.
 829          */
 830         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
 831
 832         /*
 833          * All SDHI blocks support SDIO IRQ signalling.
 834          */
 835         mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
 836
 837         /* All SDHI have CMD12 control bit */
 838         mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
 839
 840         /* All SDHI have SDIO status bits which must be 1 */
 841         mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
 842
 843         ret = renesas_sdhi_clk_enable(host);
 844         if (ret)
 845                 goto efree;
 846
 847         ver = sd_ctrl_read16(host, CTL_VERSION);
 848         /* GEN2_SDR104 is first known SDHI to use 32bit block count */
 849         if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
 850                 mmc_data->max_blk_count = U16_MAX;
 851
 852         /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
 853         if (ver == SDHI_VER_GEN2_SDR50)
 854                 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
 855
 856         ret = tmio_mmc_host_probe(host);
 857         if (ret < 0)
 858                 goto edisclk;
 859
 860         /* Enable tuning iff we have an SCC and a supported mode */
 861         if (of_data && of_data->scc_offset &&
 862             (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
 863              host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
 864                                  MMC_CAP2_HS400_1_8V))) {
 865                 const struct renesas_sdhi_scc *taps = of_data->taps;
 866                 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
 867                 bool hit = false;
 868
 869                 for (i = 0; i < of_data->taps_num; i++) {
 870                         if (taps[i].clk_rate == 0 ||
 871                             taps[i].clk_rate == host->mmc->f_max) {
 872                                 priv->scc_tappos = taps->tap;
 873                                 priv->scc_tappos_hs400 = use_4tap ?
 874                                                          taps->tap_hs400_4tap :
 875                                                          taps->tap;
 876                                 hit = true;
 877                                 break;
 878                         }
 879                 }
 880
 881                 if (!hit)
 882                         dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
 883
 884                 host->execute_tuning = renesas_sdhi_execute_tuning;
 885                 host->check_retune = renesas_sdhi_check_scc_error;
 886                 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
 887                 host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
 888                 host->ops.hs400_complete = renesas_sdhi_hs400_complete;
 889         }
 890
 891         num_irqs = platform_irq_count(pdev);
 892         if (num_irqs < 0) {
 893                 ret = num_irqs;
 894                 goto eirq;
 895         }
 896
 897         /* There must be at least one IRQ source */
 898         if (!num_irqs) {
 899                 ret = -ENXIO;
 900                 goto eirq;
 901         }
 902
 903         for (i = 0; i < num_irqs; i++) {
 904                 irq = platform_get_irq(pdev, i);
 905                 if (irq < 0) {
 906                         ret = irq;
 907                         goto eirq;
 908                 }
 909
 910                 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
 911                                        dev_name(&pdev->dev), host);
 912                 if (ret)
 913                         goto eirq;
 914         }
 915
 916         dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
 917                  mmc_hostname(host->mmc), (unsigned long)
 918                  (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
 919                  host->mmc->f_max / 1000000);
 920
 921         return ret;
 922
 923 eirq:
 924         tmio_mmc_host_remove(host);
 925 edisclk:
 926         renesas_sdhi_clk_disable(host);
 927 efree:
 928         tmio_mmc_host_free(host);
 929
 930         return ret;
 931 }
 932 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
 933
 934 int renesas_sdhi_remove(struct platform_device *pdev)
 935 {
 936         struct tmio_mmc_host *host = platform_get_drvdata(pdev);
 937
 938         tmio_mmc_host_remove(host);
 939         renesas_sdhi_clk_disable(host);
 940
 941         return 0;
 942 }
 943 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
 944
 945 MODULE_LICENSE("GPL v2");