1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8 * Copyright (C) 2009 Magnus Damm
10 * Based on "Compaq ASIC3 support":
12 * Copyright 2001 Compaq Computer Corporation.
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
16 * Authors: Phil Blundell <pb@handhelds.org>,
17 * Samuel Ortiz <sameo@openedhand.com>
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/mfd/tmio.h>
30 #include <linux/sh_dma.h>
31 #include <linux/delay.h>
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/pinctrl/pinctrl-state.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/sys_soc.h>
37 #include "renesas_sdhi.h"
40 #define HOST_MODE 0xe4
42 #define SDHI_VER_GEN2_SDR50 0x490c
43 #define SDHI_VER_RZ_A1 0x820b
44 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
45 #define SDHI_VER_GEN2_SDR104 0xcb0d
46 #define SDHI_VER_GEN3_SD 0xcc10
47 #define SDHI_VER_GEN3_SDMMC 0xcd10
49 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
55 * renesas_sdhi_of_data :: dma_buswidth
57 switch (sd_ctrl_read16(host, CTL_VERSION)) {
58 case SDHI_VER_GEN2_SDR50:
59 val = (width == 32) ? 0x0001 : 0x0000;
61 case SDHI_VER_GEN2_SDR104:
62 val = (width == 32) ? 0x0000 : 0x0001;
64 case SDHI_VER_GEN3_SD:
65 case SDHI_VER_GEN3_SDMMC:
78 sd_ctrl_write16(host, HOST_MODE, val);
81 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
83 struct mmc_host *mmc = host->mmc;
84 struct renesas_sdhi *priv = host_to_priv(host);
85 int ret = clk_prepare_enable(priv->clk);
90 ret = clk_prepare_enable(priv->clk_cd);
92 clk_disable_unprepare(priv->clk);
97 * The clock driver may not know what maximum frequency
98 * actually works, so it should be set with the max-frequency
99 * property which will already have been read to f_max. If it
100 * was missing, assume the current frequency is the maximum.
103 mmc->f_max = clk_get_rate(priv->clk);
106 * Minimum frequency is the minimum input clock frequency
107 * divided by our maximum divider.
109 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
111 /* enable 16bit data access on SDBUF as default */
112 renesas_sdhi_sdbuf_width(host, 16);
117 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
118 unsigned int new_clock)
120 struct renesas_sdhi *priv = host_to_priv(host);
121 unsigned int freq, diff, best_freq = 0, diff_min = ~0;
124 /* tested only on R-Car Gen2+ currently; may work for others */
125 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
126 return clk_get_rate(priv->clk);
129 * We want the bus clock to be as close as possible to, but no
130 * greater than, new_clock. As we can divide by 1 << i for
131 * any i in [0, 9] we want the input clock to be as close as
132 * possible, but no greater than, new_clock << i.
134 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
135 freq = clk_round_rate(priv->clk, new_clock << i);
136 if (freq > (new_clock << i)) {
137 /* Too fast; look for a slightly slower option */
138 freq = clk_round_rate(priv->clk,
139 (new_clock << i) / 4 * 3);
140 if (freq > (new_clock << i))
144 diff = new_clock - (freq >> i);
145 if (diff <= diff_min) {
151 clk_set_rate(priv->clk, best_freq);
153 return clk_get_rate(priv->clk);
156 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
157 unsigned int new_clock)
161 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
162 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
164 if (new_clock == 0) {
165 host->mmc->actual_clock = 0;
169 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
170 clock = host->mmc->actual_clock / 512;
172 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
175 /* 1/1 clock is option */
176 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
177 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
183 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
184 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
185 usleep_range(10000, 11000);
187 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
188 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
191 /* HW engineers overrode docs: no sleep needed on R-Car2+ */
192 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
193 usleep_range(10000, 11000);
196 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
198 struct renesas_sdhi *priv = host_to_priv(host);
200 clk_disable_unprepare(priv->clk);
201 clk_disable_unprepare(priv->clk_cd);
204 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
206 struct tmio_mmc_host *host = mmc_priv(mmc);
208 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
212 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
215 struct tmio_mmc_host *host = mmc_priv(mmc);
216 struct renesas_sdhi *priv = host_to_priv(host);
217 struct pinctrl_state *pin_state;
220 switch (ios->signal_voltage) {
221 case MMC_SIGNAL_VOLTAGE_330:
222 pin_state = priv->pins_default;
224 case MMC_SIGNAL_VOLTAGE_180:
225 pin_state = priv->pins_uhs;
232 * If anything is missing, assume signal voltage is fixed at
233 * 3.3V and succeed/fail accordingly.
235 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
236 return ios->signal_voltage ==
237 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
239 ret = mmc_regulator_set_vqmmc(host->mmc, ios);
243 return pinctrl_select_state(priv->pinctrl, pin_state);
247 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
248 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002
249 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004
250 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006
251 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
252 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
253 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C
254 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
256 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
257 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
258 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
260 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
262 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
264 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
265 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
266 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
268 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
269 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
270 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24))
272 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
273 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
275 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
276 struct renesas_sdhi *priv, int addr)
278 return readl(priv->scc_ctl + (addr << host->bus_shift));
281 static inline void sd_scc_write32(struct tmio_mmc_host *host,
282 struct renesas_sdhi *priv,
285 writel(val, priv->scc_ctl + (addr << host->bus_shift));
288 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
290 struct renesas_sdhi *priv;
292 priv = host_to_priv(host);
295 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
297 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
298 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
300 /* set sampling clock selection range */
301 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
302 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
303 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
305 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
306 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
307 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
309 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
310 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
311 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
313 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
315 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
316 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
319 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
320 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
321 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
324 static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host)
326 struct renesas_sdhi *priv = host_to_priv(host);
328 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
329 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
332 sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
333 sd_ctrl_read16(host, CTL_SDIF_MODE));
335 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
336 priv->scc_tappos_hs400);
338 /* Gen3 can't do automatic tap correction with HS400, so disable it */
339 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
340 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
341 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
342 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
344 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
345 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
346 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
347 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
349 /* Set the sampling clock selection range of HS400 mode */
350 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
351 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
352 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
355 if (priv->quirks && priv->quirks->hs400_4taps)
356 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
359 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
360 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
361 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
363 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
364 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
367 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
368 struct renesas_sdhi *priv)
370 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
371 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
373 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
374 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
375 sd_scc_read32(host, priv,
376 SH_MOBILE_SDHI_SCC_CKSEL));
379 static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host)
381 struct renesas_sdhi *priv = host_to_priv(host);
383 renesas_sdhi_reset_scc(host, priv);
385 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
386 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
387 sd_scc_read32(host, priv,
388 SH_MOBILE_SDHI_SCC_DTCNTL));
390 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
391 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
394 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
395 struct renesas_sdhi *priv)
397 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
398 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
400 /* Reset HS400 mode */
401 sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
402 sd_ctrl_read16(host, CTL_SDIF_MODE));
404 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
406 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
407 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
408 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
409 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
411 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
412 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
415 static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host)
417 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
420 #define SH_MOBILE_SDHI_MAX_TAP 3
422 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
424 struct renesas_sdhi *priv = host_to_priv(host);
425 unsigned long tap_cnt; /* counter of tuning success */
426 unsigned long tap_start;/* start position of tuning success */
427 unsigned long tap_end; /* end position of tuning success */
428 unsigned long ntap; /* temporary counter of tuning success */
431 priv->doing_tune = false;
433 /* Clear SCC_RVSREQ */
434 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
437 * When tuning CMD19 is issued twice for each tap, merge the
438 * result requiring the tap to be good in both runs before
439 * considering it for tuning selection.
441 for (i = 0; i < priv->tap_num * 2; i++) {
442 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
444 if (!test_bit(i, priv->taps))
445 clear_bit(i + offset, priv->taps);
449 * Find the longest consecutive run of successful probes. If that
450 * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
451 * center index as the tap.
457 for (i = 0; i < priv->tap_num * 2; i++) {
458 if (test_bit(i, priv->taps)) {
461 if (ntap > tap_cnt) {
462 tap_start = i - ntap;
470 if (ntap > tap_cnt) {
471 tap_start = i - ntap;
476 if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
477 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
482 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
484 /* Enable auto re-tuning */
485 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
486 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
487 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
492 static int renesas_sdhi_execute_tuning(struct tmio_mmc_host *host, u32 opcode)
494 struct renesas_sdhi *priv = host_to_priv(host);
497 priv->tap_num = renesas_sdhi_init_tuning(host);
499 return 0; /* Tuning is not supported */
501 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
502 dev_err(&host->pdev->dev,
503 "Too many taps, please update 'taps' in tmio_mmc_host!\n");
507 priv->doing_tune = true;
508 bitmap_zero(priv->taps, priv->tap_num * 2);
510 /* Issue CMD19 twice for each tap */
511 for (i = 0; i < 2 * priv->tap_num; i++) {
512 /* Set sampling clock position */
513 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
515 ret = mmc_send_tuning(host->mmc, opcode, NULL);
517 set_bit(i, priv->taps);
520 return renesas_sdhi_select_tuning(host);
523 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
525 struct renesas_sdhi *priv = host_to_priv(host);
526 unsigned long new_tap = priv->tap_set;
529 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
533 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
535 /* Change TAP position according to correction status */
536 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
537 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
539 * With HS400, the DAT signal is based on DS, not CLK.
540 * Therefore, use only CMD status.
542 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
543 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
545 return false; /* no error in CMD signal */
546 else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP)
548 else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN)
551 return true; /* need retune */
553 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
554 return true; /* need retune */
555 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
557 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
563 priv->tap_set = (new_tap % priv->tap_num);
564 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
565 priv->tap_set / (use_4tap ? 2 : 1));
570 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
572 struct renesas_sdhi *priv = host_to_priv(host);
574 /* Check SCC error */
575 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
576 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
577 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
584 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
586 struct renesas_sdhi *priv = host_to_priv(host);
587 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
590 * Skip checking SCC errors when running on 4 taps in HS400 mode as
591 * any retuning would still result in the same 4 taps being used.
593 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
594 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
595 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
598 if (mmc_doing_retune(host->mmc) || priv->doing_tune)
601 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
602 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
603 return renesas_sdhi_auto_correction(host);
605 return renesas_sdhi_manual_correction(host, use_4tap);
608 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
610 struct renesas_sdhi *priv;
612 priv = host_to_priv(host);
614 renesas_sdhi_reset_scc(host, priv);
615 renesas_sdhi_reset_hs400_mode(host, priv);
617 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
618 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
620 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
621 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
622 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
624 if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
625 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK,
626 TMIO_MASK_INIT_RCAR2);
629 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
632 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
633 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
635 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
636 & bit) == wait_state)
640 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
647 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
649 u32 bit = TMIO_STAT_SCLKDIVEN;
653 case CTL_STOP_INTERNAL_ACTION:
654 case CTL_XFER_BLK_COUNT:
655 case CTL_SD_XFER_LEN:
656 case CTL_SD_MEM_CARD_OPT:
657 case CTL_TRANSACTION_CTL:
660 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
661 bit = TMIO_STAT_CMD_BUSY;
663 case CTL_SD_CARD_CLK_CTL:
664 return renesas_sdhi_wait_idle(host, bit);
670 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
671 unsigned int direction, int blk_size)
674 * In Renesas controllers, when performing a
675 * multiple block read of one or two blocks,
676 * depending on the timing with which the
677 * response register is read, the response
678 * value may not be read properly.
679 * Use single block read for this HW bug
681 if ((direction == MMC_DATA_READ) &&
688 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
690 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
691 int width = (host->bus_shift == 2) ? 64 : 32;
693 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
694 renesas_sdhi_sdbuf_width(host, enable ? width : 16);
697 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
698 .hs400_disabled = true,
702 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
706 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
707 .hs400_disabled = true,
710 static const struct soc_device_attribute sdhi_quirks_match[] = {
711 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
712 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
713 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
714 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
715 { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
719 int renesas_sdhi_probe(struct platform_device *pdev,
720 const struct tmio_mmc_dma_ops *dma_ops)
722 struct tmio_mmc_data *mmd = pdev->dev.platform_data;
723 const struct renesas_sdhi_quirks *quirks = NULL;
724 const struct renesas_sdhi_of_data *of_data;
725 const struct soc_device_attribute *attr;
726 struct tmio_mmc_data *mmc_data;
727 struct tmio_mmc_dma *dma_priv;
728 struct tmio_mmc_host *host;
729 struct renesas_sdhi *priv;
730 int num_irqs, irq, ret, i;
731 struct resource *res;
734 of_data = of_device_get_match_data(&pdev->dev);
736 attr = soc_device_match(sdhi_quirks_match);
740 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
744 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
749 priv->quirks = quirks;
750 mmc_data = &priv->mmc_data;
751 dma_priv = &priv->dma_priv;
753 priv->clk = devm_clk_get(&pdev->dev, NULL);
754 if (IS_ERR(priv->clk)) {
755 ret = PTR_ERR(priv->clk);
756 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
761 * Some controllers provide a 2nd clock just to run the internal card
762 * detection logic. Unfortunately, the existing driver architecture does
763 * not support a separation of clocks for runtime PM usage. When
764 * native hotplug is used, the tmio driver assumes that the core
765 * must continue to run for card detect to stay active, so we cannot
767 * Additionally, it is prohibited to supply a clock to the core but not
768 * to the card detect circuit. That leaves us with if separate clocks
769 * are presented, we must treat them both as virtually 1 clock.
771 priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
772 if (IS_ERR(priv->clk_cd))
775 priv->pinctrl = devm_pinctrl_get(&pdev->dev);
776 if (!IS_ERR(priv->pinctrl)) {
777 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
778 PINCTRL_STATE_DEFAULT);
779 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
783 host = tmio_mmc_host_alloc(pdev, mmc_data);
785 return PTR_ERR(host);
788 mmc_data->flags |= of_data->tmio_flags;
789 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
790 mmc_data->capabilities |= of_data->capabilities;
791 mmc_data->capabilities2 |= of_data->capabilities2;
792 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
793 mmc_data->max_blk_count = of_data->max_blk_count;
794 mmc_data->max_segs = of_data->max_segs;
795 dma_priv->dma_buswidth = of_data->dma_buswidth;
796 host->bus_shift = of_data->bus_shift;
799 host->write16_hook = renesas_sdhi_write16_hook;
800 host->clk_enable = renesas_sdhi_clk_enable;
801 host->clk_disable = renesas_sdhi_clk_disable;
802 host->set_clock = renesas_sdhi_set_clock;
803 host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
804 host->dma_ops = dma_ops;
806 if (quirks && quirks->hs400_disabled)
807 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
809 /* For some SoC, we disable internal WP. GPIO may override this */
810 if (mmc_can_gpio_ro(host->mmc))
811 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
813 /* SDR speeds are only available on Gen2+ */
814 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
815 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
816 host->ops.card_busy = renesas_sdhi_card_busy;
817 host->ops.start_signal_voltage_switch =
818 renesas_sdhi_start_signal_voltage_switch;
819 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
821 /* SDR and HS200/400 registers requires HW reset */
822 if (of_data && of_data->scc_offset) {
823 priv->scc_ctl = host->ctl + of_data->scc_offset;
824 host->mmc->caps |= MMC_CAP_HW_RESET;
825 host->hw_reset = renesas_sdhi_hw_reset;
829 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
830 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
836 dma_priv->filter = shdma_chan_filter;
837 dma_priv->enable = renesas_sdhi_enable_dma;
839 mmc_data->alignment_shift = 1; /* 2-byte alignment */
840 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
843 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
846 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
849 * All SDHI blocks support SDIO IRQ signalling.
851 mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
853 /* All SDHI have CMD12 control bit */
854 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
856 /* All SDHI have SDIO status bits which must be 1 */
857 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
859 ret = renesas_sdhi_clk_enable(host);
863 ver = sd_ctrl_read16(host, CTL_VERSION);
864 /* GEN2_SDR104 is first known SDHI to use 32bit block count */
865 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
866 mmc_data->max_blk_count = U16_MAX;
868 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
869 if (ver == SDHI_VER_GEN2_SDR50)
870 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
872 ret = tmio_mmc_host_probe(host);
876 /* Enable tuning iff we have an SCC and a supported mode */
877 if (of_data && of_data->scc_offset &&
878 (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
879 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
880 MMC_CAP2_HS400_1_8V))) {
881 const struct renesas_sdhi_scc *taps = of_data->taps;
882 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
885 for (i = 0; i < of_data->taps_num; i++) {
886 if (taps[i].clk_rate == 0 ||
887 taps[i].clk_rate == host->mmc->f_max) {
888 priv->scc_tappos = taps->tap;
889 priv->scc_tappos_hs400 = use_4tap ?
890 taps->tap_hs400_4tap :
898 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
900 host->execute_tuning = renesas_sdhi_execute_tuning;
901 host->check_retune = renesas_sdhi_check_scc_error;
902 host->prepare_hs400_tuning =
903 renesas_sdhi_prepare_hs400_tuning;
904 host->hs400_downgrade = renesas_sdhi_disable_scc;
905 host->hs400_complete = renesas_sdhi_hs400_complete;
908 num_irqs = platform_irq_count(pdev);
914 /* There must be at least one IRQ source */
920 for (i = 0; i < num_irqs; i++) {
921 irq = platform_get_irq(pdev, i);
927 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
928 dev_name(&pdev->dev), host);
933 dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
934 mmc_hostname(host->mmc), (unsigned long)
935 (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
936 host->mmc->f_max / 1000000);
941 tmio_mmc_host_remove(host);
943 renesas_sdhi_clk_disable(host);
945 tmio_mmc_host_free(host);
949 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
951 int renesas_sdhi_remove(struct platform_device *pdev)
953 struct tmio_mmc_host *host = platform_get_drvdata(pdev);
955 tmio_mmc_host_remove(host);
956 renesas_sdhi_clk_disable(host);
960 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
962 MODULE_LICENSE("GPL v2");