drivers/mmc/host/owl-mmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Actions Semi Owl SoCs SD/MMC driver
   4  *
   5  * Copyright (c) 2014 Actions Semi Inc.
   6  * Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  *
   8  * TODO: SDIO support
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/dma-direction.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/mmc/host.h>
  18 #include <linux/mmc/slot-gpio.h>
  19 #include <linux/module.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/reset.h>
  22 #include <linux/spinlock.h>
  23
  24 /*
  25  * SDC registers
  26  */
  27 #define OWL_REG_SD_EN                   0x0000
  28 #define OWL_REG_SD_CTL                  0x0004
  29 #define OWL_REG_SD_STATE                0x0008
  30 #define OWL_REG_SD_CMD                  0x000c
  31 #define OWL_REG_SD_ARG                  0x0010
  32 #define OWL_REG_SD_RSPBUF0              0x0014
  33 #define OWL_REG_SD_RSPBUF1              0x0018
  34 #define OWL_REG_SD_RSPBUF2              0x001c
  35 #define OWL_REG_SD_RSPBUF3              0x0020
  36 #define OWL_REG_SD_RSPBUF4              0x0024
  37 #define OWL_REG_SD_DAT                  0x0028
  38 #define OWL_REG_SD_BLK_SIZE             0x002c
  39 #define OWL_REG_SD_BLK_NUM              0x0030
  40 #define OWL_REG_SD_BUF_SIZE             0x0034
  41
  42 /* SD_EN Bits */
  43 #define OWL_SD_EN_RANE                  BIT(31)
  44 #define OWL_SD_EN_RAN_SEED(x)           (((x) & 0x3f) << 24)
  45 #define OWL_SD_EN_S18EN                 BIT(12)
  46 #define OWL_SD_EN_RESE                  BIT(10)
  47 #define OWL_SD_EN_DAT1_S                BIT(9)
  48 #define OWL_SD_EN_CLK_S                 BIT(8)
  49 #define OWL_SD_ENABLE                   BIT(7)
  50 #define OWL_SD_EN_BSEL                  BIT(6)
  51 #define OWL_SD_EN_SDIOEN                BIT(3)
  52 #define OWL_SD_EN_DDREN                 BIT(2)
  53 #define OWL_SD_EN_DATAWID(x)            (((x) & 0x3) << 0)
  54
  55 /* SD_CTL Bits */
  56 #define OWL_SD_CTL_TOUTEN               BIT(31)
  57 #define OWL_SD_CTL_TOUTCNT(x)           (((x) & 0x7f) << 24)
  58 #define OWL_SD_CTL_DELAY_MSK            GENMASK(23, 16)
  59 #define OWL_SD_CTL_RDELAY(x)            (((x) & 0xf) << 20)
  60 #define OWL_SD_CTL_WDELAY(x)            (((x) & 0xf) << 16)
  61 #define OWL_SD_CTL_CMDLEN               BIT(13)
  62 #define OWL_SD_CTL_SCC                  BIT(12)
  63 #define OWL_SD_CTL_TCN(x)               (((x) & 0xf) << 8)
  64 #define OWL_SD_CTL_TS                   BIT(7)
  65 #define OWL_SD_CTL_LBE                  BIT(6)
  66 #define OWL_SD_CTL_C7EN                 BIT(5)
  67 #define OWL_SD_CTL_TM(x)                (((x) & 0xf) << 0)
  68
  69 #define OWL_SD_DELAY_LOW_CLK            0x0f
  70 #define OWL_SD_DELAY_MID_CLK            0x0a
  71 #define OWL_SD_DELAY_HIGH_CLK           0x09
  72 #define OWL_SD_RDELAY_DDR50             0x0a
  73 #define OWL_SD_WDELAY_DDR50             0x08
  74
  75 /* SD_STATE Bits */
  76 #define OWL_SD_STATE_DAT1BS             BIT(18)
  77 #define OWL_SD_STATE_SDIOB_P            BIT(17)
  78 #define OWL_SD_STATE_SDIOB_EN           BIT(16)
  79 #define OWL_SD_STATE_TOUTE              BIT(15)
  80 #define OWL_SD_STATE_BAEP               BIT(14)
  81 #define OWL_SD_STATE_MEMRDY             BIT(12)
  82 #define OWL_SD_STATE_CMDS               BIT(11)
  83 #define OWL_SD_STATE_DAT1AS             BIT(10)
  84 #define OWL_SD_STATE_SDIOA_P            BIT(9)
  85 #define OWL_SD_STATE_SDIOA_EN           BIT(8)
  86 #define OWL_SD_STATE_DAT0S              BIT(7)
  87 #define OWL_SD_STATE_TEIE               BIT(6)
  88 #define OWL_SD_STATE_TEI                BIT(5)
  89 #define OWL_SD_STATE_CLNR               BIT(4)
  90 #define OWL_SD_STATE_CLC                BIT(3)
  91 #define OWL_SD_STATE_WC16ER             BIT(2)
  92 #define OWL_SD_STATE_RC16ER             BIT(1)
  93 #define OWL_SD_STATE_CRC7ER             BIT(0)
  94
  95 #define OWL_CMD_TIMEOUT_MS              30000
  96
  97 struct owl_mmc_host {
  98         struct device *dev;
  99         struct reset_control *reset;
 100         void __iomem *base;
 101         struct clk *clk;
 102         struct completion sdc_complete;
 103         spinlock_t lock;
 104         int irq;
 105         u32 clock;
 106         bool ddr_50;
 107
 108         enum dma_data_direction dma_dir;
 109         struct dma_chan *dma;
 110         struct dma_async_tx_descriptor *desc;
 111         struct dma_slave_config dma_cfg;
 112         struct completion dma_complete;
 113
 114         struct mmc_host *mmc;
 115         struct mmc_request *mrq;
 116         struct mmc_command *cmd;
 117         struct mmc_data *data;
 118 };
 119
 120 static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state)
 121 {
 122         unsigned int regval;
 123
 124         regval = readl(reg);
 125
 126         if (state)
 127                 regval |= val;
 128         else
 129                 regval &= ~val;
 130
 131         writel(regval, reg);
 132 }
 133
 134 static irqreturn_t owl_irq_handler(int irq, void *devid)
 135 {
 136         struct owl_mmc_host *owl_host = devid;
 137         u32 state;
 138
 139         spin_lock(&owl_host->lock);
 140
 141         state = readl(owl_host->base + OWL_REG_SD_STATE);
 142         if (state & OWL_SD_STATE_TEI) {
 143                 state = readl(owl_host->base + OWL_REG_SD_STATE);
 144                 state |= OWL_SD_STATE_TEI;
 145                 writel(state, owl_host->base + OWL_REG_SD_STATE);
 146                 complete(&owl_host->sdc_complete);
 147         }
 148
 149         spin_unlock(&owl_host->lock);
 150
 151         return IRQ_HANDLED;
 152 }
 153
 154 static void owl_mmc_finish_request(struct owl_mmc_host *owl_host)
 155 {
 156         struct mmc_request *mrq = owl_host->mrq;
 157         struct mmc_data *data = mrq->data;
 158
 159         /* Should never be NULL */
 160         WARN_ON(!mrq);
 161
 162         owl_host->mrq = NULL;
 163
 164         if (data)
 165                 dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len,
 166                              owl_host->dma_dir);
 167
 168         /* Finally finish request */
 169         mmc_request_done(owl_host->mmc, mrq);
 170 }
 171
 172 static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host,
 173                              struct mmc_command *cmd,
 174                              struct mmc_data *data)
 175 {
 176         unsigned long timeout;
 177         u32 mode, state, resp[2];
 178         u32 cmd_rsp_mask = 0;
 179
 180         init_completion(&owl_host->sdc_complete);
 181
 182         switch (mmc_resp_type(cmd)) {
 183         case MMC_RSP_NONE:
 184                 mode = OWL_SD_CTL_TM(0);
 185                 break;
 186
 187         case MMC_RSP_R1:
 188                 if (data) {
 189                         if (data->flags & MMC_DATA_READ)
 190                                 mode = OWL_SD_CTL_TM(4);
 191                         else
 192                                 mode = OWL_SD_CTL_TM(5);
 193                 } else {
 194                         mode = OWL_SD_CTL_TM(1);
 195                 }
 196                 cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
 197
 198                 break;
 199
 200         case MMC_RSP_R1B:
 201                 mode = OWL_SD_CTL_TM(3);
 202                 cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
 203                 break;
 204
 205         case MMC_RSP_R2:
 206                 mode = OWL_SD_CTL_TM(2);
 207                 cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
 208                 break;
 209
 210         case MMC_RSP_R3:
 211                 mode = OWL_SD_CTL_TM(1);
 212                 cmd_rsp_mask = OWL_SD_STATE_CLNR;
 213                 break;
 214
 215         default:
 216                 dev_warn(owl_host->dev, "Unknown MMC command\n");
 217                 cmd->error = -EINVAL;
 218                 return;
 219         }
 220
 221         /* Keep current WDELAY and RDELAY */
 222         mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
 223
 224         /* Start to send corresponding command type */
 225         writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);
 226         writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);
 227
 228         /* Set LBE to send clk at the end of last read block */
 229         if (data) {
 230                 mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000);
 231         } else {
 232                 mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE);
 233                 mode |= OWL_SD_CTL_TS;
 234         }
 235
 236         owl_host->cmd = cmd;
 237
 238         /* Start transfer */
 239         writel(mode, owl_host->base + OWL_REG_SD_CTL);
 240
 241         if (data)
 242                 return;
 243
 244         timeout = msecs_to_jiffies(cmd->busy_timeout ? cmd->busy_timeout :
 245                 OWL_CMD_TIMEOUT_MS);
 246
 247         if (!wait_for_completion_timeout(&owl_host->sdc_complete, timeout)) {
 248                 dev_err(owl_host->dev, "CMD interrupt timeout\n");
 249                 cmd->error = -ETIMEDOUT;
 250                 return;
 251         }
 252
 253         state = readl(owl_host->base + OWL_REG_SD_STATE);
 254         if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
 255                 if (cmd_rsp_mask & state) {
 256                         if (state & OWL_SD_STATE_CLNR) {
 257                                 dev_err(owl_host->dev, "Error CMD_NO_RSP\n");
 258                                 cmd->error = -EILSEQ;
 259                                 return;
 260                         }
 261
 262                         if (state & OWL_SD_STATE_CRC7ER) {
 263                                 dev_err(owl_host->dev, "Error CMD_RSP_CRC\n");
 264                                 cmd->error = -EILSEQ;
 265                                 return;
 266                         }
 267                 }
 268
 269                 if (mmc_resp_type(cmd) & MMC_RSP_136) {
 270                         cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
 271                         cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
 272                         cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2);
 273                         cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3);
 274                 } else {
 275                         resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
 276                         resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
 277                         cmd->resp[0] = resp[1] << 24 | resp[0] >> 8;
 278                         cmd->resp[1] = resp[1] >> 8;
 279                 }
 280         }
 281 }
 282
 283 static void owl_mmc_dma_complete(void *param)
 284 {
 285         struct owl_mmc_host *owl_host = param;
 286         struct mmc_data *data = owl_host->data;
 287
 288         if (data)
 289                 complete(&owl_host->dma_complete);
 290 }
 291
 292 static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host,
 293                                 struct mmc_data *data)
 294 {
 295         u32 total;
 296
 297         owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL,
 298                            true);
 299         writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM);
 300         writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE);
 301         total = data->blksz * data->blocks;
 302
 303         if (total < 512)
 304                 writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE);
 305         else
 306                 writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE);
 307
 308         if (data->flags & MMC_DATA_WRITE) {
 309                 owl_host->dma_dir = DMA_TO_DEVICE;
 310                 owl_host->dma_cfg.direction = DMA_MEM_TO_DEV;
 311         } else {
 312                 owl_host->dma_dir = DMA_FROM_DEVICE;
 313                 owl_host->dma_cfg.direction = DMA_DEV_TO_MEM;
 314         }
 315
 316         dma_map_sg(owl_host->dma->device->dev, data->sg,
 317                    data->sg_len, owl_host->dma_dir);
 318
 319         dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg);
 320         owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg,
 321                                                  data->sg_len,
 322                                                  owl_host->dma_cfg.direction,
 323                                                  DMA_PREP_INTERRUPT |
 324                                                  DMA_CTRL_ACK);
 325         if (!owl_host->desc) {
 326                 dev_err(owl_host->dev, "Can't prepare slave sg\n");
 327                 return -EBUSY;
 328         }
 329
 330         owl_host->data = data;
 331
 332         owl_host->desc->callback = owl_mmc_dma_complete;
 333         owl_host->desc->callback_param = (void *)owl_host;
 334         data->error = 0;
 335
 336         return 0;
 337 }
 338
 339 static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 340 {
 341         struct owl_mmc_host *owl_host = mmc_priv(mmc);
 342         struct mmc_data *data = mrq->data;
 343         int ret;
 344
 345         owl_host->mrq = mrq;
 346         if (mrq->data) {
 347                 ret = owl_mmc_prepare_data(owl_host, data);
 348                 if (ret < 0) {
 349                         data->error = ret;
 350                         goto err_out;
 351                 }
 352
 353                 init_completion(&owl_host->dma_complete);
 354                 dmaengine_submit(owl_host->desc);
 355                 dma_async_issue_pending(owl_host->dma);
 356         }
 357
 358         owl_mmc_send_cmd(owl_host, mrq->cmd, data);
 359
 360         if (data) {
 361                 if (!wait_for_completion_timeout(&owl_host->sdc_complete,
 362                                                  10 * HZ)) {
 363                         dev_err(owl_host->dev, "CMD interrupt timeout\n");
 364                         mrq->cmd->error = -ETIMEDOUT;
 365                         dmaengine_terminate_all(owl_host->dma);
 366                         goto err_out;
 367                 }
 368
 369                 if (!wait_for_completion_timeout(&owl_host->dma_complete,
 370                                                  5 * HZ)) {
 371                         dev_err(owl_host->dev, "DMA interrupt timeout\n");
 372                         mrq->cmd->error = -ETIMEDOUT;
 373                         dmaengine_terminate_all(owl_host->dma);
 374                         goto err_out;
 375                 }
 376
 377                 if (data->stop)
 378                         owl_mmc_send_cmd(owl_host, data->stop, NULL);
 379
 380                 data->bytes_xfered = data->blocks * data->blksz;
 381         }
 382
 383 err_out:
 384         owl_mmc_finish_request(owl_host);
 385 }
 386
 387 static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host,
 388                                 unsigned int rate)
 389 {
 390         unsigned long clk_rate;
 391         int ret;
 392         u32 reg;
 393
 394         reg = readl(owl_host->base + OWL_REG_SD_CTL);
 395         reg &= ~OWL_SD_CTL_DELAY_MSK;
 396
 397         /* Set RDELAY and WDELAY based on the clock */
 398         if (rate <= 1000000) {
 399                 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) |
 400                        OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK),
 401                        owl_host->base + OWL_REG_SD_CTL);
 402         } else if ((rate > 1000000) && (rate <= 26000000)) {
 403                 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) |
 404                        OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK),
 405                        owl_host->base + OWL_REG_SD_CTL);
 406         } else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) {
 407                 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) |
 408                        OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK),
 409                        owl_host->base + OWL_REG_SD_CTL);
 410         /* DDR50 mode has special delay chain */
 411         } else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) {
 412                 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) |
 413                        OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50),
 414                        owl_host->base + OWL_REG_SD_CTL);
 415         } else {
 416                 dev_err(owl_host->dev, "SD clock rate not supported\n");
 417                 return -EINVAL;
 418         }
 419
 420         clk_rate = clk_round_rate(owl_host->clk, rate << 1);
 421         ret = clk_set_rate(owl_host->clk, clk_rate);
 422
 423         return ret;
 424 }
 425
 426 static void owl_mmc_set_clk(struct owl_mmc_host *owl_host, struct mmc_ios *ios)
 427 {
 428         if (!ios->clock)
 429                 return;
 430
 431         owl_host->clock = ios->clock;
 432         owl_mmc_set_clk_rate(owl_host, ios->clock);
 433 }
 434
 435 static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host,
 436                                   struct mmc_ios *ios)
 437 {
 438         u32 reg;
 439
 440         reg = readl(owl_host->base + OWL_REG_SD_EN);
 441         reg &= ~0x03;
 442         switch (ios->bus_width) {
 443         case MMC_BUS_WIDTH_1:
 444                 break;
 445         case MMC_BUS_WIDTH_4:
 446                 reg |= OWL_SD_EN_DATAWID(1);
 447                 break;
 448         case MMC_BUS_WIDTH_8:
 449                 reg |= OWL_SD_EN_DATAWID(2);
 450                 break;
 451         }
 452
 453         writel(reg, owl_host->base + OWL_REG_SD_EN);
 454 }
 455
 456 static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host)
 457 {
 458         reset_control_assert(owl_host->reset);
 459         udelay(20);
 460         reset_control_deassert(owl_host->reset);
 461 }
 462
 463 static void owl_mmc_power_on(struct owl_mmc_host *owl_host)
 464 {
 465         u32 mode;
 466
 467         init_completion(&owl_host->sdc_complete);
 468
 469         /* Enable transfer end IRQ */
 470         owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE,
 471                        OWL_SD_STATE_TEIE, true);
 472
 473         /* Send init clk */
 474         mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
 475         mode |= OWL_SD_CTL_TS | OWL_SD_CTL_TCN(5) | OWL_SD_CTL_TM(8);
 476         writel(mode, owl_host->base + OWL_REG_SD_CTL);
 477
 478         if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) {
 479                 dev_err(owl_host->dev, "CMD interrupt timeout\n");
 480                 return;
 481         }
 482 }
 483
 484 static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 485 {
 486         struct owl_mmc_host *owl_host = mmc_priv(mmc);
 487
 488         switch (ios->power_mode) {
 489         case MMC_POWER_UP:
 490                 dev_dbg(owl_host->dev, "Powering card up\n");
 491
 492                 /* Reset the SDC controller to clear all previous states */
 493                 owl_mmc_ctr_reset(owl_host);
 494                 clk_prepare_enable(owl_host->clk);
 495                 writel(OWL_SD_ENABLE | OWL_SD_EN_RESE,
 496                        owl_host->base + OWL_REG_SD_EN);
 497
 498                 break;
 499
 500         case MMC_POWER_ON:
 501                 dev_dbg(owl_host->dev, "Powering card on\n");
 502                 owl_mmc_power_on(owl_host);
 503
 504                 break;
 505
 506         case MMC_POWER_OFF:
 507                 dev_dbg(owl_host->dev, "Powering card off\n");
 508                 clk_disable_unprepare(owl_host->clk);
 509
 510                 return;
 511
 512         default:
 513                 dev_dbg(owl_host->dev, "Ignoring unknown card power state\n");
 514                 break;
 515         }
 516
 517         if (ios->clock != owl_host->clock)
 518                 owl_mmc_set_clk(owl_host, ios);
 519
 520         owl_mmc_set_bus_width(owl_host, ios);
 521
 522         /* Enable DDR mode if requested */
 523         if (ios->timing == MMC_TIMING_UHS_DDR50) {
 524                 owl_host->ddr_50 = true;
 525                 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
 526                                OWL_SD_EN_DDREN, true);
 527         } else {
 528                 owl_host->ddr_50 = false;
 529         }
 530 }
 531
 532 static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc,
 533                                                struct mmc_ios *ios)
 534 {
 535         struct owl_mmc_host *owl_host = mmc_priv(mmc);
 536
 537         /* It is enough to change the pad ctrl bit for voltage switch */
 538         switch (ios->signal_voltage) {
 539         case MMC_SIGNAL_VOLTAGE_330:
 540                 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
 541                                OWL_SD_EN_S18EN, false);
 542                 break;
 543         case MMC_SIGNAL_VOLTAGE_180:
 544                 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
 545                                OWL_SD_EN_S18EN, true);
 546                 break;
 547         default:
 548                 return -ENOTSUPP;
 549         }
 550
 551         return 0;
 552 }
 553
 554 static const struct mmc_host_ops owl_mmc_ops = {
 555         .request        = owl_mmc_request,
 556         .set_ios        = owl_mmc_set_ios,
 557         .get_ro         = mmc_gpio_get_ro,
 558         .get_cd         = mmc_gpio_get_cd,
 559         .start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch,
 560 };
 561
 562 static int owl_mmc_probe(struct platform_device *pdev)
 563 {
 564         struct owl_mmc_host *owl_host;
 565         struct mmc_host *mmc;
 566         struct resource *res;
 567         int ret;
 568
 569         mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev);
 570         if (!mmc) {
 571                 dev_err(&pdev->dev, "mmc alloc host failed\n");
 572                 return -ENOMEM;
 573         }
 574         platform_set_drvdata(pdev, mmc);
 575
 576         owl_host = mmc_priv(mmc);
 577         owl_host->dev = &pdev->dev;
 578         owl_host->mmc = mmc;
 579         spin_lock_init(&owl_host->lock);
 580
 581         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 582         owl_host->base = devm_ioremap_resource(&pdev->dev, res);
 583         if (IS_ERR(owl_host->base)) {
 584                 ret = PTR_ERR(owl_host->base);
 585                 goto err_free_host;
 586         }
 587
 588         owl_host->clk = devm_clk_get(&pdev->dev, NULL);
 589         if (IS_ERR(owl_host->clk)) {
 590                 dev_err(&pdev->dev, "No clock defined\n");
 591                 ret = PTR_ERR(owl_host->clk);
 592                 goto err_free_host;
 593         }
 594
 595         owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 596         if (IS_ERR(owl_host->reset)) {
 597                 dev_err(&pdev->dev, "Could not get reset control\n");
 598                 ret = PTR_ERR(owl_host->reset);
 599                 goto err_free_host;
 600         }
 601
 602         mmc->ops                = &owl_mmc_ops;
 603         mmc->max_blk_count      = 512;
 604         mmc->max_blk_size       = 512;
 605         mmc->max_segs           = 256;
 606         mmc->max_seg_size       = 262144;
 607         mmc->max_req_size       = 262144;
 608         /* 100kHz ~ 52MHz */
 609         mmc->f_min              = 100000;
 610         mmc->f_max              = 52000000;
 611         mmc->caps              |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
 612                                   MMC_CAP_4_BIT_DATA;
 613         mmc->caps2              = (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO);
 614         mmc->ocr_avail          = MMC_VDD_32_33 | MMC_VDD_33_34 |
 615                                   MMC_VDD_165_195;
 616
 617         ret = mmc_of_parse(mmc);
 618         if (ret)
 619                 goto err_free_host;
 620
 621         pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 622         pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 623         owl_host->dma = dma_request_chan(&pdev->dev, "mmc");
 624         if (IS_ERR(owl_host->dma)) {
 625                 dev_err(owl_host->dev, "Failed to get external DMA channel.\n");
 626                 ret = PTR_ERR(owl_host->dma);
 627                 goto err_free_host;
 628         }
 629
 630         dev_info(&pdev->dev, "Using %s for DMA transfers\n",
 631                  dma_chan_name(owl_host->dma));
 632
 633         owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT;
 634         owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT;
 635         owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 636         owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 637         owl_host->dma_cfg.device_fc = false;
 638
 639         owl_host->irq = platform_get_irq(pdev, 0);
 640         if (owl_host->irq < 0) {
 641                 ret = -EINVAL;
 642                 goto err_release_channel;
 643         }
 644
 645         ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler,
 646                                0, dev_name(&pdev->dev), owl_host);
 647         if (ret) {
 648                 dev_err(&pdev->dev, "Failed to request irq %d\n",
 649                         owl_host->irq);
 650                 goto err_release_channel;
 651         }
 652
 653         ret = mmc_add_host(mmc);
 654         if (ret) {
 655                 dev_err(&pdev->dev, "Failed to add host\n");
 656                 goto err_release_channel;
 657         }
 658
 659         dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n");
 660
 661         return 0;
 662
 663 err_release_channel:
 664         dma_release_channel(owl_host->dma);
 665 err_free_host:
 666         mmc_free_host(mmc);
 667
 668         return ret;
 669 }
 670
 671 static int owl_mmc_remove(struct platform_device *pdev)
 672 {
 673         struct mmc_host *mmc = platform_get_drvdata(pdev);
 674         struct owl_mmc_host *owl_host = mmc_priv(mmc);
 675
 676         mmc_remove_host(mmc);
 677         disable_irq(owl_host->irq);
 678         dma_release_channel(owl_host->dma);
 679         mmc_free_host(mmc);
 680
 681         return 0;
 682 }
 683
 684 static const struct of_device_id owl_mmc_of_match[] = {
 685         {.compatible = "actions,owl-mmc",},
 686         { /* sentinel */ }
 687 };
 688 MODULE_DEVICE_TABLE(of, owl_mmc_of_match);
 689
 690 static struct platform_driver owl_mmc_driver = {
 691         .driver = {
 692                 .name   = "owl_mmc",
 693                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
 694                 .of_match_table = owl_mmc_of_match,
 695         },
 696         .probe          = owl_mmc_probe,
 697         .remove         = owl_mmc_remove,
 698 };
 699 module_platform_driver(owl_mmc_driver);
 700
 701 MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver");
 702 MODULE_AUTHOR("Actions Semi");
 703 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
 704 MODULE_LICENSE("GPL");