1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
4 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
6 * Copyright 2008 Embedded Alley Solutions, Inc.
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/ioport.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmaengine.h>
19 #include <linux/dma/mxs-dma.h>
20 #include <linux/highmem.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/completion.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/mmc.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/module.h>
30 #include <linux/stmp_device.h>
31 #include <linux/spi/mxs-spi.h>
33 #define DRIVER_NAME "mxs-mmc"
35 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
36 BM_SSP_CTRL1_RESP_ERR_IRQ | \
37 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
38 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
39 BM_SSP_CTRL1_DATA_CRC_IRQ | \
40 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
41 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
42 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
44 /* card detect polling timeout */
45 #define MXS_MMC_DETECT_TIMEOUT (HZ/2)
51 struct mmc_request *mrq;
52 struct mmc_command *cmd;
53 struct mmc_data *data;
55 unsigned char bus_width;
61 static int mxs_mmc_get_cd(struct mmc_host *mmc)
63 struct mxs_mmc_host *host = mmc_priv(mmc);
64 struct mxs_ssp *ssp = &host->ssp;
70 ret = mmc_gpio_get_cd(mmc);
74 present = mmc->caps & MMC_CAP_NEEDS_POLL ||
75 !(readl(ssp->base + HW_SSP_STATUS(ssp)) &
76 BM_SSP_STATUS_CARD_DETECT);
78 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
84 static int mxs_mmc_reset(struct mxs_mmc_host *host)
86 struct mxs_ssp *ssp = &host->ssp;
90 ret = stmp_reset_block(ssp->base);
94 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
95 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
96 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
97 BM_SSP_CTRL1_DMA_ENABLE |
98 BM_SSP_CTRL1_POLARITY |
99 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
100 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
101 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
102 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
103 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
105 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
106 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
107 BF_SSP(0, TIMING_CLOCK_RATE),
108 ssp->base + HW_SSP_TIMING(ssp));
110 if (host->sdio_irq_en) {
111 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
112 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
115 writel(ctrl0, ssp->base + HW_SSP_CTRL0);
116 writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp));
120 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
121 struct mmc_command *cmd);
123 static void mxs_mmc_request_done(struct mxs_mmc_host *host)
125 struct mmc_command *cmd = host->cmd;
126 struct mmc_data *data = host->data;
127 struct mmc_request *mrq = host->mrq;
128 struct mxs_ssp *ssp = &host->ssp;
130 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
131 if (mmc_resp_type(cmd) & MMC_RSP_136) {
132 cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
133 cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp));
134 cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp));
135 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp));
137 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
141 if (cmd == mrq->sbc) {
142 /* Finished CMD23, now send actual command. */
143 mxs_mmc_start_cmd(host, mrq->cmd);
146 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
147 data->sg_len, ssp->dma_dir);
149 * If there was an error on any block, we mark all
150 * data blocks as being in error.
153 data->bytes_xfered = data->blocks * data->blksz;
155 data->bytes_xfered = 0;
158 if (data->stop && (data->error || !mrq->sbc)) {
159 mxs_mmc_start_cmd(host, mrq->stop);
165 mmc_request_done(host->mmc, mrq);
168 static void mxs_mmc_dma_irq_callback(void *param)
170 struct mxs_mmc_host *host = param;
172 mxs_mmc_request_done(host);
175 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
177 struct mxs_mmc_host *host = dev_id;
178 struct mmc_command *cmd = host->cmd;
179 struct mmc_data *data = host->data;
180 struct mxs_ssp *ssp = &host->ssp;
183 spin_lock(&host->lock);
185 stat = readl(ssp->base + HW_SSP_CTRL1(ssp));
186 writel(stat & MXS_MMC_IRQ_BITS,
187 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
189 spin_unlock(&host->lock);
191 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
192 mmc_signal_sdio_irq(host->mmc);
194 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
195 cmd->error = -ETIMEDOUT;
196 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
200 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
201 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
202 data->error = -ETIMEDOUT;
203 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
204 data->error = -EILSEQ;
205 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
206 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
213 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
214 struct mxs_mmc_host *host, unsigned long flags)
216 struct mxs_ssp *ssp = &host->ssp;
217 struct dma_async_tx_descriptor *desc;
218 struct mmc_data *data = host->data;
219 struct scatterlist * sgl;
224 dma_map_sg(mmc_dev(host->mmc), data->sg,
225 data->sg_len, ssp->dma_dir);
227 sg_len = data->sg_len;
230 sgl = (struct scatterlist *) ssp->ssp_pio_words;
231 sg_len = SSP_PIO_NUM;
234 desc = dmaengine_prep_slave_sg(ssp->dmach,
235 sgl, sg_len, ssp->slave_dirn, flags);
237 desc->callback = mxs_mmc_dma_irq_callback;
238 desc->callback_param = host;
241 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
242 data->sg_len, ssp->dma_dir);
248 static void mxs_mmc_bc(struct mxs_mmc_host *host)
250 struct mxs_ssp *ssp = &host->ssp;
251 struct mmc_command *cmd = host->cmd;
252 struct dma_async_tx_descriptor *desc;
253 u32 ctrl0, cmd0, cmd1;
255 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
256 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
259 if (host->sdio_irq_en) {
260 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
261 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
264 ssp->ssp_pio_words[0] = ctrl0;
265 ssp->ssp_pio_words[1] = cmd0;
266 ssp->ssp_pio_words[2] = cmd1;
267 ssp->dma_dir = DMA_NONE;
268 ssp->slave_dirn = DMA_TRANS_NONE;
269 desc = mxs_mmc_prep_dma(host, MXS_DMA_CTRL_WAIT4END);
273 dmaengine_submit(desc);
274 dma_async_issue_pending(ssp->dmach);
278 dev_warn(mmc_dev(host->mmc),
279 "%s: failed to prep dma\n", __func__);
282 static void mxs_mmc_ac(struct mxs_mmc_host *host)
284 struct mxs_ssp *ssp = &host->ssp;
285 struct mmc_command *cmd = host->cmd;
286 struct dma_async_tx_descriptor *desc;
287 u32 ignore_crc, get_resp, long_resp;
288 u32 ctrl0, cmd0, cmd1;
290 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
291 0 : BM_SSP_CTRL0_IGNORE_CRC;
292 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
293 BM_SSP_CTRL0_GET_RESP : 0;
294 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
295 BM_SSP_CTRL0_LONG_RESP : 0;
297 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
298 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
301 if (cmd->opcode == MMC_STOP_TRANSMISSION)
302 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
304 if (host->sdio_irq_en) {
305 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
306 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
309 ssp->ssp_pio_words[0] = ctrl0;
310 ssp->ssp_pio_words[1] = cmd0;
311 ssp->ssp_pio_words[2] = cmd1;
312 ssp->dma_dir = DMA_NONE;
313 ssp->slave_dirn = DMA_TRANS_NONE;
314 desc = mxs_mmc_prep_dma(host, MXS_DMA_CTRL_WAIT4END);
318 dmaengine_submit(desc);
319 dma_async_issue_pending(ssp->dmach);
323 dev_warn(mmc_dev(host->mmc),
324 "%s: failed to prep dma\n", __func__);
327 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
329 const unsigned int ssp_timeout_mul = 4096;
331 * Calculate ticks in ms since ns are large numbers
334 const unsigned int clock_per_ms = clock_rate / 1000;
335 const unsigned int ms = ns / 1000;
336 const unsigned int ticks = ms * clock_per_ms;
337 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
339 WARN_ON(ssp_ticks == 0);
343 static void mxs_mmc_adtc(struct mxs_mmc_host *host)
345 struct mmc_command *cmd = host->cmd;
346 struct mmc_data *data = cmd->data;
347 struct dma_async_tx_descriptor *desc;
348 struct scatterlist *sgl = data->sg, *sg;
349 unsigned int sg_len = data->sg_len;
352 unsigned short dma_data_dir, timeout;
353 enum dma_transfer_direction slave_dirn;
354 unsigned int data_size = 0, log2_blksz;
355 unsigned int blocks = data->blocks;
357 struct mxs_ssp *ssp = &host->ssp;
359 u32 ignore_crc, get_resp, long_resp, read;
360 u32 ctrl0, cmd0, cmd1, val;
362 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
363 0 : BM_SSP_CTRL0_IGNORE_CRC;
364 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
365 BM_SSP_CTRL0_GET_RESP : 0;
366 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
367 BM_SSP_CTRL0_LONG_RESP : 0;
369 if (data->flags & MMC_DATA_WRITE) {
370 dma_data_dir = DMA_TO_DEVICE;
371 slave_dirn = DMA_MEM_TO_DEV;
374 dma_data_dir = DMA_FROM_DEVICE;
375 slave_dirn = DMA_DEV_TO_MEM;
376 read = BM_SSP_CTRL0_READ;
379 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
380 ignore_crc | get_resp | long_resp |
381 BM_SSP_CTRL0_DATA_XFER | read |
382 BM_SSP_CTRL0_WAIT_FOR_IRQ |
385 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
387 /* get logarithm to base 2 of block size for setting register */
388 log2_blksz = ilog2(data->blksz);
391 * take special care of the case that data size from data->sg
392 * is not equal to blocks x blksz
394 for_each_sg(sgl, sg, sg_len, i)
395 data_size += sg->length;
397 if (data_size != data->blocks * data->blksz)
400 /* xfer count, block size and count need to be set differently */
401 if (ssp_is_old(ssp)) {
402 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
403 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
404 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
406 writel(data_size, ssp->base + HW_SSP_XFER_SIZE);
407 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
408 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
409 ssp->base + HW_SSP_BLOCK_SIZE);
412 if (cmd->opcode == SD_IO_RW_EXTENDED)
413 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
417 if (host->sdio_irq_en) {
418 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
419 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
422 /* set the timeout count */
423 timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns);
424 val = readl(ssp->base + HW_SSP_TIMING(ssp));
425 val &= ~(BM_SSP_TIMING_TIMEOUT);
426 val |= BF_SSP(timeout, TIMING_TIMEOUT);
427 writel(val, ssp->base + HW_SSP_TIMING(ssp));
430 ssp->ssp_pio_words[0] = ctrl0;
431 ssp->ssp_pio_words[1] = cmd0;
432 ssp->ssp_pio_words[2] = cmd1;
433 ssp->dma_dir = DMA_NONE;
434 ssp->slave_dirn = DMA_TRANS_NONE;
435 desc = mxs_mmc_prep_dma(host, 0);
440 WARN_ON(host->data != NULL);
442 ssp->dma_dir = dma_data_dir;
443 ssp->slave_dirn = slave_dirn;
444 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | MXS_DMA_CTRL_WAIT4END);
448 dmaengine_submit(desc);
449 dma_async_issue_pending(ssp->dmach);
452 dev_warn(mmc_dev(host->mmc),
453 "%s: failed to prep dma\n", __func__);
456 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
457 struct mmc_command *cmd)
461 switch (mmc_cmd_type(cmd)) {
475 dev_warn(mmc_dev(host->mmc),
476 "%s: unknown MMC command\n", __func__);
481 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
483 struct mxs_mmc_host *host = mmc_priv(mmc);
485 WARN_ON(host->mrq != NULL);
489 mxs_mmc_start_cmd(host, mrq->sbc);
491 mxs_mmc_start_cmd(host, mrq->cmd);
494 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
496 struct mxs_mmc_host *host = mmc_priv(mmc);
498 if (ios->bus_width == MMC_BUS_WIDTH_8)
500 else if (ios->bus_width == MMC_BUS_WIDTH_4)
506 mxs_ssp_set_clk_rate(&host->ssp, ios->clock);
509 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
511 struct mxs_mmc_host *host = mmc_priv(mmc);
512 struct mxs_ssp *ssp = &host->ssp;
515 spin_lock_irqsave(&host->lock, flags);
517 host->sdio_irq_en = enable;
520 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
521 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
522 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
523 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET);
525 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
526 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
527 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
528 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
531 spin_unlock_irqrestore(&host->lock, flags);
533 if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) &
534 BM_SSP_STATUS_SDIO_IRQ)
535 mmc_signal_sdio_irq(host->mmc);
539 static const struct mmc_host_ops mxs_mmc_ops = {
540 .request = mxs_mmc_request,
541 .get_ro = mmc_gpio_get_ro,
542 .get_cd = mxs_mmc_get_cd,
543 .set_ios = mxs_mmc_set_ios,
544 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
547 static const struct of_device_id mxs_mmc_dt_ids[] = {
548 { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, },
549 { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, },
552 MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
554 static void mxs_mmc_regulator_disable(void *regulator)
556 regulator_disable(regulator);
559 static int mxs_mmc_probe(struct platform_device *pdev)
561 struct device_node *np = pdev->dev.of_node;
562 struct mxs_mmc_host *host;
563 struct mmc_host *mmc;
564 int ret = 0, irq_err;
565 struct regulator *reg_vmmc;
568 irq_err = platform_get_irq(pdev, 0);
572 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
576 host = mmc_priv(mmc);
578 ssp->dev = &pdev->dev;
579 ssp->base = devm_platform_ioremap_resource(pdev, 0);
580 if (IS_ERR(ssp->base)) {
581 ret = PTR_ERR(ssp->base);
585 ssp->devid = (enum mxs_ssp_id)of_device_get_match_data(&pdev->dev);
588 host->sdio_irq_en = 0;
590 reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc");
591 if (!IS_ERR(reg_vmmc)) {
592 ret = regulator_enable(reg_vmmc);
595 "Failed to enable vmmc regulator: %d\n", ret);
599 ret = devm_add_action_or_reset(&pdev->dev, mxs_mmc_regulator_disable,
605 ssp->clk = devm_clk_get(&pdev->dev, NULL);
606 if (IS_ERR(ssp->clk)) {
607 ret = PTR_ERR(ssp->clk);
610 ret = clk_prepare_enable(ssp->clk);
614 ret = mxs_mmc_reset(host);
616 dev_err(&pdev->dev, "Failed to reset mmc: %d\n", ret);
617 goto out_clk_disable;
620 ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
621 if (IS_ERR(ssp->dmach)) {
622 dev_err(mmc_dev(host->mmc),
623 "%s: failed to request dma\n", __func__);
624 ret = PTR_ERR(ssp->dmach);
625 goto out_clk_disable;
628 /* set mmc core parameters */
629 mmc->ops = &mxs_mmc_ops;
630 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
631 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL | MMC_CAP_CMD23;
633 host->broken_cd = of_property_read_bool(np, "broken-cd");
636 mmc->f_max = 288000000;
638 ret = mmc_of_parse(mmc);
642 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
645 mmc->max_blk_size = 1 << 0xf;
646 mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff;
647 mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff;
648 mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev);
650 platform_set_drvdata(pdev, mmc);
652 spin_lock_init(&host->lock);
654 ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
655 dev_name(&pdev->dev), host);
659 ret = mmc_add_host(mmc);
663 dev_info(mmc_dev(host->mmc), "initialized\n");
668 dma_release_channel(ssp->dmach);
670 clk_disable_unprepare(ssp->clk);
676 static void mxs_mmc_remove(struct platform_device *pdev)
678 struct mmc_host *mmc = platform_get_drvdata(pdev);
679 struct mxs_mmc_host *host = mmc_priv(mmc);
680 struct mxs_ssp *ssp = &host->ssp;
682 mmc_remove_host(mmc);
685 dma_release_channel(ssp->dmach);
687 clk_disable_unprepare(ssp->clk);
692 #ifdef CONFIG_PM_SLEEP
693 static int mxs_mmc_suspend(struct device *dev)
695 struct mmc_host *mmc = dev_get_drvdata(dev);
696 struct mxs_mmc_host *host = mmc_priv(mmc);
697 struct mxs_ssp *ssp = &host->ssp;
699 clk_disable_unprepare(ssp->clk);
703 static int mxs_mmc_resume(struct device *dev)
705 struct mmc_host *mmc = dev_get_drvdata(dev);
706 struct mxs_mmc_host *host = mmc_priv(mmc);
707 struct mxs_ssp *ssp = &host->ssp;
709 return clk_prepare_enable(ssp->clk);
713 static SIMPLE_DEV_PM_OPS(mxs_mmc_pm_ops, mxs_mmc_suspend, mxs_mmc_resume);
715 static struct platform_driver mxs_mmc_driver = {
716 .probe = mxs_mmc_probe,
717 .remove_new = mxs_mmc_remove,
720 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
721 .pm = &mxs_mmc_pm_ops,
722 .of_match_table = mxs_mmc_dt_ids,
726 module_platform_driver(mxs_mmc_driver);
728 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
729 MODULE_AUTHOR("Freescale Semiconductor");
730 MODULE_LICENSE("GPL");
731 MODULE_ALIAS("platform:" DRIVER_NAME);