2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
4 * Copyright (C) 2007 Google Inc,
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 * Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Author: San Mehat (san@android.com)
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/highmem.h>
27 #include <linux/log2.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/mmc/sdio.h>
31 #include <linux/clk.h>
32 #include <linux/scatterlist.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/debugfs.h>
37 #include <linux/memory.h>
38 #include <linux/gfp.h>
40 #include <asm/cacheflush.h>
41 #include <asm/div64.h>
42 #include <asm/sizes.h>
45 #include <mach/msm_iomap.h>
51 #define DRIVER_NAME "msm-sdcc"
53 #define BUSCLK_PWRSAVE 1
54 #define BUSCLK_TIMEOUT (HZ)
55 static unsigned int msmsdcc_fmin = 144000;
56 static unsigned int msmsdcc_fmax = 50000000;
57 static unsigned int msmsdcc_4bit = 1;
58 static unsigned int msmsdcc_pwrsave = 1;
59 static unsigned int msmsdcc_piopoll = 1;
60 static unsigned int msmsdcc_sdioirq;
62 #define PIO_SPINMAX 30
63 #define CMD_SPINMAX 20
67 msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
69 WARN_ON(!host->clks_on);
71 BUG_ON(host->curr.mrq);
74 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
76 del_timer_sync(&host->busclk_timer);
77 /* Need to check clks_on again in case the busclk
81 clk_disable(host->clk);
82 clk_disable(host->pclk);
89 msmsdcc_enable_clocks(struct msmsdcc_host *host)
93 del_timer_sync(&host->busclk_timer);
96 rc = clk_enable(host->pclk);
99 rc = clk_enable(host->clk);
101 clk_disable(host->pclk);
104 udelay(1 + ((3 * USEC_PER_SEC) /
105 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
111 static inline unsigned int
112 msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
114 return readl(host->base + reg);
118 msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
120 writel(data, host->base + reg);
121 /* 3 clk delay required! */
122 udelay(1 + ((3 * USEC_PER_SEC) /
123 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
127 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
130 static void msmsdcc_reset_and_restore(struct msmsdcc_host *host)
136 /* Save the controller state */
137 mci_clk = readl(host->base + MMCICLOCK);
138 mci_mask0 = readl(host->base + MMCIMASK0);
140 /* Reset the controller */
141 ret = clk_reset(host->clk, CLK_RESET_ASSERT);
143 pr_err("%s: Clock assert failed at %u Hz with err %d\n",
144 mmc_hostname(host->mmc), host->clk_rate, ret);
146 ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
148 pr_err("%s: Clock deassert failed at %u Hz with err %d\n",
149 mmc_hostname(host->mmc), host->clk_rate, ret);
151 pr_info("%s: Controller has been re-initialiazed\n",
152 mmc_hostname(host->mmc));
154 /* Restore the contoller state */
155 writel(host->pwr, host->base + MMCIPOWER);
156 writel(mci_clk, host->base + MMCICLOCK);
157 writel(mci_mask0, host->base + MMCIMASK0);
158 ret = clk_set_rate(host->clk, host->clk_rate);
160 pr_err("%s: Failed to set clk rate %u Hz (%d)\n",
161 mmc_hostname(host->mmc), host->clk_rate, ret);
165 msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
167 BUG_ON(host->curr.data);
169 host->curr.mrq = NULL;
170 host->curr.cmd = NULL;
173 mrq->data->bytes_xfered = host->curr.data_xfered;
174 if (mrq->cmd->error == -ETIMEDOUT)
178 msmsdcc_disable_clocks(host, 1);
181 * Need to drop the host lock here; mmc_request_done may call
182 * back into the driver...
184 spin_unlock(&host->lock);
185 mmc_request_done(host->mmc, mrq);
186 spin_lock(&host->lock);
190 msmsdcc_stop_data(struct msmsdcc_host *host)
192 host->curr.data = NULL;
193 host->curr.got_dataend = 0;
196 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
198 return host->memres->start + MMCIFIFO;
202 msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
203 msmsdcc_writel(host, arg, MMCIARGUMENT);
204 msmsdcc_writel(host, c, MMCICOMMAND);
208 msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
210 struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
212 msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
213 msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
215 msmsdcc_writel(host, host->cmd_pio_irqmask, MMCIMASK1);
216 msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
219 msmsdcc_start_command_exec(host,
220 (u32) host->cmd_cmd->arg,
223 host->dma.active = 1;
227 msmsdcc_dma_complete_tlet(unsigned long data)
229 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
231 struct mmc_request *mrq;
232 struct msm_dmov_errdata err;
234 spin_lock_irqsave(&host->lock, flags);
235 host->dma.active = 0;
238 mrq = host->curr.mrq;
242 if (!(host->dma.result & DMOV_RSLT_VALID)) {
243 pr_err("msmsdcc: Invalid DataMover result\n");
247 if (host->dma.result & DMOV_RSLT_DONE) {
248 host->curr.data_xfered = host->curr.xfer_size;
251 if (host->dma.result & DMOV_RSLT_ERROR)
252 pr_err("%s: DMA error (0x%.8x)\n",
253 mmc_hostname(host->mmc), host->dma.result);
254 if (host->dma.result & DMOV_RSLT_FLUSH)
255 pr_err("%s: DMA channel flushed (0x%.8x)\n",
256 mmc_hostname(host->mmc), host->dma.result);
258 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
259 err.flush[0], err.flush[1], err.flush[2],
260 err.flush[3], err.flush[4], err.flush[5]);
262 msmsdcc_reset_and_restore(host);
263 if (!mrq->data->error)
264 mrq->data->error = -EIO;
266 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
269 if (host->curr.user_pages) {
270 struct scatterlist *sg = host->dma.sg;
273 for (i = 0; i < host->dma.num_ents; i++)
274 flush_dcache_page(sg_page(sg++));
280 if (host->curr.got_dataend || mrq->data->error) {
283 * If we've already gotten our DATAEND / DATABLKEND
284 * for this request, then complete it through here.
286 msmsdcc_stop_data(host);
288 if (!mrq->data->error)
289 host->curr.data_xfered = host->curr.xfer_size;
290 if (!mrq->data->stop || mrq->cmd->error) {
291 host->curr.mrq = NULL;
292 host->curr.cmd = NULL;
293 mrq->data->bytes_xfered = host->curr.data_xfered;
295 spin_unlock_irqrestore(&host->lock, flags);
297 msmsdcc_disable_clocks(host, 1);
299 mmc_request_done(host->mmc, mrq);
302 msmsdcc_start_command(host, mrq->data->stop, 0);
306 spin_unlock_irqrestore(&host->lock, flags);
311 msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
313 struct msm_dmov_errdata *err)
315 struct msmsdcc_dma_data *dma_data =
316 container_of(cmd, struct msmsdcc_dma_data, hdr);
317 struct msmsdcc_host *host = dma_data->host;
319 dma_data->result = result;
321 memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata));
323 tasklet_schedule(&host->dma_tlet);
326 static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
328 if (host->dma.channel == -1)
331 if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
333 if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
338 static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
340 struct msmsdcc_nc_dmadata *nc;
346 struct scatterlist *sg = data->sg;
348 rc = validate_dma(host, data);
352 host->dma.sg = data->sg;
353 host->dma.num_ents = data->sg_len;
355 BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
359 switch (host->pdev_id) {
361 crci = MSMSDCC_CRCI_SDC1;
364 crci = MSMSDCC_CRCI_SDC2;
367 crci = MSMSDCC_CRCI_SDC3;
370 crci = MSMSDCC_CRCI_SDC4;
374 host->dma.num_ents = 0;
378 if (data->flags & MMC_DATA_READ)
379 host->dma.dir = DMA_FROM_DEVICE;
381 host->dma.dir = DMA_TO_DEVICE;
383 host->curr.user_pages = 0;
387 /* location of command block must be 64 bit aligned */
388 BUG_ON(host->dma.cmd_busaddr & 0x07);
390 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
391 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
392 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
393 host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
395 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
396 host->dma.num_ents, host->dma.dir);
398 printk(KERN_ERR "%s: Unable to map in all sg elements\n",
399 mmc_hostname(host->mmc));
401 host->dma.num_ents = 0;
405 for_each_sg(host->dma.sg, sg, n, i) {
407 box->cmd = CMD_MODE_BOX;
411 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
412 (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
413 (sg_dma_len(sg) / MCI_FIFOSIZE) ;
415 if (data->flags & MMC_DATA_READ) {
416 box->src_row_addr = msmsdcc_fifo_addr(host);
417 box->dst_row_addr = sg_dma_address(sg);
419 box->src_dst_len = (MCI_FIFOSIZE << 16) |
421 box->row_offset = MCI_FIFOSIZE;
423 box->num_rows = rows * ((1 << 16) + 1);
424 box->cmd |= CMD_SRC_CRCI(crci);
426 box->src_row_addr = sg_dma_address(sg);
427 box->dst_row_addr = msmsdcc_fifo_addr(host);
429 box->src_dst_len = (MCI_FIFOSIZE << 16) |
431 box->row_offset = (MCI_FIFOSIZE << 16);
433 box->num_rows = rows * ((1 << 16) + 1);
434 box->cmd |= CMD_DST_CRCI(crci);
443 snoop_cccr_abort(struct mmc_command *cmd)
445 if ((cmd->opcode == 52) &&
446 (cmd->arg & 0x80000000) &&
447 (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
453 msmsdcc_start_command_deferred(struct msmsdcc_host *host,
454 struct mmc_command *cmd, u32 *c)
456 *c |= (cmd->opcode | MCI_CPSM_ENABLE);
458 if (cmd->flags & MMC_RSP_PRESENT) {
459 if (cmd->flags & MMC_RSP_136)
460 *c |= MCI_CPSM_LONGRSP;
461 *c |= MCI_CPSM_RESPONSE;
465 *c |= MCI_CPSM_INTERRUPT;
467 if ((((cmd->opcode == 17) || (cmd->opcode == 18)) ||
468 ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
470 *c |= MCI_CSPM_DATCMD;
472 if (host->prog_scan && (cmd->opcode == 12)) {
473 *c |= MCI_CPSM_PROGENA;
474 host->prog_enable = true;
477 if (cmd == cmd->mrq->stop)
478 *c |= MCI_CSPM_MCIABORT;
480 if (snoop_cccr_abort(cmd))
481 *c |= MCI_CSPM_MCIABORT;
483 if (host->curr.cmd != NULL) {
484 printk(KERN_ERR "%s: Overlapping command requests\n",
485 mmc_hostname(host->mmc));
487 host->curr.cmd = cmd;
491 msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
492 struct mmc_command *cmd, u32 c)
494 unsigned int datactrl, timeout;
495 unsigned long long clks;
496 unsigned int pio_irqmask = 0;
498 host->curr.data = data;
499 host->curr.xfer_size = data->blksz * data->blocks;
500 host->curr.xfer_remain = host->curr.xfer_size;
501 host->curr.data_xfered = 0;
502 host->curr.got_dataend = 0;
504 memset(&host->pio, 0, sizeof(host->pio));
506 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
508 if (!msmsdcc_config_dma(host, data))
509 datactrl |= MCI_DPSM_DMAENABLE;
511 host->pio.sg = data->sg;
512 host->pio.sg_len = data->sg_len;
513 host->pio.sg_off = 0;
515 if (data->flags & MMC_DATA_READ) {
516 pio_irqmask = MCI_RXFIFOHALFFULLMASK;
517 if (host->curr.xfer_remain < MCI_FIFOSIZE)
518 pio_irqmask |= MCI_RXDATAAVLBLMASK;
520 pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
523 if (data->flags & MMC_DATA_READ)
524 datactrl |= MCI_DPSM_DIRECTION;
526 clks = (unsigned long long)data->timeout_ns * host->clk_rate;
527 do_div(clks, NSEC_PER_SEC);
528 timeout = data->timeout_clks + (unsigned int)clks*2 ;
530 if (datactrl & MCI_DPSM_DMAENABLE) {
531 /* Save parameters for the exec function */
532 host->cmd_timeout = timeout;
533 host->cmd_pio_irqmask = pio_irqmask;
534 host->cmd_datactrl = datactrl;
537 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
538 host->dma.hdr.data = (void *)host;
542 msmsdcc_start_command_deferred(host, cmd, &c);
545 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
546 if (data->flags & MMC_DATA_WRITE)
547 host->prog_scan = true;
549 msmsdcc_writel(host, timeout, MMCIDATATIMER);
551 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
553 msmsdcc_writel(host, pio_irqmask, MMCIMASK1);
554 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
557 /* Daisy-chain the command if requested */
558 msmsdcc_start_command(host, cmd, c);
564 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
566 if (cmd == cmd->mrq->stop)
567 c |= MCI_CSPM_MCIABORT;
571 msmsdcc_start_command_deferred(host, cmd, &c);
572 msmsdcc_start_command_exec(host, cmd->arg, c);
576 msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
579 if (status & MCI_DATACRCFAIL) {
580 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
581 pr_err("%s: opcode 0x%.8x\n", __func__,
582 data->mrq->cmd->opcode);
583 pr_err("%s: blksz %d, blocks %d\n", __func__,
584 data->blksz, data->blocks);
585 data->error = -EILSEQ;
586 } else if (status & MCI_DATATIMEOUT) {
587 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
588 data->error = -ETIMEDOUT;
589 } else if (status & MCI_RXOVERRUN) {
590 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
592 } else if (status & MCI_TXUNDERRUN) {
593 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
596 pr_err("%s: Unknown error (0x%.8x)\n",
597 mmc_hostname(host->mmc), status);
604 msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
606 uint32_t *ptr = (uint32_t *) buffer;
610 remain = ((remain >> 2) + 1) << 2;
612 while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
613 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
615 count += sizeof(uint32_t);
617 remain -= sizeof(uint32_t);
625 msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
626 unsigned int remain, u32 status)
628 void __iomem *base = host->base;
632 unsigned int count, maxcnt, sz;
634 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
636 count = min(remain, maxcnt);
638 sz = count % 4 ? (count >> 2) + 1 : (count >> 2);
639 writesl(base + MMCIFIFO, ptr, sz);
646 status = msmsdcc_readl(host, MMCISTATUS);
647 } while (status & MCI_TXFIFOHALFEMPTY);
653 msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
656 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
665 msmsdcc_pio_irq(int irq, void *dev_id)
667 struct msmsdcc_host *host = dev_id;
670 status = msmsdcc_readl(host, MMCISTATUS);
674 unsigned int remain, len;
677 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
678 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
681 if (msmsdcc_spin_on_status(host,
682 (MCI_TXFIFOHALFEMPTY |
689 /* Map the current scatter buffer */
690 local_irq_save(flags);
691 buffer = kmap_atomic(sg_page(host->pio.sg),
692 KM_BIO_SRC_IRQ) + host->pio.sg->offset;
693 buffer += host->pio.sg_off;
694 remain = host->pio.sg->length - host->pio.sg_off;
696 if (status & MCI_RXACTIVE)
697 len = msmsdcc_pio_read(host, buffer, remain);
698 if (status & MCI_TXACTIVE)
699 len = msmsdcc_pio_write(host, buffer, remain, status);
701 /* Unmap the buffer */
702 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
703 local_irq_restore(flags);
705 host->pio.sg_off += len;
706 host->curr.xfer_remain -= len;
707 host->curr.data_xfered += len;
711 /* This sg page is full - do some housekeeping */
712 if (status & MCI_RXACTIVE && host->curr.user_pages)
713 flush_dcache_page(sg_page(host->pio.sg));
715 if (!--host->pio.sg_len) {
716 memset(&host->pio, 0, sizeof(host->pio));
720 /* Advance to next sg */
722 host->pio.sg_off = 0;
725 status = msmsdcc_readl(host, MMCISTATUS);
728 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
729 msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1);
731 if (!host->curr.xfer_remain)
732 msmsdcc_writel(host, 0, MMCIMASK1);
737 static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
739 struct mmc_command *cmd = host->curr.cmd;
741 host->curr.cmd = NULL;
742 cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
743 cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
744 cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
745 cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
747 if (status & MCI_CMDTIMEOUT) {
748 cmd->error = -ETIMEDOUT;
749 } else if (status & MCI_CMDCRCFAIL &&
750 cmd->flags & MMC_RSP_CRC) {
751 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
752 cmd->error = -EILSEQ;
755 if (!cmd->data || cmd->error) {
756 if (host->curr.data && host->dma.sg)
757 msm_dmov_stop_cmd(host->dma.channel,
759 else if (host->curr.data) { /* Non DMA */
760 msmsdcc_reset_and_restore(host);
761 msmsdcc_stop_data(host);
762 msmsdcc_request_end(host, cmd->mrq);
763 } else { /* host->data == NULL */
764 if (!cmd->error && host->prog_enable) {
765 if (status & MCI_PROGDONE) {
766 host->prog_scan = false;
767 host->prog_enable = false;
768 msmsdcc_request_end(host, cmd->mrq);
770 host->curr.cmd = cmd;
773 if (host->prog_enable) {
774 host->prog_scan = false;
775 host->prog_enable = false;
777 msmsdcc_request_end(host, cmd->mrq);
780 } else if (cmd->data)
781 if (!(cmd->data->flags & MMC_DATA_READ))
782 msmsdcc_start_data(host, cmd->data,
787 msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
790 struct mmc_data *data = host->curr.data;
792 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
793 MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) {
794 msmsdcc_do_cmdirq(host, status);
800 /* Check for data errors */
801 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
802 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
803 msmsdcc_data_err(host, data, status);
804 host->curr.data_xfered = 0;
806 msm_dmov_stop_cmd(host->dma.channel,
809 msmsdcc_reset_and_restore(host);
811 msmsdcc_stop_data(host);
813 msmsdcc_request_end(host, data->mrq);
815 msmsdcc_start_command(host, data->stop, 0);
819 /* Check for data done */
820 if (!host->curr.got_dataend && (status & MCI_DATAEND))
821 host->curr.got_dataend = 1;
824 * If DMA is still in progress, we complete via the completion handler
826 if (host->curr.got_dataend && !host->dma.busy) {
828 * There appears to be an issue in the controller where
829 * if you request a small block transfer (< fifo size),
830 * you may get your DATAEND/DATABLKEND irq without the
833 * Check to see if there is still data to be read,
834 * and simulate a PIO irq.
836 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
837 msmsdcc_pio_irq(1, host);
839 msmsdcc_stop_data(host);
841 host->curr.data_xfered = host->curr.xfer_size;
844 msmsdcc_request_end(host, data->mrq);
846 msmsdcc_start_command(host, data->stop, 0);
851 msmsdcc_irq(int irq, void *dev_id)
853 struct msmsdcc_host *host = dev_id;
854 void __iomem *base = host->base;
859 spin_lock(&host->lock);
862 status = msmsdcc_readl(host, MMCISTATUS);
863 status &= msmsdcc_readl(host, MMCIMASK0);
864 msmsdcc_writel(host, status, MMCICLEAR);
866 if (status & MCI_SDIOINTR)
867 status &= ~MCI_SDIOINTR;
872 msmsdcc_handle_irq_data(host, status, base);
874 if (status & MCI_SDIOINTOPER) {
876 status &= ~MCI_SDIOINTOPER;
881 spin_unlock(&host->lock);
884 * We have to delay handling the card interrupt as it calls
885 * back into the driver.
888 mmc_signal_sdio_irq(host->mmc);
890 return IRQ_RETVAL(ret);
894 msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
896 struct msmsdcc_host *host = mmc_priv(mmc);
899 WARN_ON(host->curr.mrq != NULL);
900 WARN_ON(host->pwr == 0);
902 spin_lock_irqsave(&host->lock, flags);
907 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
909 mrq->data->bytes_xfered = mrq->data->blksz *
912 mrq->cmd->error = -ENOMEDIUM;
914 spin_unlock_irqrestore(&host->lock, flags);
915 mmc_request_done(mmc, mrq);
919 msmsdcc_enable_clocks(host);
921 host->curr.mrq = mrq;
923 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
924 /* Queue/read data, daisy-chain command when data starts */
925 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
927 msmsdcc_start_command(host, mrq->cmd, 0);
929 if (host->cmdpoll && !msmsdcc_spin_on_status(host,
930 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
932 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
933 msmsdcc_do_cmdirq(host, status);
935 MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
937 host->stats.cmdpoll_hits++;
939 host->stats.cmdpoll_misses++;
941 spin_unlock_irqrestore(&host->lock, flags);
945 msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
947 struct msmsdcc_host *host = mmc_priv(mmc);
948 u32 clk = 0, pwr = 0;
952 spin_lock_irqsave(&host->lock, flags);
954 msmsdcc_enable_clocks(host);
957 if (ios->clock != host->clk_rate) {
958 rc = clk_set_rate(host->clk, ios->clock);
960 pr_err("%s: Error setting clock rate (%d)\n",
961 mmc_hostname(host->mmc), rc);
963 host->clk_rate = ios->clock;
965 clk |= MCI_CLK_ENABLE;
968 if (ios->bus_width == MMC_BUS_WIDTH_4)
969 clk |= (2 << 10); /* Set WIDEBUS */
971 if (ios->clock > 400000 && msmsdcc_pwrsave)
972 clk |= (1 << 9); /* PWRSAVE */
974 clk |= (1 << 12); /* FLOW_ENA */
975 clk |= (1 << 15); /* feedback clock */
977 if (host->plat->translate_vdd)
978 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
980 switch (ios->power_mode) {
991 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
994 msmsdcc_writel(host, clk, MMCICLOCK);
996 if (host->pwr != pwr) {
998 msmsdcc_writel(host, pwr, MMCIPOWER);
1001 msmsdcc_disable_clocks(host, 1);
1003 spin_unlock_irqrestore(&host->lock, flags);
1006 static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1008 struct msmsdcc_host *host = mmc_priv(mmc);
1009 unsigned long flags;
1012 spin_lock_irqsave(&host->lock, flags);
1013 if (msmsdcc_sdioirq == 1) {
1014 status = msmsdcc_readl(host, MMCIMASK0);
1016 status |= MCI_SDIOINTOPERMASK;
1018 status &= ~MCI_SDIOINTOPERMASK;
1019 host->saved_irq0mask = status;
1020 msmsdcc_writel(host, status, MMCIMASK0);
1022 spin_unlock_irqrestore(&host->lock, flags);
1025 static const struct mmc_host_ops msmsdcc_ops = {
1026 .request = msmsdcc_request,
1027 .set_ios = msmsdcc_set_ios,
1028 .enable_sdio_irq = msmsdcc_enable_sdio_irq,
1032 msmsdcc_check_status(unsigned long data)
1034 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
1035 unsigned int status;
1037 if (!host->plat->status) {
1038 mmc_detect_change(host->mmc, 0);
1042 status = host->plat->status(mmc_dev(host->mmc));
1043 host->eject = !status;
1044 if (status ^ host->oldstat) {
1045 pr_info("%s: Slot status change detected (%d -> %d)\n",
1046 mmc_hostname(host->mmc), host->oldstat, status);
1048 mmc_detect_change(host->mmc, (5 * HZ) / 2);
1050 mmc_detect_change(host->mmc, 0);
1053 host->oldstat = status;
1056 if (host->timer.function)
1057 mod_timer(&host->timer, jiffies + HZ);
1061 msmsdcc_platform_status_irq(int irq, void *dev_id)
1063 struct msmsdcc_host *host = dev_id;
1065 printk(KERN_DEBUG "%s: %d\n", __func__, irq);
1066 msmsdcc_check_status((unsigned long) host);
1071 msmsdcc_status_notify_cb(int card_present, void *dev_id)
1073 struct msmsdcc_host *host = dev_id;
1075 printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
1077 msmsdcc_check_status((unsigned long) host);
1081 msmsdcc_busclk_expired(unsigned long _data)
1083 struct msmsdcc_host *host = (struct msmsdcc_host *) _data;
1086 msmsdcc_disable_clocks(host, 0);
1090 msmsdcc_init_dma(struct msmsdcc_host *host)
1092 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1093 host->dma.host = host;
1094 host->dma.channel = -1;
1099 host->dma.nc = dma_alloc_coherent(NULL,
1100 sizeof(struct msmsdcc_nc_dmadata),
1101 &host->dma.nc_busaddr,
1103 if (host->dma.nc == NULL) {
1104 pr_err("Unable to allocate DMA buffer\n");
1107 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1108 host->dma.cmd_busaddr = host->dma.nc_busaddr;
1109 host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1110 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1111 host->dma.channel = host->dmares->start;
1117 msmsdcc_probe(struct platform_device *pdev)
1119 struct msm_mmc_platform_data *plat = pdev->dev.platform_data;
1120 struct msmsdcc_host *host;
1121 struct mmc_host *mmc;
1122 struct resource *cmd_irqres = NULL;
1123 struct resource *pio_irqres = NULL;
1124 struct resource *stat_irqres = NULL;
1125 struct resource *memres = NULL;
1126 struct resource *dmares = NULL;
1129 /* must have platform data */
1131 pr_err("%s: Platform data not available\n", __func__);
1136 if (pdev->id < 1 || pdev->id > 4)
1139 if (pdev->resource == NULL || pdev->num_resources < 2) {
1140 pr_err("%s: Invalid resource\n", __func__);
1144 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1145 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1146 cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1148 pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1150 stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1153 if (!cmd_irqres || !pio_irqres || !memres) {
1154 pr_err("%s: Invalid resource\n", __func__);
1159 * Setup our host structure
1162 mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1168 host = mmc_priv(mmc);
1169 host->pdev_id = pdev->id;
1172 host->curr.cmd = NULL;
1176 host->base = ioremap(memres->start, PAGE_SIZE);
1182 host->cmd_irqres = cmd_irqres;
1183 host->pio_irqres = pio_irqres;
1184 host->memres = memres;
1185 host->dmares = dmares;
1186 spin_lock_init(&host->lock);
1188 tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet,
1189 (unsigned long)host);
1194 msmsdcc_init_dma(host);
1196 /* Get our clocks */
1197 host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1198 if (IS_ERR(host->pclk)) {
1199 ret = PTR_ERR(host->pclk);
1203 host->clk = clk_get(&pdev->dev, "sdc_clk");
1204 if (IS_ERR(host->clk)) {
1205 ret = PTR_ERR(host->clk);
1210 ret = msmsdcc_enable_clocks(host);
1214 ret = clk_set_rate(host->clk, msmsdcc_fmin);
1216 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
1220 host->pclk_rate = clk_get_rate(host->pclk);
1221 host->clk_rate = clk_get_rate(host->clk);
1224 * Setup MMC host structure
1226 mmc->ops = &msmsdcc_ops;
1227 mmc->f_min = msmsdcc_fmin;
1228 mmc->f_max = msmsdcc_fmax;
1229 mmc->ocr_avail = plat->ocr_mask;
1232 mmc->caps |= MMC_CAP_4_BIT_DATA;
1233 if (msmsdcc_sdioirq)
1234 mmc->caps |= MMC_CAP_SDIO_IRQ;
1235 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1237 mmc->max_segs = NR_SG;
1238 mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1239 mmc->max_blk_count = 65536;
1241 mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */
1242 mmc->max_seg_size = mmc->max_req_size;
1244 msmsdcc_writel(host, 0, MMCIMASK0);
1245 msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
1247 msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
1248 host->saved_irq0mask = MCI_IRQENABLE;
1251 * Setup card detect change
1254 memset(&host->timer, 0, sizeof(host->timer));
1256 if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1257 unsigned long irqflags = IRQF_SHARED |
1258 (stat_irqres->flags & IRQF_TRIGGER_MASK);
1260 host->stat_irq = stat_irqres->start;
1261 ret = request_irq(host->stat_irq,
1262 msmsdcc_platform_status_irq,
1264 DRIVER_NAME " (slot)",
1267 pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1268 mmc_hostname(mmc), host->stat_irq, ret);
1271 } else if (plat->register_status_notify) {
1272 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1273 } else if (!plat->status)
1274 pr_err("%s: No card detect facilities available\n",
1277 init_timer(&host->timer);
1278 host->timer.data = (unsigned long)host;
1279 host->timer.function = msmsdcc_check_status;
1280 host->timer.expires = jiffies + HZ;
1281 add_timer(&host->timer);
1285 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1286 host->eject = !host->oldstat;
1289 init_timer(&host->busclk_timer);
1290 host->busclk_timer.data = (unsigned long) host;
1291 host->busclk_timer.function = msmsdcc_busclk_expired;
1293 ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1294 DRIVER_NAME " (cmd)", host);
1298 ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1299 DRIVER_NAME " (pio)", host);
1303 mmc_set_drvdata(pdev, mmc);
1306 pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1307 mmc_hostname(mmc), (unsigned long long)memres->start,
1308 (unsigned int) cmd_irqres->start,
1309 (unsigned int) host->stat_irq, host->dma.channel);
1310 pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1311 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1312 pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1313 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1314 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1315 pr_info("%s: Power save feature enable = %d\n",
1316 mmc_hostname(mmc), msmsdcc_pwrsave);
1318 if (host->dma.channel != -1) {
1319 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1320 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1321 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1322 mmc_hostname(mmc), host->dma.cmd_busaddr,
1323 host->dma.cmdptr_busaddr);
1325 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
1326 if (host->timer.function)
1327 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
1330 msmsdcc_disable_clocks(host, 1);
1334 free_irq(cmd_irqres->start, host);
1337 free_irq(host->stat_irq, host);
1339 msmsdcc_disable_clocks(host, 0);
1343 clk_put(host->pclk);
1351 #ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1353 do_resume_work(struct work_struct *work)
1355 struct msmsdcc_host *host =
1356 container_of(work, struct msmsdcc_host, resume_task);
1357 struct mmc_host *mmc = host->mmc;
1360 mmc_resume_host(mmc);
1362 enable_irq(host->stat_irq);
1369 msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1371 struct mmc_host *mmc = mmc_get_drvdata(dev);
1375 struct msmsdcc_host *host = mmc_priv(mmc);
1378 disable_irq(host->stat_irq);
1380 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1381 rc = mmc_suspend_host(mmc);
1383 msmsdcc_writel(host, 0, MMCIMASK0);
1385 msmsdcc_disable_clocks(host, 0);
1391 msmsdcc_resume(struct platform_device *dev)
1393 struct mmc_host *mmc = mmc_get_drvdata(dev);
1396 struct msmsdcc_host *host = mmc_priv(mmc);
1398 msmsdcc_enable_clocks(host);
1400 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
1402 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1403 mmc_resume_host(mmc);
1405 enable_irq(host->stat_irq);
1407 msmsdcc_disable_clocks(host, 1);
1413 #define msmsdcc_suspend 0
1414 #define msmsdcc_resume 0
1417 static struct platform_driver msmsdcc_driver = {
1418 .probe = msmsdcc_probe,
1419 .suspend = msmsdcc_suspend,
1420 .resume = msmsdcc_resume,
1426 static int __init msmsdcc_init(void)
1428 return platform_driver_register(&msmsdcc_driver);
1431 static void __exit msmsdcc_exit(void)
1433 platform_driver_unregister(&msmsdcc_driver);
1436 module_init(msmsdcc_init);
1437 module_exit(msmsdcc_exit);
1439 MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1440 MODULE_LICENSE("GPL");