2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
4 * Copyright (C) 2007 Google Inc,
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 * Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Author: San Mehat (san@android.com)
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/highmem.h>
27 #include <linux/log2.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/mmc/sdio.h>
31 #include <linux/clk.h>
32 #include <linux/scatterlist.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/debugfs.h>
37 #include <linux/memory.h>
38 #include <linux/gfp.h>
40 #include <asm/cacheflush.h>
41 #include <asm/div64.h>
42 #include <asm/sizes.h>
45 #include <mach/msm_iomap.h>
51 #define DRIVER_NAME "msm-sdcc"
53 #define BUSCLK_PWRSAVE 1
54 #define BUSCLK_TIMEOUT (HZ)
55 static unsigned int msmsdcc_fmin = 144000;
56 static unsigned int msmsdcc_fmax = 50000000;
57 static unsigned int msmsdcc_4bit = 1;
58 static unsigned int msmsdcc_pwrsave = 1;
59 static unsigned int msmsdcc_piopoll = 1;
60 static unsigned int msmsdcc_sdioirq;
62 #define PIO_SPINMAX 30
63 #define CMD_SPINMAX 20
67 msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
69 WARN_ON(!host->clks_on);
71 BUG_ON(host->curr.mrq);
74 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
76 del_timer_sync(&host->busclk_timer);
77 /* Need to check clks_on again in case the busclk
81 clk_disable(host->clk);
82 clk_disable(host->pclk);
89 msmsdcc_enable_clocks(struct msmsdcc_host *host)
93 del_timer_sync(&host->busclk_timer);
96 rc = clk_enable(host->pclk);
99 rc = clk_enable(host->clk);
101 clk_disable(host->pclk);
104 udelay(1 + ((3 * USEC_PER_SEC) /
105 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
111 static inline unsigned int
112 msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
114 return readl(host->base + reg);
118 msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
120 writel(data, host->base + reg);
121 /* 3 clk delay required! */
122 udelay(1 + ((3 * USEC_PER_SEC) /
123 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
127 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
130 static void msmsdcc_reset_and_restore(struct msmsdcc_host *host)
136 /* Save the controller state */
137 mci_clk = readl(host->base + MMCICLOCK);
138 mci_mask0 = readl(host->base + MMCIMASK0);
140 /* Reset the controller */
141 ret = clk_reset(host->clk, CLK_RESET_ASSERT);
143 pr_err("%s: Clock assert failed at %u Hz with err %d\n",
144 mmc_hostname(host->mmc), host->clk_rate, ret);
146 ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
148 pr_err("%s: Clock deassert failed at %u Hz with err %d\n",
149 mmc_hostname(host->mmc), host->clk_rate, ret);
151 pr_info("%s: Controller has been re-initialiazed\n",
152 mmc_hostname(host->mmc));
154 /* Restore the contoller state */
155 writel(host->pwr, host->base + MMCIPOWER);
156 writel(mci_clk, host->base + MMCICLOCK);
157 writel(mci_mask0, host->base + MMCIMASK0);
158 ret = clk_set_rate(host->clk, host->clk_rate);
160 pr_err("%s: Failed to set clk rate %u Hz (%d)\n",
161 mmc_hostname(host->mmc), host->clk_rate, ret);
165 msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
167 BUG_ON(host->curr.data);
169 host->curr.mrq = NULL;
170 host->curr.cmd = NULL;
173 mrq->data->bytes_xfered = host->curr.data_xfered;
174 if (mrq->cmd->error == -ETIMEDOUT)
178 msmsdcc_disable_clocks(host, 1);
181 * Need to drop the host lock here; mmc_request_done may call
182 * back into the driver...
184 spin_unlock(&host->lock);
185 mmc_request_done(host->mmc, mrq);
186 spin_lock(&host->lock);
190 msmsdcc_stop_data(struct msmsdcc_host *host)
192 host->curr.data = NULL;
193 host->curr.got_dataend = 0;
196 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
198 return host->memres->start + MMCIFIFO;
202 msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
203 msmsdcc_writel(host, arg, MMCIARGUMENT);
204 msmsdcc_writel(host, c, MMCICOMMAND);
208 msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
210 struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
212 msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
213 msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
215 msmsdcc_writel(host, host->cmd_pio_irqmask, MMCIMASK1);
216 msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
219 msmsdcc_start_command_exec(host,
220 (u32) host->cmd_cmd->arg,
223 host->dma.active = 1;
227 msmsdcc_dma_complete_tlet(unsigned long data)
229 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
231 struct mmc_request *mrq;
232 struct msm_dmov_errdata err;
234 spin_lock_irqsave(&host->lock, flags);
235 host->dma.active = 0;
238 mrq = host->curr.mrq;
242 if (!(host->dma.result & DMOV_RSLT_VALID)) {
243 pr_err("msmsdcc: Invalid DataMover result\n");
247 if (host->dma.result & DMOV_RSLT_DONE) {
248 host->curr.data_xfered = host->curr.xfer_size;
251 if (host->dma.result & DMOV_RSLT_ERROR)
252 pr_err("%s: DMA error (0x%.8x)\n",
253 mmc_hostname(host->mmc), host->dma.result);
254 if (host->dma.result & DMOV_RSLT_FLUSH)
255 pr_err("%s: DMA channel flushed (0x%.8x)\n",
256 mmc_hostname(host->mmc), host->dma.result);
258 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
259 err.flush[0], err.flush[1], err.flush[2],
260 err.flush[3], err.flush[4], err.flush[5]);
262 msmsdcc_reset_and_restore(host);
263 if (!mrq->data->error)
264 mrq->data->error = -EIO;
266 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
269 if (host->curr.user_pages) {
270 struct scatterlist *sg = host->dma.sg;
273 for (i = 0; i < host->dma.num_ents; i++)
274 flush_dcache_page(sg_page(sg++));
280 if (host->curr.got_dataend || mrq->data->error) {
283 * If we've already gotten our DATAEND / DATABLKEND
284 * for this request, then complete it through here.
286 msmsdcc_stop_data(host);
288 if (!mrq->data->error)
289 host->curr.data_xfered = host->curr.xfer_size;
290 if (!mrq->data->stop || mrq->cmd->error) {
291 host->curr.mrq = NULL;
292 host->curr.cmd = NULL;
293 mrq->data->bytes_xfered = host->curr.data_xfered;
295 spin_unlock_irqrestore(&host->lock, flags);
297 msmsdcc_disable_clocks(host, 1);
299 mmc_request_done(host->mmc, mrq);
302 msmsdcc_start_command(host, mrq->data->stop, 0);
306 spin_unlock_irqrestore(&host->lock, flags);
311 msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
313 struct msm_dmov_errdata *err)
315 struct msmsdcc_dma_data *dma_data =
316 container_of(cmd, struct msmsdcc_dma_data, hdr);
317 struct msmsdcc_host *host = dma_data->host;
319 dma_data->result = result;
321 memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata));
323 tasklet_schedule(&host->dma_tlet);
326 static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
328 if (host->dma.channel == -1)
331 if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
333 if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
338 static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
340 struct msmsdcc_nc_dmadata *nc;
346 struct scatterlist *sg = data->sg;
348 rc = validate_dma(host, data);
352 host->dma.sg = data->sg;
353 host->dma.num_ents = data->sg_len;
355 BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
359 switch (host->pdev_id) {
361 crci = MSMSDCC_CRCI_SDC1;
364 crci = MSMSDCC_CRCI_SDC2;
367 crci = MSMSDCC_CRCI_SDC3;
370 crci = MSMSDCC_CRCI_SDC4;
374 host->dma.num_ents = 0;
378 if (data->flags & MMC_DATA_READ)
379 host->dma.dir = DMA_FROM_DEVICE;
381 host->dma.dir = DMA_TO_DEVICE;
383 host->curr.user_pages = 0;
386 for (i = 0; i < host->dma.num_ents; i++) {
387 box->cmd = CMD_MODE_BOX;
389 /* Initialize sg dma address */
390 sg->dma_address = page_to_dma(mmc_dev(host->mmc), sg_page(sg))
393 if (i == (host->dma.num_ents - 1))
395 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
396 (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
397 (sg_dma_len(sg) / MCI_FIFOSIZE) ;
399 if (data->flags & MMC_DATA_READ) {
400 box->src_row_addr = msmsdcc_fifo_addr(host);
401 box->dst_row_addr = sg_dma_address(sg);
403 box->src_dst_len = (MCI_FIFOSIZE << 16) |
405 box->row_offset = MCI_FIFOSIZE;
407 box->num_rows = rows * ((1 << 16) + 1);
408 box->cmd |= CMD_SRC_CRCI(crci);
410 box->src_row_addr = sg_dma_address(sg);
411 box->dst_row_addr = msmsdcc_fifo_addr(host);
413 box->src_dst_len = (MCI_FIFOSIZE << 16) |
415 box->row_offset = (MCI_FIFOSIZE << 16);
417 box->num_rows = rows * ((1 << 16) + 1);
418 box->cmd |= CMD_DST_CRCI(crci);
424 /* location of command block must be 64 bit aligned */
425 BUG_ON(host->dma.cmd_busaddr & 0x07);
427 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
428 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
429 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
430 host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
432 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
433 host->dma.num_ents, host->dma.dir);
434 /* dsb inside dma_map_sg will write nc out to mem as well */
436 if (n != host->dma.num_ents) {
437 printk(KERN_ERR "%s: Unable to map in all sg elements\n",
438 mmc_hostname(host->mmc));
440 host->dma.num_ents = 0;
448 snoop_cccr_abort(struct mmc_command *cmd)
450 if ((cmd->opcode == 52) &&
451 (cmd->arg & 0x80000000) &&
452 (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
458 msmsdcc_start_command_deferred(struct msmsdcc_host *host,
459 struct mmc_command *cmd, u32 *c)
461 *c |= (cmd->opcode | MCI_CPSM_ENABLE);
463 if (cmd->flags & MMC_RSP_PRESENT) {
464 if (cmd->flags & MMC_RSP_136)
465 *c |= MCI_CPSM_LONGRSP;
466 *c |= MCI_CPSM_RESPONSE;
470 *c |= MCI_CPSM_INTERRUPT;
472 if ((((cmd->opcode == 17) || (cmd->opcode == 18)) ||
473 ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
475 *c |= MCI_CSPM_DATCMD;
477 if (host->prog_scan && (cmd->opcode == 12)) {
478 *c |= MCI_CPSM_PROGENA;
479 host->prog_enable = true;
482 if (cmd == cmd->mrq->stop)
483 *c |= MCI_CSPM_MCIABORT;
485 if (snoop_cccr_abort(cmd))
486 *c |= MCI_CSPM_MCIABORT;
488 if (host->curr.cmd != NULL) {
489 printk(KERN_ERR "%s: Overlapping command requests\n",
490 mmc_hostname(host->mmc));
492 host->curr.cmd = cmd;
496 msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
497 struct mmc_command *cmd, u32 c)
499 unsigned int datactrl, timeout;
500 unsigned long long clks;
501 unsigned int pio_irqmask = 0;
503 host->curr.data = data;
504 host->curr.xfer_size = data->blksz * data->blocks;
505 host->curr.xfer_remain = host->curr.xfer_size;
506 host->curr.data_xfered = 0;
507 host->curr.got_dataend = 0;
509 memset(&host->pio, 0, sizeof(host->pio));
511 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
513 if (!msmsdcc_config_dma(host, data))
514 datactrl |= MCI_DPSM_DMAENABLE;
516 host->pio.sg = data->sg;
517 host->pio.sg_len = data->sg_len;
518 host->pio.sg_off = 0;
520 if (data->flags & MMC_DATA_READ) {
521 pio_irqmask = MCI_RXFIFOHALFFULLMASK;
522 if (host->curr.xfer_remain < MCI_FIFOSIZE)
523 pio_irqmask |= MCI_RXDATAAVLBLMASK;
525 pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
528 if (data->flags & MMC_DATA_READ)
529 datactrl |= MCI_DPSM_DIRECTION;
531 clks = (unsigned long long)data->timeout_ns * host->clk_rate;
532 do_div(clks, NSEC_PER_SEC);
533 timeout = data->timeout_clks + (unsigned int)clks*2 ;
535 if (datactrl & MCI_DPSM_DMAENABLE) {
536 /* Save parameters for the exec function */
537 host->cmd_timeout = timeout;
538 host->cmd_pio_irqmask = pio_irqmask;
539 host->cmd_datactrl = datactrl;
542 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
543 host->dma.hdr.data = (void *)host;
547 msmsdcc_start_command_deferred(host, cmd, &c);
550 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
551 if (data->flags & MMC_DATA_WRITE)
552 host->prog_scan = true;
554 msmsdcc_writel(host, timeout, MMCIDATATIMER);
556 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
558 msmsdcc_writel(host, pio_irqmask, MMCIMASK1);
559 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
562 /* Daisy-chain the command if requested */
563 msmsdcc_start_command(host, cmd, c);
569 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
571 if (cmd == cmd->mrq->stop)
572 c |= MCI_CSPM_MCIABORT;
576 msmsdcc_start_command_deferred(host, cmd, &c);
577 msmsdcc_start_command_exec(host, cmd->arg, c);
581 msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
584 if (status & MCI_DATACRCFAIL) {
585 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
586 pr_err("%s: opcode 0x%.8x\n", __func__,
587 data->mrq->cmd->opcode);
588 pr_err("%s: blksz %d, blocks %d\n", __func__,
589 data->blksz, data->blocks);
590 data->error = -EILSEQ;
591 } else if (status & MCI_DATATIMEOUT) {
592 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
593 data->error = -ETIMEDOUT;
594 } else if (status & MCI_RXOVERRUN) {
595 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
597 } else if (status & MCI_TXUNDERRUN) {
598 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
601 pr_err("%s: Unknown error (0x%.8x)\n",
602 mmc_hostname(host->mmc), status);
609 msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
611 uint32_t *ptr = (uint32_t *) buffer;
615 remain = ((remain >> 2) + 1) << 2;
617 while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
618 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
620 count += sizeof(uint32_t);
622 remain -= sizeof(uint32_t);
630 msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
631 unsigned int remain, u32 status)
633 void __iomem *base = host->base;
637 unsigned int count, maxcnt, sz;
639 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
641 count = min(remain, maxcnt);
643 sz = count % 4 ? (count >> 2) + 1 : (count >> 2);
644 writesl(base + MMCIFIFO, ptr, sz);
651 status = msmsdcc_readl(host, MMCISTATUS);
652 } while (status & MCI_TXFIFOHALFEMPTY);
658 msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
661 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
670 msmsdcc_pio_irq(int irq, void *dev_id)
672 struct msmsdcc_host *host = dev_id;
675 status = msmsdcc_readl(host, MMCISTATUS);
679 unsigned int remain, len;
682 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
683 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
686 if (msmsdcc_spin_on_status(host,
687 (MCI_TXFIFOHALFEMPTY |
694 /* Map the current scatter buffer */
695 local_irq_save(flags);
696 buffer = kmap_atomic(sg_page(host->pio.sg),
697 KM_BIO_SRC_IRQ) + host->pio.sg->offset;
698 buffer += host->pio.sg_off;
699 remain = host->pio.sg->length - host->pio.sg_off;
701 if (status & MCI_RXACTIVE)
702 len = msmsdcc_pio_read(host, buffer, remain);
703 if (status & MCI_TXACTIVE)
704 len = msmsdcc_pio_write(host, buffer, remain, status);
706 /* Unmap the buffer */
707 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
708 local_irq_restore(flags);
710 host->pio.sg_off += len;
711 host->curr.xfer_remain -= len;
712 host->curr.data_xfered += len;
716 /* This sg page is full - do some housekeeping */
717 if (status & MCI_RXACTIVE && host->curr.user_pages)
718 flush_dcache_page(sg_page(host->pio.sg));
720 if (!--host->pio.sg_len) {
721 memset(&host->pio, 0, sizeof(host->pio));
725 /* Advance to next sg */
727 host->pio.sg_off = 0;
730 status = msmsdcc_readl(host, MMCISTATUS);
733 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
734 msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1);
736 if (!host->curr.xfer_remain)
737 msmsdcc_writel(host, 0, MMCIMASK1);
742 static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
744 struct mmc_command *cmd = host->curr.cmd;
746 host->curr.cmd = NULL;
747 cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
748 cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
749 cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
750 cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
752 if (status & MCI_CMDTIMEOUT) {
753 cmd->error = -ETIMEDOUT;
754 } else if (status & MCI_CMDCRCFAIL &&
755 cmd->flags & MMC_RSP_CRC) {
756 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
757 cmd->error = -EILSEQ;
760 if (!cmd->data || cmd->error) {
761 if (host->curr.data && host->dma.sg)
762 msm_dmov_stop_cmd(host->dma.channel,
764 else if (host->curr.data) { /* Non DMA */
765 msmsdcc_reset_and_restore(host);
766 msmsdcc_stop_data(host);
767 msmsdcc_request_end(host, cmd->mrq);
768 } else { /* host->data == NULL */
769 if (!cmd->error && host->prog_enable) {
770 if (status & MCI_PROGDONE) {
771 host->prog_scan = false;
772 host->prog_enable = false;
773 msmsdcc_request_end(host, cmd->mrq);
775 host->curr.cmd = cmd;
778 if (host->prog_enable) {
779 host->prog_scan = false;
780 host->prog_enable = false;
782 msmsdcc_request_end(host, cmd->mrq);
785 } else if (cmd->data)
786 if (!(cmd->data->flags & MMC_DATA_READ))
787 msmsdcc_start_data(host, cmd->data,
792 msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
795 struct mmc_data *data = host->curr.data;
797 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
798 MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) {
799 msmsdcc_do_cmdirq(host, status);
805 /* Check for data errors */
806 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
807 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
808 msmsdcc_data_err(host, data, status);
809 host->curr.data_xfered = 0;
811 msm_dmov_stop_cmd(host->dma.channel,
814 msmsdcc_reset_and_restore(host);
816 msmsdcc_stop_data(host);
818 msmsdcc_request_end(host, data->mrq);
820 msmsdcc_start_command(host, data->stop, 0);
824 /* Check for data done */
825 if (!host->curr.got_dataend && (status & MCI_DATAEND))
826 host->curr.got_dataend = 1;
829 * If DMA is still in progress, we complete via the completion handler
831 if (host->curr.got_dataend && !host->dma.busy) {
833 * There appears to be an issue in the controller where
834 * if you request a small block transfer (< fifo size),
835 * you may get your DATAEND/DATABLKEND irq without the
838 * Check to see if there is still data to be read,
839 * and simulate a PIO irq.
841 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
842 msmsdcc_pio_irq(1, host);
844 msmsdcc_stop_data(host);
846 host->curr.data_xfered = host->curr.xfer_size;
849 msmsdcc_request_end(host, data->mrq);
851 msmsdcc_start_command(host, data->stop, 0);
856 msmsdcc_irq(int irq, void *dev_id)
858 struct msmsdcc_host *host = dev_id;
859 void __iomem *base = host->base;
864 spin_lock(&host->lock);
867 status = msmsdcc_readl(host, MMCISTATUS);
868 status &= msmsdcc_readl(host, MMCIMASK0);
869 msmsdcc_writel(host, status, MMCICLEAR);
871 if (status & MCI_SDIOINTR)
872 status &= ~MCI_SDIOINTR;
877 msmsdcc_handle_irq_data(host, status, base);
879 if (status & MCI_SDIOINTOPER) {
881 status &= ~MCI_SDIOINTOPER;
886 spin_unlock(&host->lock);
889 * We have to delay handling the card interrupt as it calls
890 * back into the driver.
893 mmc_signal_sdio_irq(host->mmc);
895 return IRQ_RETVAL(ret);
899 msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
901 struct msmsdcc_host *host = mmc_priv(mmc);
904 WARN_ON(host->curr.mrq != NULL);
905 WARN_ON(host->pwr == 0);
907 spin_lock_irqsave(&host->lock, flags);
912 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
914 mrq->data->bytes_xfered = mrq->data->blksz *
917 mrq->cmd->error = -ENOMEDIUM;
919 spin_unlock_irqrestore(&host->lock, flags);
920 mmc_request_done(mmc, mrq);
924 msmsdcc_enable_clocks(host);
926 host->curr.mrq = mrq;
928 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
929 /* Queue/read data, daisy-chain command when data starts */
930 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
932 msmsdcc_start_command(host, mrq->cmd, 0);
934 if (host->cmdpoll && !msmsdcc_spin_on_status(host,
935 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
937 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
938 msmsdcc_do_cmdirq(host, status);
940 MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
942 host->stats.cmdpoll_hits++;
944 host->stats.cmdpoll_misses++;
946 spin_unlock_irqrestore(&host->lock, flags);
950 msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
952 struct msmsdcc_host *host = mmc_priv(mmc);
953 u32 clk = 0, pwr = 0;
957 spin_lock_irqsave(&host->lock, flags);
959 msmsdcc_enable_clocks(host);
962 if (ios->clock != host->clk_rate) {
963 rc = clk_set_rate(host->clk, ios->clock);
965 pr_err("%s: Error setting clock rate (%d)\n",
966 mmc_hostname(host->mmc), rc);
968 host->clk_rate = ios->clock;
970 clk |= MCI_CLK_ENABLE;
973 if (ios->bus_width == MMC_BUS_WIDTH_4)
974 clk |= (2 << 10); /* Set WIDEBUS */
976 if (ios->clock > 400000 && msmsdcc_pwrsave)
977 clk |= (1 << 9); /* PWRSAVE */
979 clk |= (1 << 12); /* FLOW_ENA */
980 clk |= (1 << 15); /* feedback clock */
982 if (host->plat->translate_vdd)
983 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
985 switch (ios->power_mode) {
996 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
999 msmsdcc_writel(host, clk, MMCICLOCK);
1001 if (host->pwr != pwr) {
1003 msmsdcc_writel(host, pwr, MMCIPOWER);
1006 msmsdcc_disable_clocks(host, 1);
1008 spin_unlock_irqrestore(&host->lock, flags);
1011 static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1013 struct msmsdcc_host *host = mmc_priv(mmc);
1014 unsigned long flags;
1017 spin_lock_irqsave(&host->lock, flags);
1018 if (msmsdcc_sdioirq == 1) {
1019 status = msmsdcc_readl(host, MMCIMASK0);
1021 status |= MCI_SDIOINTOPERMASK;
1023 status &= ~MCI_SDIOINTOPERMASK;
1024 host->saved_irq0mask = status;
1025 msmsdcc_writel(host, status, MMCIMASK0);
1027 spin_unlock_irqrestore(&host->lock, flags);
1030 static const struct mmc_host_ops msmsdcc_ops = {
1031 .request = msmsdcc_request,
1032 .set_ios = msmsdcc_set_ios,
1033 .enable_sdio_irq = msmsdcc_enable_sdio_irq,
1037 msmsdcc_check_status(unsigned long data)
1039 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
1040 unsigned int status;
1042 if (!host->plat->status) {
1043 mmc_detect_change(host->mmc, 0);
1047 status = host->plat->status(mmc_dev(host->mmc));
1048 host->eject = !status;
1049 if (status ^ host->oldstat) {
1050 pr_info("%s: Slot status change detected (%d -> %d)\n",
1051 mmc_hostname(host->mmc), host->oldstat, status);
1053 mmc_detect_change(host->mmc, (5 * HZ) / 2);
1055 mmc_detect_change(host->mmc, 0);
1058 host->oldstat = status;
1061 if (host->timer.function)
1062 mod_timer(&host->timer, jiffies + HZ);
1066 msmsdcc_platform_status_irq(int irq, void *dev_id)
1068 struct msmsdcc_host *host = dev_id;
1070 printk(KERN_DEBUG "%s: %d\n", __func__, irq);
1071 msmsdcc_check_status((unsigned long) host);
1076 msmsdcc_status_notify_cb(int card_present, void *dev_id)
1078 struct msmsdcc_host *host = dev_id;
1080 printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
1082 msmsdcc_check_status((unsigned long) host);
1086 msmsdcc_busclk_expired(unsigned long _data)
1088 struct msmsdcc_host *host = (struct msmsdcc_host *) _data;
1091 msmsdcc_disable_clocks(host, 0);
1095 msmsdcc_init_dma(struct msmsdcc_host *host)
1097 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1098 host->dma.host = host;
1099 host->dma.channel = -1;
1104 host->dma.nc = dma_alloc_coherent(NULL,
1105 sizeof(struct msmsdcc_nc_dmadata),
1106 &host->dma.nc_busaddr,
1108 if (host->dma.nc == NULL) {
1109 pr_err("Unable to allocate DMA buffer\n");
1112 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1113 host->dma.cmd_busaddr = host->dma.nc_busaddr;
1114 host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1115 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1116 host->dma.channel = host->dmares->start;
1122 msmsdcc_probe(struct platform_device *pdev)
1124 struct msm_mmc_platform_data *plat = pdev->dev.platform_data;
1125 struct msmsdcc_host *host;
1126 struct mmc_host *mmc;
1127 struct resource *cmd_irqres = NULL;
1128 struct resource *pio_irqres = NULL;
1129 struct resource *stat_irqres = NULL;
1130 struct resource *memres = NULL;
1131 struct resource *dmares = NULL;
1134 /* must have platform data */
1136 pr_err("%s: Platform data not available\n", __func__);
1141 if (pdev->id < 1 || pdev->id > 4)
1144 if (pdev->resource == NULL || pdev->num_resources < 2) {
1145 pr_err("%s: Invalid resource\n", __func__);
1149 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1151 cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1153 pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1155 stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1158 if (!cmd_irqres || !pio_irqres || !memres) {
1159 pr_err("%s: Invalid resource\n", __func__);
1164 * Setup our host structure
1167 mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1173 host = mmc_priv(mmc);
1174 host->pdev_id = pdev->id;
1177 host->curr.cmd = NULL;
1181 host->base = ioremap(memres->start, PAGE_SIZE);
1187 host->cmd_irqres = cmd_irqres;
1188 host->pio_irqres = pio_irqres;
1189 host->memres = memres;
1190 host->dmares = dmares;
1191 spin_lock_init(&host->lock);
1193 tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet,
1194 (unsigned long)host);
1199 msmsdcc_init_dma(host);
1201 /* Get our clocks */
1202 host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1203 if (IS_ERR(host->pclk)) {
1204 ret = PTR_ERR(host->pclk);
1208 host->clk = clk_get(&pdev->dev, "sdc_clk");
1209 if (IS_ERR(host->clk)) {
1210 ret = PTR_ERR(host->clk);
1215 ret = msmsdcc_enable_clocks(host);
1219 ret = clk_set_rate(host->clk, msmsdcc_fmin);
1221 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
1225 host->pclk_rate = clk_get_rate(host->pclk);
1226 host->clk_rate = clk_get_rate(host->clk);
1229 * Setup MMC host structure
1231 mmc->ops = &msmsdcc_ops;
1232 mmc->f_min = msmsdcc_fmin;
1233 mmc->f_max = msmsdcc_fmax;
1234 mmc->ocr_avail = plat->ocr_mask;
1237 mmc->caps |= MMC_CAP_4_BIT_DATA;
1238 if (msmsdcc_sdioirq)
1239 mmc->caps |= MMC_CAP_SDIO_IRQ;
1240 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1242 mmc->max_segs = NR_SG;
1243 mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1244 mmc->max_blk_count = 65536;
1246 mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */
1247 mmc->max_seg_size = mmc->max_req_size;
1249 msmsdcc_writel(host, 0, MMCIMASK0);
1250 msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
1252 msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
1253 host->saved_irq0mask = MCI_IRQENABLE;
1256 * Setup card detect change
1259 memset(&host->timer, 0, sizeof(host->timer));
1261 if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1262 unsigned long irqflags = IRQF_SHARED |
1263 (stat_irqres->flags & IRQF_TRIGGER_MASK);
1265 host->stat_irq = stat_irqres->start;
1266 ret = request_irq(host->stat_irq,
1267 msmsdcc_platform_status_irq,
1269 DRIVER_NAME " (slot)",
1272 pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1273 mmc_hostname(mmc), host->stat_irq, ret);
1276 } else if (plat->register_status_notify) {
1277 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1278 } else if (!plat->status)
1279 pr_err("%s: No card detect facilities available\n",
1282 init_timer(&host->timer);
1283 host->timer.data = (unsigned long)host;
1284 host->timer.function = msmsdcc_check_status;
1285 host->timer.expires = jiffies + HZ;
1286 add_timer(&host->timer);
1290 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1291 host->eject = !host->oldstat;
1294 init_timer(&host->busclk_timer);
1295 host->busclk_timer.data = (unsigned long) host;
1296 host->busclk_timer.function = msmsdcc_busclk_expired;
1298 ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1299 DRIVER_NAME " (cmd)", host);
1303 ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1304 DRIVER_NAME " (pio)", host);
1308 mmc_set_drvdata(pdev, mmc);
1311 pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1312 mmc_hostname(mmc), (unsigned long long)memres->start,
1313 (unsigned int) cmd_irqres->start,
1314 (unsigned int) host->stat_irq, host->dma.channel);
1315 pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1316 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1317 pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1318 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1319 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1320 pr_info("%s: Power save feature enable = %d\n",
1321 mmc_hostname(mmc), msmsdcc_pwrsave);
1323 if (host->dma.channel != -1) {
1324 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1325 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1326 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1327 mmc_hostname(mmc), host->dma.cmd_busaddr,
1328 host->dma.cmdptr_busaddr);
1330 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
1331 if (host->timer.function)
1332 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
1335 msmsdcc_disable_clocks(host, 1);
1339 free_irq(cmd_irqres->start, host);
1342 free_irq(host->stat_irq, host);
1344 msmsdcc_disable_clocks(host, 0);
1348 clk_put(host->pclk);
1356 #ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1358 do_resume_work(struct work_struct *work)
1360 struct msmsdcc_host *host =
1361 container_of(work, struct msmsdcc_host, resume_task);
1362 struct mmc_host *mmc = host->mmc;
1365 mmc_resume_host(mmc);
1367 enable_irq(host->stat_irq);
1374 msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1376 struct mmc_host *mmc = mmc_get_drvdata(dev);
1380 struct msmsdcc_host *host = mmc_priv(mmc);
1383 disable_irq(host->stat_irq);
1385 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1386 rc = mmc_suspend_host(mmc);
1388 msmsdcc_writel(host, 0, MMCIMASK0);
1390 msmsdcc_disable_clocks(host, 0);
1396 msmsdcc_resume(struct platform_device *dev)
1398 struct mmc_host *mmc = mmc_get_drvdata(dev);
1401 struct msmsdcc_host *host = mmc_priv(mmc);
1403 msmsdcc_enable_clocks(host);
1405 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
1407 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1408 mmc_resume_host(mmc);
1410 enable_irq(host->stat_irq);
1412 msmsdcc_disable_clocks(host, 1);
1418 #define msmsdcc_suspend 0
1419 #define msmsdcc_resume 0
1422 static struct platform_driver msmsdcc_driver = {
1423 .probe = msmsdcc_probe,
1424 .suspend = msmsdcc_suspend,
1425 .resume = msmsdcc_resume,
1431 static int __init msmsdcc_init(void)
1433 return platform_driver_register(&msmsdcc_driver);
1436 static void __exit msmsdcc_exit(void)
1438 platform_driver_unregister(&msmsdcc_driver);
1441 module_init(msmsdcc_init);
1442 module_exit(msmsdcc_exit);
1444 MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1445 MODULE_LICENSE("GPL");