2 * MOXA ART MMC host driver.
4 * Copyright (C) 2014 Jonas Jensen
6 * Jonas Jensen <jonas.jensen@gmail.com>
9 * Moxa Technologies Co., Ltd. <www.moxa.com>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/blkdev.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmaengine.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/sd.h>
27 #include <linux/sched.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/clk.h>
32 #include <linux/bitops.h>
33 #include <linux/of_dma.h>
34 #include <linux/spinlock.h>
37 #define REG_ARGUMENT 4
38 #define REG_RESPONSE0 8
39 #define REG_RESPONSE1 12
40 #define REG_RESPONSE2 16
41 #define REG_RESPONSE3 20
42 #define REG_RESPONSE_COMMAND 24
43 #define REG_DATA_CONTROL 28
44 #define REG_DATA_TIMER 32
45 #define REG_DATA_LENGTH 36
48 #define REG_INTERRUPT_MASK 48
49 #define REG_POWER_CONTROL 52
50 #define REG_CLOCK_CONTROL 56
51 #define REG_BUS_WIDTH 60
52 #define REG_DATA_WINDOW 64
53 #define REG_FEATURE 68
54 #define REG_REVISION 72
57 #define CMD_SDC_RESET BIT(10)
59 #define CMD_APP_CMD BIT(8)
60 #define CMD_LONG_RSP BIT(7)
61 #define CMD_NEED_RSP BIT(6)
62 #define CMD_IDX_MASK 0x3f
64 /* REG_RESPONSE_COMMAND */
65 #define RSP_CMD_APP BIT(6)
66 #define RSP_CMD_IDX_MASK 0x3f
68 /* REG_DATA_CONTROL */
69 #define DCR_DATA_FIFO_RESET BIT(8)
70 #define DCR_DATA_THRES BIT(7)
71 #define DCR_DATA_EN BIT(6)
72 #define DCR_DMA_EN BIT(5)
73 #define DCR_DATA_WRITE BIT(4)
74 #define DCR_BLK_SIZE 0x0f
77 #define DATA_LEN_MASK 0xffffff
80 #define WRITE_PROT BIT(12)
81 #define CARD_DETECT BIT(11)
82 /* 1-10 below can be sent to either registers, interrupt or clear. */
83 #define CARD_CHANGE BIT(10)
84 #define FIFO_ORUN BIT(9)
85 #define FIFO_URUN BIT(8)
86 #define DATA_END BIT(7)
87 #define CMD_SENT BIT(6)
88 #define DATA_CRC_OK BIT(5)
89 #define RSP_CRC_OK BIT(4)
90 #define DATA_TIMEOUT BIT(3)
91 #define RSP_TIMEOUT BIT(2)
92 #define DATA_CRC_FAIL BIT(1)
93 #define RSP_CRC_FAIL BIT(0)
95 #define MASK_RSP (RSP_TIMEOUT | RSP_CRC_FAIL | \
96 RSP_CRC_OK | CARD_DETECT | CMD_SENT)
98 #define MASK_DATA (DATA_CRC_OK | DATA_END | \
99 DATA_CRC_FAIL | DATA_TIMEOUT)
101 #define MASK_INTR_PIO (FIFO_URUN | FIFO_ORUN | CARD_CHANGE)
103 /* REG_POWER_CONTROL */
104 #define SD_POWER_ON BIT(4)
105 #define SD_POWER_MASK 0x0f
107 /* REG_CLOCK_CONTROL */
108 #define CLK_HISPD BIT(9)
109 #define CLK_OFF BIT(8)
110 #define CLK_SD BIT(7)
111 #define CLK_DIV_MASK 0x7f
114 #define BUS_WIDTH_4_SUPPORT BIT(3)
115 #define BUS_WIDTH_4 BIT(2)
116 #define BUS_WIDTH_1 BIT(0)
118 #define MMC_VDD_360 23
119 #define MIN_POWER (MMC_VDD_360 - SD_POWER_MASK)
120 #define MAX_RETRIES 500000
127 phys_addr_t reg_phys;
129 struct dma_chan *dma_chan_tx;
130 struct dma_chan *dma_chan_rx;
131 struct dma_async_tx_descriptor *tx_desc;
132 struct mmc_host *mmc;
133 struct mmc_request *mrq;
134 struct scatterlist *cur_sg;
135 struct completion dma_complete;
136 struct completion pio_complete;
151 static inline void moxart_init_sg(struct moxart_host *host,
152 struct mmc_data *data)
154 host->cur_sg = data->sg;
155 host->num_sg = data->sg_len;
156 host->data_remain = host->cur_sg->length;
158 if (host->data_remain > host->data_len)
159 host->data_remain = host->data_len;
162 static inline int moxart_next_sg(struct moxart_host *host)
165 struct mmc_data *data = host->mrq->cmd->data;
170 if (host->num_sg > 0) {
171 host->data_remain = host->cur_sg->length;
172 remain = host->data_len - data->bytes_xfered;
173 if (remain > 0 && remain < host->data_remain)
174 host->data_remain = remain;
180 static int moxart_wait_for_status(struct moxart_host *host,
181 u32 mask, u32 *status)
183 int ret = -ETIMEDOUT;
186 for (i = 0; i < MAX_RETRIES; i++) {
187 *status = readl(host->base + REG_STATUS);
188 if (!(*status & mask)) {
192 writel(*status & mask, host->base + REG_CLEAR);
198 dev_err(mmc_dev(host->mmc), "timed out waiting for status\n");
204 static void moxart_send_command(struct moxart_host *host,
205 struct mmc_command *cmd)
209 writel(RSP_TIMEOUT | RSP_CRC_OK |
210 RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR);
211 writel(cmd->arg, host->base + REG_ARGUMENT);
213 cmdctrl = cmd->opcode & CMD_IDX_MASK;
214 if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND ||
215 cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS ||
216 cmdctrl == SD_APP_SEND_NUM_WR_BLKS)
217 cmdctrl |= CMD_APP_CMD;
219 if (cmd->flags & MMC_RSP_PRESENT)
220 cmdctrl |= CMD_NEED_RSP;
222 if (cmd->flags & MMC_RSP_136)
223 cmdctrl |= CMD_LONG_RSP;
225 writel(cmdctrl | CMD_EN, host->base + REG_COMMAND);
227 if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT)
228 cmd->error = -ETIMEDOUT;
230 if (status & RSP_TIMEOUT) {
231 cmd->error = -ETIMEDOUT;
234 if (status & RSP_CRC_FAIL) {
238 if (status & RSP_CRC_OK) {
239 if (cmd->flags & MMC_RSP_136) {
240 cmd->resp[3] = readl(host->base + REG_RESPONSE0);
241 cmd->resp[2] = readl(host->base + REG_RESPONSE1);
242 cmd->resp[1] = readl(host->base + REG_RESPONSE2);
243 cmd->resp[0] = readl(host->base + REG_RESPONSE3);
245 cmd->resp[0] = readl(host->base + REG_RESPONSE0);
250 static void moxart_dma_complete(void *param)
252 struct moxart_host *host = param;
254 complete(&host->dma_complete);
257 static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host)
260 struct dma_async_tx_descriptor *desc = NULL;
261 struct dma_chan *dma_chan;
263 if (host->data_len == data->bytes_xfered)
266 if (data->flags & MMC_DATA_WRITE) {
267 dma_chan = host->dma_chan_tx;
268 dir_slave = DMA_MEM_TO_DEV;
270 dma_chan = host->dma_chan_rx;
271 dir_slave = DMA_DEV_TO_MEM;
274 len = dma_map_sg(dma_chan->device->dev, data->sg,
275 data->sg_len, mmc_get_dma_dir(data));
278 desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
283 dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
287 host->tx_desc = desc;
288 desc->callback = moxart_dma_complete;
289 desc->callback_param = host;
290 dmaengine_submit(desc);
291 dma_async_issue_pending(dma_chan);
294 data->bytes_xfered += host->data_remain;
296 wait_for_completion_interruptible_timeout(&host->dma_complete,
299 dma_unmap_sg(dma_chan->device->dev,
300 data->sg, data->sg_len,
301 mmc_get_dma_dir(data));
305 static void moxart_transfer_pio(struct moxart_host *host)
307 struct mmc_data *data = host->mrq->cmd->data;
308 u32 *sgp, len = 0, remain, status;
310 if (host->data_len == data->bytes_xfered)
313 sgp = sg_virt(host->cur_sg);
314 remain = host->data_remain;
316 if (data->flags & MMC_DATA_WRITE) {
318 if (moxart_wait_for_status(host, FIFO_URUN, &status)
320 data->error = -ETIMEDOUT;
321 complete(&host->pio_complete);
324 for (len = 0; len < remain && len < host->fifo_width;) {
325 iowrite32(*sgp, host->base + REG_DATA_WINDOW);
334 if (moxart_wait_for_status(host, FIFO_ORUN, &status)
336 data->error = -ETIMEDOUT;
337 complete(&host->pio_complete);
340 for (len = 0; len < remain && len < host->fifo_width;) {
341 *sgp = ioread32(host->base + REG_DATA_WINDOW);
349 data->bytes_xfered += host->data_remain - remain;
350 host->data_remain = remain;
352 if (host->data_len != data->bytes_xfered)
353 moxart_next_sg(host);
355 complete(&host->pio_complete);
358 static void moxart_prepare_data(struct moxart_host *host)
360 struct mmc_data *data = host->mrq->cmd->data;
367 host->data_len = data->blocks * data->blksz;
368 blksz_bits = ffs(data->blksz) - 1;
369 BUG_ON(1 << blksz_bits != data->blksz);
371 moxart_init_sg(host, data);
373 datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE);
375 if (data->flags & MMC_DATA_WRITE)
376 datactrl |= DCR_DATA_WRITE;
378 if ((host->data_len > host->fifo_width) && host->have_dma)
379 datactrl |= DCR_DMA_EN;
381 writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL);
382 writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR);
383 writel(host->rate, host->base + REG_DATA_TIMER);
384 writel(host->data_len, host->base + REG_DATA_LENGTH);
385 writel(datactrl, host->base + REG_DATA_CONTROL);
388 static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq)
390 struct moxart_host *host = mmc_priv(mmc);
394 spin_lock_irqsave(&host->lock, flags);
396 init_completion(&host->dma_complete);
397 init_completion(&host->pio_complete);
401 if (readl(host->base + REG_STATUS) & CARD_DETECT) {
402 mrq->cmd->error = -ETIMEDOUT;
406 moxart_prepare_data(host);
407 moxart_send_command(host, host->mrq->cmd);
409 if (mrq->cmd->data) {
410 if ((host->data_len > host->fifo_width) && host->have_dma) {
412 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
414 spin_unlock_irqrestore(&host->lock, flags);
416 moxart_transfer_dma(mrq->cmd->data, host);
418 spin_lock_irqsave(&host->lock, flags);
421 writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK);
423 spin_unlock_irqrestore(&host->lock, flags);
425 /* PIO transfers start from interrupt. */
426 wait_for_completion_interruptible_timeout(&host->pio_complete,
429 spin_lock_irqsave(&host->lock, flags);
432 if (host->is_removed) {
433 dev_err(mmc_dev(host->mmc), "card removed\n");
434 mrq->cmd->error = -ETIMEDOUT;
438 if (moxart_wait_for_status(host, MASK_DATA, &status)
440 mrq->cmd->data->error = -ETIMEDOUT;
444 if (status & DATA_CRC_FAIL)
445 mrq->cmd->data->error = -ETIMEDOUT;
447 if (mrq->cmd->data->stop)
448 moxart_send_command(host, mrq->cmd->data->stop);
452 spin_unlock_irqrestore(&host->lock, flags);
453 mmc_request_done(host->mmc, mrq);
456 static irqreturn_t moxart_irq(int irq, void *devid)
458 struct moxart_host *host = (struct moxart_host *)devid;
461 spin_lock(&host->lock);
463 status = readl(host->base + REG_STATUS);
464 if (status & CARD_CHANGE) {
465 host->is_removed = status & CARD_DETECT;
466 if (host->is_removed && host->have_dma) {
467 dmaengine_terminate_all(host->dma_chan_tx);
468 dmaengine_terminate_all(host->dma_chan_rx);
471 writel(MASK_INTR_PIO, host->base + REG_CLEAR);
472 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
473 mmc_detect_change(host->mmc, 0);
475 if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq)
476 moxart_transfer_pio(host);
478 spin_unlock(&host->lock);
483 static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
485 struct moxart_host *host = mmc_priv(mmc);
490 spin_lock_irqsave(&host->lock, flags);
493 for (div = 0; div < CLK_DIV_MASK; ++div) {
494 if (ios->clock >= host->sysclk / (2 * (div + 1)))
498 host->rate = host->sysclk / (2 * (div + 1));
499 if (host->rate > host->sysclk)
501 writel(ctrl, host->base + REG_CLOCK_CONTROL);
504 if (ios->power_mode == MMC_POWER_OFF) {
505 writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON,
506 host->base + REG_POWER_CONTROL);
508 if (ios->vdd < MIN_POWER)
511 power = ios->vdd - MIN_POWER;
513 writel(SD_POWER_ON | (u32) power,
514 host->base + REG_POWER_CONTROL);
517 switch (ios->bus_width) {
518 case MMC_BUS_WIDTH_4:
519 writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH);
522 writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH);
526 spin_unlock_irqrestore(&host->lock, flags);
530 static int moxart_get_ro(struct mmc_host *mmc)
532 struct moxart_host *host = mmc_priv(mmc);
534 return !!(readl(host->base + REG_STATUS) & WRITE_PROT);
537 static const struct mmc_host_ops moxart_ops = {
538 .request = moxart_request,
539 .set_ios = moxart_set_ios,
540 .get_ro = moxart_get_ro,
543 static int moxart_probe(struct platform_device *pdev)
545 struct device *dev = &pdev->dev;
546 struct device_node *node = dev->of_node;
547 struct resource res_mmc;
548 struct mmc_host *mmc;
549 struct moxart_host *host = NULL;
550 struct dma_slave_config cfg;
552 void __iomem *reg_mmc;
556 mmc = mmc_alloc_host(sizeof(struct moxart_host), dev);
558 dev_err(dev, "mmc_alloc_host failed\n");
563 ret = of_address_to_resource(node, 0, &res_mmc);
565 dev_err(dev, "of_address_to_resource failed\n");
569 irq = irq_of_parse_and_map(node, 0);
571 dev_err(dev, "irq_of_parse_and_map failed\n");
576 clk = devm_clk_get(dev, NULL);
582 reg_mmc = devm_ioremap_resource(dev, &res_mmc);
583 if (IS_ERR(reg_mmc)) {
584 ret = PTR_ERR(reg_mmc);
588 ret = mmc_of_parse(mmc);
592 host = mmc_priv(mmc);
594 host->base = reg_mmc;
595 host->reg_phys = res_mmc.start;
596 host->timeout = msecs_to_jiffies(1000);
597 host->sysclk = clk_get_rate(clk);
598 host->fifo_width = readl(host->base + REG_FEATURE) << 2;
599 host->dma_chan_tx = dma_request_chan(dev, "tx");
600 host->dma_chan_rx = dma_request_chan(dev, "rx");
602 spin_lock_init(&host->lock);
604 mmc->ops = &moxart_ops;
605 mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2);
606 mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2);
607 mmc->ocr_avail = 0xffff00; /* Support 2.0v - 3.6v power. */
608 mmc->max_blk_size = 2048; /* Max. block length in REG_DATA_CONTROL */
609 mmc->max_req_size = DATA_LEN_MASK; /* bits 0-23 in REG_DATA_LENGTH */
610 mmc->max_blk_count = mmc->max_req_size / 512;
612 if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) {
613 if (PTR_ERR(host->dma_chan_tx) == -EPROBE_DEFER ||
614 PTR_ERR(host->dma_chan_rx) == -EPROBE_DEFER) {
618 if (!IS_ERR(host->dma_chan_tx)) {
619 dma_release_channel(host->dma_chan_tx);
620 host->dma_chan_tx = NULL;
622 if (!IS_ERR(host->dma_chan_rx)) {
623 dma_release_channel(host->dma_chan_rx);
624 host->dma_chan_rx = NULL;
626 dev_dbg(dev, "PIO mode transfer enabled\n");
627 host->have_dma = false;
629 mmc->max_seg_size = mmc->max_req_size;
631 dev_dbg(dev, "DMA channels found (%p,%p)\n",
632 host->dma_chan_tx, host->dma_chan_rx);
633 host->have_dma = true;
635 memset(&cfg, 0, sizeof(cfg));
636 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
637 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
639 cfg.direction = DMA_MEM_TO_DEV;
641 cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW;
642 dmaengine_slave_config(host->dma_chan_tx, &cfg);
644 cfg.direction = DMA_DEV_TO_MEM;
645 cfg.src_addr = host->reg_phys + REG_DATA_WINDOW;
647 dmaengine_slave_config(host->dma_chan_rx, &cfg);
649 mmc->max_seg_size = min3(mmc->max_req_size,
650 dma_get_max_seg_size(host->dma_chan_rx->device->dev),
651 dma_get_max_seg_size(host->dma_chan_tx->device->dev));
654 if (readl(host->base + REG_BUS_WIDTH) & BUS_WIDTH_4_SUPPORT)
655 mmc->caps |= MMC_CAP_4_BIT_DATA;
657 writel(0, host->base + REG_INTERRUPT_MASK);
659 writel(CMD_SDC_RESET, host->base + REG_COMMAND);
660 for (i = 0; i < MAX_RETRIES; i++) {
661 if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET))
666 ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host);
670 dev_set_drvdata(dev, mmc);
671 ret = mmc_add_host(mmc);
675 dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width);
680 if (!IS_ERR_OR_NULL(host->dma_chan_tx))
681 dma_release_channel(host->dma_chan_tx);
682 if (!IS_ERR_OR_NULL(host->dma_chan_rx))
683 dma_release_channel(host->dma_chan_rx);
690 static void moxart_remove(struct platform_device *pdev)
692 struct mmc_host *mmc = dev_get_drvdata(&pdev->dev);
693 struct moxart_host *host = mmc_priv(mmc);
695 if (!IS_ERR_OR_NULL(host->dma_chan_tx))
696 dma_release_channel(host->dma_chan_tx);
697 if (!IS_ERR_OR_NULL(host->dma_chan_rx))
698 dma_release_channel(host->dma_chan_rx);
699 mmc_remove_host(mmc);
701 writel(0, host->base + REG_INTERRUPT_MASK);
702 writel(0, host->base + REG_POWER_CONTROL);
703 writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF,
704 host->base + REG_CLOCK_CONTROL);
708 static const struct of_device_id moxart_mmc_match[] = {
709 { .compatible = "moxa,moxart-mmc" },
710 { .compatible = "faraday,ftsdc010" },
713 MODULE_DEVICE_TABLE(of, moxart_mmc_match);
715 static struct platform_driver moxart_mmc_driver = {
716 .probe = moxart_probe,
717 .remove_new = moxart_remove,
719 .name = "mmc-moxart",
720 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
721 .of_match_table = moxart_mmc_match,
724 module_platform_driver(moxart_mmc_driver);
726 MODULE_ALIAS("platform:mmc-moxart");
727 MODULE_DESCRIPTION("MOXA ART MMC driver");
728 MODULE_LICENSE("GPL v2");
729 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");