2 * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #define MMCIPOWER 0x000
11 #define MCI_PWR_OFF 0x00
12 #define MCI_PWR_UP 0x02
13 #define MCI_PWR_ON 0x03
14 #define MCI_OD (1 << 6)
15 #define MCI_ROD (1 << 7)
17 * The ST Micro version does not have ROD and reuse the voltage registers for
20 #define MCI_ST_DATA2DIREN (1 << 2)
21 #define MCI_ST_CMDDIREN (1 << 3)
22 #define MCI_ST_DATA0DIREN (1 << 4)
23 #define MCI_ST_DATA31DIREN (1 << 5)
24 #define MCI_ST_FBCLKEN (1 << 7)
25 #define MCI_ST_DATA74DIREN (1 << 8)
27 * The STM32 sdmmc does not have PWR_UP/OD/ROD
28 * and uses the power register for
30 #define MCI_STM32_PWR_CYC 0x02
31 #define MCI_STM32_VSWITCH BIT(2)
32 #define MCI_STM32_VSWITCHEN BIT(3)
33 #define MCI_STM32_DIRPOL BIT(4)
35 #define MMCICLOCK 0x004
36 #define MCI_CLK_ENABLE (1 << 8)
37 #define MCI_CLK_PWRSAVE (1 << 9)
38 #define MCI_CLK_BYPASS (1 << 10)
39 #define MCI_4BIT_BUS (1 << 11)
41 * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
42 * supported in ST Micro U300 and Ux500 versions
44 #define MCI_ST_8BIT_BUS (1 << 12)
45 #define MCI_ST_U300_HWFCEN (1 << 13)
46 #define MCI_ST_UX500_NEG_EDGE (1 << 13)
47 #define MCI_ST_UX500_HWFCEN (1 << 14)
48 #define MCI_ST_UX500_CLK_INV (1 << 15)
49 /* Modified PL180 on Versatile Express platform */
50 #define MCI_ARM_HWFCEN (1 << 12)
52 /* Modified on Qualcomm Integrations */
53 #define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11))
54 #define MCI_QCOM_CLK_FLOWENA BIT(12)
55 #define MCI_QCOM_CLK_INVERTOUT BIT(13)
57 /* select in latch data and command in */
58 #define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
59 #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
61 /* Modified on STM32 sdmmc */
62 #define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0)
63 #define MCI_STM32_CLK_WIDEBUS_4 BIT(14)
64 #define MCI_STM32_CLK_WIDEBUS_8 BIT(15)
65 #define MCI_STM32_CLK_NEGEDGE BIT(16)
66 #define MCI_STM32_CLK_HWFCEN BIT(17)
67 #define MCI_STM32_CLK_DDR BIT(18)
68 #define MCI_STM32_CLK_BUSSPEED BIT(19)
69 #define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20)
70 #define MCI_STM32_CLK_SELCK (0 << 20)
71 #define MCI_STM32_CLK_SELCKIN (1 << 20)
72 #define MCI_STM32_CLK_SELFBCK (2 << 20)
74 #define MMCIARGUMENT 0x008
76 /* The command register controls the Command Path State Machine (CPSM) */
77 #define MMCICOMMAND 0x00c
78 #define MCI_CPSM_RESPONSE BIT(6)
79 #define MCI_CPSM_LONGRSP BIT(7)
80 #define MCI_CPSM_INTERRUPT BIT(8)
81 #define MCI_CPSM_PENDING BIT(9)
82 #define MCI_CPSM_ENABLE BIT(10)
83 /* Command register flag extenstions in the ST Micro versions */
84 #define MCI_CPSM_ST_SDIO_SUSP BIT(11)
85 #define MCI_CPSM_ST_ENCMD_COMPL BIT(12)
86 #define MCI_CPSM_ST_NIEN BIT(13)
87 #define MCI_CPSM_ST_CE_ATACMD BIT(14)
88 /* Command register flag extensions in the Qualcomm versions */
89 #define MCI_CPSM_QCOM_PROGENA BIT(11)
90 #define MCI_CPSM_QCOM_DATCMD BIT(12)
91 #define MCI_CPSM_QCOM_MCIABORT BIT(13)
92 #define MCI_CPSM_QCOM_CCSENABLE BIT(14)
93 #define MCI_CPSM_QCOM_CCSDISABLE BIT(15)
94 #define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16)
95 #define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21)
96 /* Command register in STM32 sdmmc versions */
97 #define MCI_CPSM_STM32_CMDTRANS BIT(6)
98 #define MCI_CPSM_STM32_CMDSTOP BIT(7)
99 #define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8)
100 #define MCI_CPSM_STM32_NORSP (0 << 8)
101 #define MCI_CPSM_STM32_SRSP_CRC (1 << 8)
102 #define MCI_CPSM_STM32_SRSP (2 << 8)
103 #define MCI_CPSM_STM32_LRSP_CRC (3 << 8)
104 #define MCI_CPSM_STM32_ENABLE BIT(12)
106 #define MMCIRESPCMD 0x010
107 #define MMCIRESPONSE0 0x014
108 #define MMCIRESPONSE1 0x018
109 #define MMCIRESPONSE2 0x01c
110 #define MMCIRESPONSE3 0x020
111 #define MMCIDATATIMER 0x024
112 #define MMCIDATALENGTH 0x028
114 /* The data control register controls the Data Path State Machine (DPSM) */
115 #define MMCIDATACTRL 0x02c
116 #define MCI_DPSM_ENABLE BIT(0)
117 #define MCI_DPSM_DIRECTION BIT(1)
118 #define MCI_DPSM_MODE BIT(2)
119 #define MCI_DPSM_DMAENABLE BIT(3)
120 #define MCI_DPSM_BLOCKSIZE BIT(4)
121 /* Control register extensions in the ST Micro U300 and Ux500 versions */
122 #define MCI_DPSM_ST_RWSTART BIT(8)
123 #define MCI_DPSM_ST_RWSTOP BIT(9)
124 #define MCI_DPSM_ST_RWMOD BIT(10)
125 #define MCI_DPSM_ST_SDIOEN BIT(11)
126 /* Control register extensions in the ST Micro Ux500 versions */
127 #define MCI_DPSM_ST_DMAREQCTL BIT(12)
128 #define MCI_DPSM_ST_DBOOTMODEEN BIT(13)
129 #define MCI_DPSM_ST_BUSYMODE BIT(14)
130 #define MCI_DPSM_ST_DDRMODE BIT(15)
131 /* Control register extensions in the Qualcomm versions */
132 #define MCI_DPSM_QCOM_DATA_PEND BIT(17)
133 #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
134 /* Control register extensions in STM32 versions */
135 #define MCI_DPSM_STM32_MODE_BLOCK (0 << 2)
136 #define MCI_DPSM_STM32_MODE_SDIO (1 << 2)
137 #define MCI_DPSM_STM32_MODE_STREAM (2 << 2)
138 #define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2)
140 #define MMCIDATACNT 0x030
141 #define MMCISTATUS 0x034
142 #define MCI_CMDCRCFAIL (1 << 0)
143 #define MCI_DATACRCFAIL (1 << 1)
144 #define MCI_CMDTIMEOUT (1 << 2)
145 #define MCI_DATATIMEOUT (1 << 3)
146 #define MCI_TXUNDERRUN (1 << 4)
147 #define MCI_RXOVERRUN (1 << 5)
148 #define MCI_CMDRESPEND (1 << 6)
149 #define MCI_CMDSENT (1 << 7)
150 #define MCI_DATAEND (1 << 8)
151 #define MCI_STARTBITERR (1 << 9)
152 #define MCI_DATABLOCKEND (1 << 10)
153 #define MCI_CMDACTIVE (1 << 11)
154 #define MCI_TXACTIVE (1 << 12)
155 #define MCI_RXACTIVE (1 << 13)
156 #define MCI_TXFIFOHALFEMPTY (1 << 14)
157 #define MCI_RXFIFOHALFFULL (1 << 15)
158 #define MCI_TXFIFOFULL (1 << 16)
159 #define MCI_RXFIFOFULL (1 << 17)
160 #define MCI_TXFIFOEMPTY (1 << 18)
161 #define MCI_RXFIFOEMPTY (1 << 19)
162 #define MCI_TXDATAAVLBL (1 << 20)
163 #define MCI_RXDATAAVLBL (1 << 21)
164 /* Extended status bits for the ST Micro variants */
165 #define MCI_ST_SDIOIT (1 << 22)
166 #define MCI_ST_CEATAEND (1 << 23)
167 #define MCI_ST_CARDBUSY (1 << 24)
168 /* Extended status bits for the STM32 variants */
169 #define MCI_STM32_BUSYD0 BIT(20)
171 #define MMCICLEAR 0x038
172 #define MCI_CMDCRCFAILCLR (1 << 0)
173 #define MCI_DATACRCFAILCLR (1 << 1)
174 #define MCI_CMDTIMEOUTCLR (1 << 2)
175 #define MCI_DATATIMEOUTCLR (1 << 3)
176 #define MCI_TXUNDERRUNCLR (1 << 4)
177 #define MCI_RXOVERRUNCLR (1 << 5)
178 #define MCI_CMDRESPENDCLR (1 << 6)
179 #define MCI_CMDSENTCLR (1 << 7)
180 #define MCI_DATAENDCLR (1 << 8)
181 #define MCI_STARTBITERRCLR (1 << 9)
182 #define MCI_DATABLOCKENDCLR (1 << 10)
183 /* Extended status bits for the ST Micro variants */
184 #define MCI_ST_SDIOITC (1 << 22)
185 #define MCI_ST_CEATAENDC (1 << 23)
186 #define MCI_ST_BUSYENDC (1 << 24)
188 #define MMCIMASK0 0x03c
189 #define MCI_CMDCRCFAILMASK (1 << 0)
190 #define MCI_DATACRCFAILMASK (1 << 1)
191 #define MCI_CMDTIMEOUTMASK (1 << 2)
192 #define MCI_DATATIMEOUTMASK (1 << 3)
193 #define MCI_TXUNDERRUNMASK (1 << 4)
194 #define MCI_RXOVERRUNMASK (1 << 5)
195 #define MCI_CMDRESPENDMASK (1 << 6)
196 #define MCI_CMDSENTMASK (1 << 7)
197 #define MCI_DATAENDMASK (1 << 8)
198 #define MCI_STARTBITERRMASK (1 << 9)
199 #define MCI_DATABLOCKENDMASK (1 << 10)
200 #define MCI_CMDACTIVEMASK (1 << 11)
201 #define MCI_TXACTIVEMASK (1 << 12)
202 #define MCI_RXACTIVEMASK (1 << 13)
203 #define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
204 #define MCI_RXFIFOHALFFULLMASK (1 << 15)
205 #define MCI_TXFIFOFULLMASK (1 << 16)
206 #define MCI_RXFIFOFULLMASK (1 << 17)
207 #define MCI_TXFIFOEMPTYMASK (1 << 18)
208 #define MCI_RXFIFOEMPTYMASK (1 << 19)
209 #define MCI_TXDATAAVLBLMASK (1 << 20)
210 #define MCI_RXDATAAVLBLMASK (1 << 21)
211 /* Extended status bits for the ST Micro variants */
212 #define MCI_ST_SDIOITMASK (1 << 22)
213 #define MCI_ST_CEATAENDMASK (1 << 23)
214 #define MCI_ST_BUSYENDMASK (1 << 24)
215 /* Extended status bits for the STM32 variants */
216 #define MCI_STM32_BUSYD0ENDMASK BIT(21)
218 #define MMCIMASK1 0x040
219 #define MMCIFIFOCNT 0x048
220 #define MMCIFIFO 0x080 /* to 0x0bc */
222 /* STM32 sdmmc registers for IDMA (Internal DMA) */
223 #define MMCI_STM32_IDMACTRLR 0x050
224 #define MMCI_STM32_IDMAEN BIT(0)
225 #define MMCI_STM32_IDMALLIEN BIT(1)
227 #define MMCI_STM32_IDMABSIZER 0x054
228 #define MMCI_STM32_IDMABNDT_SHIFT 5
229 #define MMCI_STM32_IDMABNDT_MASK GENMASK(12, 5)
231 #define MMCI_STM32_IDMABASE0R 0x058
233 #define MMCI_STM32_IDMALAR 0x64
234 #define MMCI_STM32_IDMALA_MASK GENMASK(13, 0)
235 #define MMCI_STM32_ABR BIT(29)
236 #define MMCI_STM32_ULS BIT(30)
237 #define MMCI_STM32_ULA BIT(31)
239 #define MMCI_STM32_IDMABAR 0x68
241 #define MCI_IRQENABLE \
242 (MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
243 MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \
244 MCI_CMDRESPENDMASK | MCI_CMDSENTMASK)
246 /* These interrupts are directed to IRQ1 when two IRQ lines are available */
247 #define MCI_IRQ_PIO_MASK \
248 (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
249 MCI_TXFIFOHALFEMPTYMASK)
251 #define MCI_IRQ_PIO_STM32_MASK \
252 (MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)
256 #define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
263 * struct variant_data - MMCI variant-specific quirks
264 * @clkreg: default value for MCICLOCK register
265 * @clkreg_enable: enable value for MMCICLOCK register
266 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
267 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
268 * @cmdreg_cpsm_enable: enable value for CPSM
269 * @cmdreg_lrsp_crc: enable value for long response with crc
270 * @cmdreg_srsp_crc: enable value for short response with crc
271 * @cmdreg_srsp: enable value for short response without crc
272 * @cmdreg_stop: enable value for stop and abort transmission
273 * @datalength_bits: number of bits in the MMCIDATALENGTH register
274 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
275 * is asserted (likewise for RX)
276 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
277 * is asserted (likewise for RX)
278 * @data_cmd_enable: enable value for data commands.
279 * @st_sdio: enable ST specific SDIO logic
280 * @st_clkdiv: true if using a ST-specific clock divider algorithm
281 * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm
282 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
283 * @datactrl_mask_sdio: SDIO enable mask in datactrl register
284 * @datactrl_blksz: block size in power of two
285 * @datactrl_first: true if data must be setup before send command
286 * @datacnt_useless: true if you could not use datacnt register to read
288 * @pwrreg_powerup: power up value for MMCIPOWER register
289 * @f_max: maximum clk frequency supported by the controller.
290 * @signal_direction: input/out direction of bus signals can be indicated
291 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
292 * @busy_detect: true if the variant supports busy detection on DAT0.
293 * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
294 * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
295 * indicating that the card is busy
296 * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
297 * getting busy end detection interrupts
298 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
299 * @explicit_mclk_control: enable explicit mclk control in driver.
300 * @qcom_fifo: enables qcom specific fifo pio read logic.
301 * @qcom_dml: enables qcom specific dma glue for dma transfers.
302 * @reversed_irq_handling: handle data irq before cmd irq.
303 * @mmcimask1: true if variant have a MMCIMASK1 register.
304 * @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask
306 * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
308 * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
309 * @dma_lli: true if variant has dma link list feature.
310 * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
312 struct variant_data {
314 unsigned int clkreg_enable;
315 unsigned int clkreg_8bit_bus_enable;
316 unsigned int clkreg_neg_edge_enable;
317 unsigned int cmdreg_cpsm_enable;
318 unsigned int cmdreg_lrsp_crc;
319 unsigned int cmdreg_srsp_crc;
320 unsigned int cmdreg_srsp;
321 unsigned int cmdreg_stop;
322 unsigned int datalength_bits;
323 unsigned int fifosize;
324 unsigned int fifohalfsize;
325 unsigned int data_cmd_enable;
326 unsigned int datactrl_mask_ddrmode;
327 unsigned int datactrl_mask_sdio;
328 unsigned int datactrl_blocksz;
330 u8 datacnt_useless:1;
336 u8 signal_direction:1;
340 u32 busy_detect_flag;
341 u32 busy_detect_mask;
343 u8 explicit_mclk_control:1;
346 u8 reversed_irq_handling:1;
348 unsigned int irq_pio_mask;
352 u32 stm32_idmabsize_mask;
353 void (*init)(struct mmci_host *host);
356 /* mmci variant callbacks */
357 struct mmci_host_ops {
358 int (*validate_data)(struct mmci_host *host, struct mmc_data *data);
359 int (*prep_data)(struct mmci_host *host, struct mmc_data *data,
361 void (*unprep_data)(struct mmci_host *host, struct mmc_data *data,
363 u32 (*get_datactrl_cfg)(struct mmci_host *host);
364 void (*get_next_data)(struct mmci_host *host, struct mmc_data *data);
365 int (*dma_setup)(struct mmci_host *host);
366 void (*dma_release)(struct mmci_host *host);
367 int (*dma_start)(struct mmci_host *host, unsigned int *datactrl);
368 void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data);
369 void (*dma_error)(struct mmci_host *host);
370 void (*set_clkreg)(struct mmci_host *host, unsigned int desired);
371 void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr);
377 struct mmc_request *mrq;
378 struct mmc_command *cmd;
379 struct mmc_command stop_abort;
380 struct mmc_data *data;
381 struct mmc_host *mmc;
385 struct reset_control *rst;
390 /* cached value of requested clk in set_ios */
391 unsigned int clock_cache;
401 struct mmci_platform_data *plat;
402 struct mmci_host_ops *ops;
403 struct variant_data *variant;
404 struct pinctrl *pinctrl;
405 struct pinctrl_state *pins_default;
406 struct pinctrl_state *pins_opendrain;
411 struct timer_list timer;
412 unsigned int oldstat;
415 struct sg_mapping_iter sg_miter;
417 int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain);
420 u8 dma_in_progress:1;
426 #define dma_inprogress(host) ((host)->dma_in_progress)
428 void mmci_write_clkreg(struct mmci_host *host, u32 clk);
429 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr);
431 static inline u32 mmci_dctrl_blksz(struct mmci_host *host)
433 return (ffs(host->data->blksz) - 1) << 4;
436 #ifdef CONFIG_DMA_ENGINE
437 int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
439 void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data,
441 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data);
442 int mmci_dmae_setup(struct mmci_host *host);
443 void mmci_dmae_release(struct mmci_host *host);
444 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl);
445 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data);
446 void mmci_dmae_error(struct mmci_host *host);
449 #ifdef CONFIG_MMC_QCOM_DML
450 void qcom_variant_init(struct mmci_host *host);
452 static inline void qcom_variant_init(struct mmci_host *host) {}
455 #ifdef CONFIG_MMC_STM32_SDMMC
456 void sdmmc_variant_init(struct mmci_host *host);
458 static inline void sdmmc_variant_init(struct mmci_host *host) {}