drivers/mmc/host/mmci.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
   4  *
   5  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   6  *  Copyright (C) 2010 ST-Ericsson SA
   7  */
   8 #include <linux/module.h>
   9 #include <linux/moduleparam.h>
  10 #include <linux/init.h>
  11 #include <linux/ioport.h>
  12 #include <linux/device.h>
  13 #include <linux/io.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/slab.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/highmem.h>
  20 #include <linux/log2.h>
  21 #include <linux/mmc/mmc.h>
  22 #include <linux/mmc/pm.h>
  23 #include <linux/mmc/host.h>
  24 #include <linux/mmc/card.h>
  25 #include <linux/mmc/slot-gpio.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/clk.h>
  28 #include <linux/scatterlist.h>
  29 #include <linux/of.h>
  30 #include <linux/regulator/consumer.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/amba/mmci.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/types.h>
  36 #include <linux/pinctrl/consumer.h>
  37 #include <linux/reset.h>
  38
  39 #include <asm/div64.h>
  40 #include <asm/io.h>
  41
  42 #include "mmci.h"
  43
  44 #define DRIVER_NAME "mmci-pl18x"
  45
  46 static void mmci_variant_init(struct mmci_host *host);
  47 static void ux500_variant_init(struct mmci_host *host);
  48 static void ux500v2_variant_init(struct mmci_host *host);
  49
  50 static unsigned int fmax = 515633;
  51
  52 static struct variant_data variant_arm = {
  53         .fifosize               = 16 * 4,
  54         .fifohalfsize           = 8 * 4,
  55         .cmdreg_cpsm_enable     = MCI_CPSM_ENABLE,
  56         .cmdreg_lrsp_crc        = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  57         .cmdreg_srsp_crc        = MCI_CPSM_RESPONSE,
  58         .cmdreg_srsp            = MCI_CPSM_RESPONSE,
  59         .datalength_bits        = 16,
  60         .datactrl_blocksz       = 11,
  61         .pwrreg_powerup         = MCI_PWR_UP,
  62         .f_max                  = 100000000,
  63         .reversed_irq_handling  = true,
  64         .mmcimask1              = true,
  65         .irq_pio_mask           = MCI_IRQ_PIO_MASK,
  66         .start_err              = MCI_STARTBITERR,
  67         .opendrain              = MCI_ROD,
  68         .init                   = mmci_variant_init,
  69 };
  70
  71 static struct variant_data variant_arm_extended_fifo = {
  72         .fifosize               = 128 * 4,
  73         .fifohalfsize           = 64 * 4,
  74         .cmdreg_cpsm_enable     = MCI_CPSM_ENABLE,
  75         .cmdreg_lrsp_crc        = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  76         .cmdreg_srsp_crc        = MCI_CPSM_RESPONSE,
  77         .cmdreg_srsp            = MCI_CPSM_RESPONSE,
  78         .datalength_bits        = 16,
  79         .datactrl_blocksz       = 11,
  80         .pwrreg_powerup         = MCI_PWR_UP,
  81         .f_max                  = 100000000,
  82         .mmcimask1              = true,
  83         .irq_pio_mask           = MCI_IRQ_PIO_MASK,
  84         .start_err              = MCI_STARTBITERR,
  85         .opendrain              = MCI_ROD,
  86         .init                   = mmci_variant_init,
  87 };
  88
  89 static struct variant_data variant_arm_extended_fifo_hwfc = {
  90         .fifosize               = 128 * 4,
  91         .fifohalfsize           = 64 * 4,
  92         .clkreg_enable          = MCI_ARM_HWFCEN,
  93         .cmdreg_cpsm_enable     = MCI_CPSM_ENABLE,
  94         .cmdreg_lrsp_crc        = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
  95         .cmdreg_srsp_crc        = MCI_CPSM_RESPONSE,
  96         .cmdreg_srsp            = MCI_CPSM_RESPONSE,
  97         .datalength_bits        = 16,
  98         .datactrl_blocksz       = 11,
  99         .pwrreg_powerup         = MCI_PWR_UP,
 100         .f_max                  = 100000000,
 101         .mmcimask1              = true,
 102         .irq_pio_mask           = MCI_IRQ_PIO_MASK,
 103         .start_err              = MCI_STARTBITERR,
 104         .opendrain              = MCI_ROD,
 105         .init                   = mmci_variant_init,
 106 };
 107
 108 static struct variant_data variant_u300 = {
 109         .fifosize               = 16 * 4,
 110         .fifohalfsize           = 8 * 4,
 111         .clkreg_enable          = MCI_ST_U300_HWFCEN,
 112         .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 113         .cmdreg_cpsm_enable     = MCI_CPSM_ENABLE,
 114         .cmdreg_lrsp_crc        = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
 115         .cmdreg_srsp_crc        = MCI_CPSM_RESPONSE,
 116         .cmdreg_srsp            = MCI_CPSM_RESPONSE,
 117         .datalength_bits        = 16,
 118         .datactrl_blocksz       = 11,
 119         .datactrl_mask_sdio     = MCI_DPSM_ST_SDIOEN,
 120         .st_sdio                        = true,
 121         .pwrreg_powerup         = MCI_PWR_ON,
 122         .f_max                  = 100000000,
 123         .signal_direction       = true,
 124         .pwrreg_clkgate         = true,
 125         .pwrreg_nopower         = true,
 126         .mmcimask1              = true,
 127         .irq_pio_mask           = MCI_IRQ_PIO_MASK,
 128         .start_err              = MCI_STARTBITERR,
 129         .opendrain              = MCI_OD,
 130         .init                   = mmci_variant_init,
 131 };
 132
 133 static struct variant_data variant_nomadik = {
 134         .fifosize               = 16 * 4,
 135         .fifohalfsize           = 8 * 4,
 136         .clkreg                 = MCI_CLK_ENABLE,
 137         .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 138         .cmdreg_cpsm_enable     = MCI_CPSM_ENABLE,
 139         .cmdreg_lrsp_crc        = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
 140         .cmdreg_srsp_crc        = MCI_CPSM_RESPONSE,
 141         .cmdreg_srsp            = MCI_CPSM_RESPONSE,
 142         .datalength_bits        = 24,
 143         .datactrl_blocksz       = 11,
 144         .datactrl_mask_sdio     = MCI_DPSM_ST_SDIOEN,
 145         .st_sdio                = true,
 146         .st_clkdiv              = true,
 147         .pwrreg_powerup         = MCI_PWR_ON,
 148         .f_max                  = 100000000,
 149         .signal_direction       = true,
 150         .pwrreg_clkgate         = true,
 151         .pwrreg_nopower         = true,
 152         .mmcimask1              = true,
 153         .irq_pio_mask           = MCI_IRQ_PIO_MASK,
 154         .start_err              = MCI_STARTBITERR,
 155         .opendrain              = MCI_OD,
 156         .init                   = mmci_variant_init,
 157 };
 158
 159 static struct variant_data variant_ux500 = {
 160         .fifosize               = 30 * 4,
 161         .fifohalfsize           = 8 * 4,
 162         .clkreg                 = MCI_CLK_ENABLE,
 163         .clkreg_enable          = MCI_ST_UX500_HWFCEN,
 164         .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 165         .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
 166         .cmdreg_cpsm_enable     = MCI_CPSM_ENABLE,
 167         .cmdreg_lrsp_crc        = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
 168         .cmdreg_srsp_crc        = MCI_CPSM_RESPONSE,
 169         .cmdreg_srsp            = MCI_CPSM_RESPONSE,
 170         .datalength_bits        = 24,
 171         .datactrl_blocksz       = 11,
 172         .datactrl_any_blocksz   = true,
 173         .dma_power_of_2         = true,
 174         .datactrl_mask_sdio     = MCI_DPSM_ST_SDIOEN,
 175         .st_sdio                = true,
 176         .st_clkdiv              = true,
 177         .pwrreg_powerup         = MCI_PWR_ON,
 178         .f_max                  = 100000000,
 179         .signal_direction       = true,
 180         .pwrreg_clkgate         = true,
 181         .busy_detect            = true,
 182         .busy_dpsm_flag         = MCI_DPSM_ST_BUSYMODE,
 183         .busy_detect_flag       = MCI_ST_CARDBUSY,
 184         .busy_detect_mask       = MCI_ST_BUSYENDMASK,
 185         .pwrreg_nopower         = true,
 186         .mmcimask1              = true,
 187         .irq_pio_mask           = MCI_IRQ_PIO_MASK,
 188         .start_err              = MCI_STARTBITERR,
 189         .opendrain              = MCI_OD,
 190         .init                   = ux500_variant_init,
 191 };
 192
 193 static struct variant_data variant_ux500v2 = {
 194         .fifosize               = 30 * 4,
 195         .fifohalfsize           = 8 * 4,
 196         .clkreg                 = MCI_CLK_ENABLE,
 197         .clkreg_enable          = MCI_ST_UX500_HWFCEN,
 198         .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 199         .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
 200         .cmdreg_cpsm_enable     = MCI_CPSM_ENABLE,
 201         .cmdreg_lrsp_crc        = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
 202         .cmdreg_srsp_crc        = MCI_CPSM_RESPONSE,
 203         .cmdreg_srsp            = MCI_CPSM_RESPONSE,
 204         .datactrl_mask_ddrmode  = MCI_DPSM_ST_DDRMODE,
 205         .datalength_bits        = 24,
 206         .datactrl_blocksz       = 11,
 207         .datactrl_any_blocksz   = true,
 208         .dma_power_of_2         = true,
 209         .datactrl_mask_sdio     = MCI_DPSM_ST_SDIOEN,
 210         .st_sdio                = true,
 211         .st_clkdiv              = true,
 212         .pwrreg_powerup         = MCI_PWR_ON,
 213         .f_max                  = 100000000,
 214         .signal_direction       = true,
 215         .pwrreg_clkgate         = true,
 216         .busy_detect            = true,
 217         .busy_dpsm_flag         = MCI_DPSM_ST_BUSYMODE,
 218         .busy_detect_flag       = MCI_ST_CARDBUSY,
 219         .busy_detect_mask       = MCI_ST_BUSYENDMASK,
 220         .pwrreg_nopower         = true,
 221         .mmcimask1              = true,
 222         .irq_pio_mask           = MCI_IRQ_PIO_MASK,
 223         .start_err              = MCI_STARTBITERR,
 224         .opendrain              = MCI_OD,
 225         .init                   = ux500v2_variant_init,
 226 };
 227
 228 static struct variant_data variant_stm32 = {
 229         .fifosize               = 32 * 4,
 230         .fifohalfsize           = 8 * 4,
 231         .clkreg                 = MCI_CLK_ENABLE,
 232         .clkreg_enable          = MCI_ST_UX500_HWFCEN,
 233         .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 234         .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
 235         .cmdreg_cpsm_enable     = MCI_CPSM_ENABLE,
 236         .cmdreg_lrsp_crc        = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
 237         .cmdreg_srsp_crc        = MCI_CPSM_RESPONSE,
 238         .cmdreg_srsp            = MCI_CPSM_RESPONSE,
 239         .irq_pio_mask           = MCI_IRQ_PIO_MASK,
 240         .datalength_bits        = 24,
 241         .datactrl_blocksz       = 11,
 242         .datactrl_mask_sdio     = MCI_DPSM_ST_SDIOEN,
 243         .st_sdio                = true,
 244         .st_clkdiv              = true,
 245         .pwrreg_powerup         = MCI_PWR_ON,
 246         .f_max                  = 48000000,
 247         .pwrreg_clkgate         = true,
 248         .pwrreg_nopower         = true,
 249         .init                   = mmci_variant_init,
 250 };
 251
 252 static struct variant_data variant_stm32_sdmmc = {
 253         .fifosize               = 16 * 4,
 254         .fifohalfsize           = 8 * 4,
 255         .f_max                  = 208000000,
 256         .stm32_clkdiv           = true,
 257         .cmdreg_cpsm_enable     = MCI_CPSM_STM32_ENABLE,
 258         .cmdreg_lrsp_crc        = MCI_CPSM_STM32_LRSP_CRC,
 259         .cmdreg_srsp_crc        = MCI_CPSM_STM32_SRSP_CRC,
 260         .cmdreg_srsp            = MCI_CPSM_STM32_SRSP,
 261         .cmdreg_stop            = MCI_CPSM_STM32_CMDSTOP,
 262         .data_cmd_enable        = MCI_CPSM_STM32_CMDTRANS,
 263         .irq_pio_mask           = MCI_IRQ_PIO_STM32_MASK,
 264         .datactrl_first         = true,
 265         .datacnt_useless        = true,
 266         .datalength_bits        = 25,
 267         .datactrl_blocksz       = 14,
 268         .datactrl_any_blocksz   = true,
 269         .stm32_idmabsize_mask   = GENMASK(12, 5),
 270         .busy_timeout           = true,
 271         .busy_detect            = true,
 272         .busy_detect_flag       = MCI_STM32_BUSYD0,
 273         .busy_detect_mask       = MCI_STM32_BUSYD0ENDMASK,
 274         .init                   = sdmmc_variant_init,
 275 };
 276
 277 static struct variant_data variant_qcom = {
 278         .fifosize               = 16 * 4,
 279         .fifohalfsize           = 8 * 4,
 280         .clkreg                 = MCI_CLK_ENABLE,
 281         .clkreg_enable          = MCI_QCOM_CLK_FLOWENA |
 282                                   MCI_QCOM_CLK_SELECT_IN_FBCLK,
 283         .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
 284         .datactrl_mask_ddrmode  = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
 285         .cmdreg_cpsm_enable     = MCI_CPSM_ENABLE,
 286         .cmdreg_lrsp_crc        = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
 287         .cmdreg_srsp_crc        = MCI_CPSM_RESPONSE,
 288         .cmdreg_srsp            = MCI_CPSM_RESPONSE,
 289         .data_cmd_enable        = MCI_CPSM_QCOM_DATCMD,
 290         .datalength_bits        = 24,
 291         .datactrl_blocksz       = 11,
 292         .datactrl_any_blocksz   = true,
 293         .pwrreg_powerup         = MCI_PWR_UP,
 294         .f_max                  = 208000000,
 295         .explicit_mclk_control  = true,
 296         .qcom_fifo              = true,
 297         .qcom_dml               = true,
 298         .mmcimask1              = true,
 299         .irq_pio_mask           = MCI_IRQ_PIO_MASK,
 300         .start_err              = MCI_STARTBITERR,
 301         .opendrain              = MCI_ROD,
 302         .init                   = qcom_variant_init,
 303 };
 304
 305 /* Busy detection for the ST Micro variant */
 306 static int mmci_card_busy(struct mmc_host *mmc)
 307 {
 308         struct mmci_host *host = mmc_priv(mmc);
 309         unsigned long flags;
 310         int busy = 0;
 311
 312         spin_lock_irqsave(&host->lock, flags);
 313         if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
 314                 busy = 1;
 315         spin_unlock_irqrestore(&host->lock, flags);
 316
 317         return busy;
 318 }
 319
 320 static void mmci_reg_delay(struct mmci_host *host)
 321 {
 322         /*
 323          * According to the spec, at least three feedback clock cycles
 324          * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
 325          * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
 326          * Worst delay time during card init is at 100 kHz => 30 us.
 327          * Worst delay time when up and running is at 25 MHz => 120 ns.
 328          */
 329         if (host->cclk < 25000000)
 330                 udelay(30);
 331         else
 332                 ndelay(120);
 333 }
 334
 335 /*
 336  * This must be called with host->lock held
 337  */
 338 void mmci_write_clkreg(struct mmci_host *host, u32 clk)
 339 {
 340         if (host->clk_reg != clk) {
 341                 host->clk_reg = clk;
 342                 writel(clk, host->base + MMCICLOCK);
 343         }
 344 }
 345
 346 /*
 347  * This must be called with host->lock held
 348  */
 349 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
 350 {
 351         if (host->pwr_reg != pwr) {
 352                 host->pwr_reg = pwr;
 353                 writel(pwr, host->base + MMCIPOWER);
 354         }
 355 }
 356
 357 /*
 358  * This must be called with host->lock held
 359  */
 360 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
 361 {
 362         /* Keep busy mode in DPSM if enabled */
 363         datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
 364
 365         if (host->datactrl_reg != datactrl) {
 366                 host->datactrl_reg = datactrl;
 367                 writel(datactrl, host->base + MMCIDATACTRL);
 368         }
 369 }
 370
 371 /*
 372  * This must be called with host->lock held
 373  */
 374 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 375 {
 376         struct variant_data *variant = host->variant;
 377         u32 clk = variant->clkreg;
 378
 379         /* Make sure cclk reflects the current calculated clock */
 380         host->cclk = 0;
 381
 382         if (desired) {
 383                 if (variant->explicit_mclk_control) {
 384                         host->cclk = host->mclk;
 385                 } else if (desired >= host->mclk) {
 386                         clk = MCI_CLK_BYPASS;
 387                         if (variant->st_clkdiv)
 388                                 clk |= MCI_ST_UX500_NEG_EDGE;
 389                         host->cclk = host->mclk;
 390                 } else if (variant->st_clkdiv) {
 391                         /*
 392                          * DB8500 TRM says f = mclk / (clkdiv + 2)
 393                          * => clkdiv = (mclk / f) - 2
 394                          * Round the divider up so we don't exceed the max
 395                          * frequency
 396                          */
 397                         clk = DIV_ROUND_UP(host->mclk, desired) - 2;
 398                         if (clk >= 256)
 399                                 clk = 255;
 400                         host->cclk = host->mclk / (clk + 2);
 401                 } else {
 402                         /*
 403                          * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
 404                          * => clkdiv = mclk / (2 * f) - 1
 405                          */
 406                         clk = host->mclk / (2 * desired) - 1;
 407                         if (clk >= 256)
 408                                 clk = 255;
 409                         host->cclk = host->mclk / (2 * (clk + 1));
 410                 }
 411
 412                 clk |= variant->clkreg_enable;
 413                 clk |= MCI_CLK_ENABLE;
 414                 /* This hasn't proven to be worthwhile */
 415                 /* clk |= MCI_CLK_PWRSAVE; */
 416         }
 417
 418         /* Set actual clock for debug */
 419         host->mmc->actual_clock = host->cclk;
 420
 421         if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
 422                 clk |= MCI_4BIT_BUS;
 423         if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
 424                 clk |= variant->clkreg_8bit_bus_enable;
 425
 426         if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
 427             host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
 428                 clk |= variant->clkreg_neg_edge_enable;
 429
 430         mmci_write_clkreg(host, clk);
 431 }
 432
 433 static void mmci_dma_release(struct mmci_host *host)
 434 {
 435         if (host->ops && host->ops->dma_release)
 436                 host->ops->dma_release(host);
 437
 438         host->use_dma = false;
 439 }
 440
 441 static void mmci_dma_setup(struct mmci_host *host)
 442 {
 443         if (!host->ops || !host->ops->dma_setup)
 444                 return;
 445
 446         if (host->ops->dma_setup(host))
 447                 return;
 448
 449         /* initialize pre request cookie */
 450         host->next_cookie = 1;
 451
 452         host->use_dma = true;
 453 }
 454
 455 /*
 456  * Validate mmc prerequisites
 457  */
 458 static int mmci_validate_data(struct mmci_host *host,
 459                               struct mmc_data *data)
 460 {
 461         struct variant_data *variant = host->variant;
 462
 463         if (!data)
 464                 return 0;
 465         if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) {
 466                 dev_err(mmc_dev(host->mmc),
 467                         "unsupported block size (%d bytes)\n", data->blksz);
 468                 return -EINVAL;
 469         }
 470
 471         if (host->ops && host->ops->validate_data)
 472                 return host->ops->validate_data(host, data);
 473
 474         return 0;
 475 }
 476
 477 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
 478 {
 479         int err;
 480
 481         if (!host->ops || !host->ops->prep_data)
 482                 return 0;
 483
 484         err = host->ops->prep_data(host, data, next);
 485
 486         if (next && !err)
 487                 data->host_cookie = ++host->next_cookie < 0 ?
 488                         1 : host->next_cookie;
 489
 490         return err;
 491 }
 492
 493 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
 494                       int err)
 495 {
 496         if (host->ops && host->ops->unprep_data)
 497                 host->ops->unprep_data(host, data, err);
 498
 499         data->host_cookie = 0;
 500 }
 501
 502 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
 503 {
 504         WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
 505
 506         if (host->ops && host->ops->get_next_data)
 507                 host->ops->get_next_data(host, data);
 508 }
 509
 510 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
 511 {
 512         struct mmc_data *data = host->data;
 513         int ret;
 514
 515         if (!host->use_dma)
 516                 return -EINVAL;
 517
 518         ret = mmci_prep_data(host, data, false);
 519         if (ret)
 520                 return ret;
 521
 522         if (!host->ops || !host->ops->dma_start)
 523                 return -EINVAL;
 524
 525         /* Okay, go for it. */
 526         dev_vdbg(mmc_dev(host->mmc),
 527                  "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
 528                  data->sg_len, data->blksz, data->blocks, data->flags);
 529
 530         ret = host->ops->dma_start(host, &datactrl);
 531         if (ret)
 532                 return ret;
 533
 534         /* Trigger the DMA transfer */
 535         mmci_write_datactrlreg(host, datactrl);
 536
 537         /*
 538          * Let the MMCI say when the data is ended and it's time
 539          * to fire next DMA request. When that happens, MMCI will
 540          * call mmci_data_end()
 541          */
 542         writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
 543                host->base + MMCIMASK0);
 544         return 0;
 545 }
 546
 547 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
 548 {
 549         if (!host->use_dma)
 550                 return;
 551
 552         if (host->ops && host->ops->dma_finalize)
 553                 host->ops->dma_finalize(host, data);
 554 }
 555
 556 static void mmci_dma_error(struct mmci_host *host)
 557 {
 558         if (!host->use_dma)
 559                 return;
 560
 561         if (host->ops && host->ops->dma_error)
 562                 host->ops->dma_error(host);
 563 }
 564
 565 static void
 566 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
 567 {
 568         writel(0, host->base + MMCICOMMAND);
 569
 570         BUG_ON(host->data);
 571
 572         host->mrq = NULL;
 573         host->cmd = NULL;
 574
 575         mmc_request_done(host->mmc, mrq);
 576 }
 577
 578 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
 579 {
 580         void __iomem *base = host->base;
 581         struct variant_data *variant = host->variant;
 582
 583         if (host->singleirq) {
 584                 unsigned int mask0 = readl(base + MMCIMASK0);
 585
 586                 mask0 &= ~variant->irq_pio_mask;
 587                 mask0 |= mask;
 588
 589                 writel(mask0, base + MMCIMASK0);
 590         }
 591
 592         if (variant->mmcimask1)
 593                 writel(mask, base + MMCIMASK1);
 594
 595         host->mask1_reg = mask;
 596 }
 597
 598 static void mmci_stop_data(struct mmci_host *host)
 599 {
 600         mmci_write_datactrlreg(host, 0);
 601         mmci_set_mask1(host, 0);
 602         host->data = NULL;
 603 }
 604
 605 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
 606 {
 607         unsigned int flags = SG_MITER_ATOMIC;
 608
 609         if (data->flags & MMC_DATA_READ)
 610                 flags |= SG_MITER_TO_SG;
 611         else
 612                 flags |= SG_MITER_FROM_SG;
 613
 614         sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 615 }
 616
 617 static u32 mmci_get_dctrl_cfg(struct mmci_host *host)
 618 {
 619         return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host);
 620 }
 621
 622 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host)
 623 {
 624         return MCI_DPSM_ENABLE | (host->data->blksz << 16);
 625 }
 626
 627 static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
 628 {
 629         void __iomem *base = host->base;
 630
 631         /*
 632          * Before unmasking for the busy end IRQ, confirm that the
 633          * command was sent successfully. To keep track of having a
 634          * command in-progress, waiting for busy signaling to end,
 635          * store the status in host->busy_status.
 636          *
 637          * Note that, the card may need a couple of clock cycles before
 638          * it starts signaling busy on DAT0, hence re-read the
 639          * MMCISTATUS register here, to allow the busy bit to be set.
 640          * Potentially we may even need to poll the register for a
 641          * while, to allow it to be set, but tests indicates that it
 642          * isn't needed.
 643          */
 644         if (!host->busy_status && !(status & err_msk) &&
 645             (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
 646                 writel(readl(base + MMCIMASK0) |
 647                        host->variant->busy_detect_mask,
 648                        base + MMCIMASK0);
 649
 650                 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND);
 651                 return false;
 652         }
 653
 654         /*
 655          * If there is a command in-progress that has been successfully
 656          * sent, then bail out if busy status is set and wait for the
 657          * busy end IRQ.
 658          *
 659          * Note that, the HW triggers an IRQ on both edges while
 660          * monitoring DAT0 for busy completion, but there is only one
 661          * status bit in MMCISTATUS for the busy state. Therefore
 662          * both the start and the end interrupts needs to be cleared,
 663          * one after the other. So, clear the busy start IRQ here.
 664          */
 665         if (host->busy_status &&
 666             (status & host->variant->busy_detect_flag)) {
 667                 writel(host->variant->busy_detect_mask, base + MMCICLEAR);
 668                 return false;
 669         }
 670
 671         /*
 672          * If there is a command in-progress that has been successfully
 673          * sent and the busy bit isn't set, it means we have received
 674          * the busy end IRQ. Clear and mask the IRQ, then continue to
 675          * process the command.
 676          */
 677         if (host->busy_status) {
 678                 writel(host->variant->busy_detect_mask, base + MMCICLEAR);
 679
 680                 writel(readl(base + MMCIMASK0) &
 681                        ~host->variant->busy_detect_mask, base + MMCIMASK0);
 682                 host->busy_status = 0;
 683         }
 684
 685         return true;
 686 }
 687
 688 /*
 689  * All the DMA operation mode stuff goes inside this ifdef.
 690  * This assumes that you have a generic DMA device interface,
 691  * no custom DMA interfaces are supported.
 692  */
 693 #ifdef CONFIG_DMA_ENGINE
 694 struct mmci_dmae_next {
 695         struct dma_async_tx_descriptor *desc;
 696         struct dma_chan *chan;
 697 };
 698
 699 struct mmci_dmae_priv {
 700         struct dma_chan *cur;
 701         struct dma_chan *rx_channel;
 702         struct dma_chan *tx_channel;
 703         struct dma_async_tx_descriptor  *desc_current;
 704         struct mmci_dmae_next next_data;
 705 };
 706
 707 int mmci_dmae_setup(struct mmci_host *host)
 708 {
 709         const char *rxname, *txname;
 710         struct mmci_dmae_priv *dmae;
 711
 712         dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
 713         if (!dmae)
 714                 return -ENOMEM;
 715
 716         host->dma_priv = dmae;
 717
 718         dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx");
 719         if (IS_ERR(dmae->rx_channel)) {
 720                 int ret = PTR_ERR(dmae->rx_channel);
 721                 dmae->rx_channel = NULL;
 722                 return ret;
 723         }
 724
 725         dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx");
 726         if (IS_ERR(dmae->tx_channel)) {
 727                 if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER)
 728                         dev_warn(mmc_dev(host->mmc),
 729                                  "Deferred probe for TX channel ignored\n");
 730                 dmae->tx_channel = NULL;
 731         }
 732
 733         /*
 734          * If only an RX channel is specified, the driver will
 735          * attempt to use it bidirectionally, however if it is
 736          * is specified but cannot be located, DMA will be disabled.
 737          */
 738         if (dmae->rx_channel && !dmae->tx_channel)
 739                 dmae->tx_channel = dmae->rx_channel;
 740
 741         if (dmae->rx_channel)
 742                 rxname = dma_chan_name(dmae->rx_channel);
 743         else
 744                 rxname = "none";
 745
 746         if (dmae->tx_channel)
 747                 txname = dma_chan_name(dmae->tx_channel);
 748         else
 749                 txname = "none";
 750
 751         dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
 752                  rxname, txname);
 753
 754         /*
 755          * Limit the maximum segment size in any SG entry according to
 756          * the parameters of the DMA engine device.
 757          */
 758         if (dmae->tx_channel) {
 759                 struct device *dev = dmae->tx_channel->device->dev;
 760                 unsigned int max_seg_size = dma_get_max_seg_size(dev);
 761
 762                 if (max_seg_size < host->mmc->max_seg_size)
 763                         host->mmc->max_seg_size = max_seg_size;
 764         }
 765         if (dmae->rx_channel) {
 766                 struct device *dev = dmae->rx_channel->device->dev;
 767                 unsigned int max_seg_size = dma_get_max_seg_size(dev);
 768
 769                 if (max_seg_size < host->mmc->max_seg_size)
 770                         host->mmc->max_seg_size = max_seg_size;
 771         }
 772
 773         if (!dmae->tx_channel || !dmae->rx_channel) {
 774                 mmci_dmae_release(host);
 775                 return -EINVAL;
 776         }
 777
 778         return 0;
 779 }
 780
 781 /*
 782  * This is used in or so inline it
 783  * so it can be discarded.
 784  */
 785 void mmci_dmae_release(struct mmci_host *host)
 786 {
 787         struct mmci_dmae_priv *dmae = host->dma_priv;
 788
 789         if (dmae->rx_channel)
 790                 dma_release_channel(dmae->rx_channel);
 791         if (dmae->tx_channel)
 792                 dma_release_channel(dmae->tx_channel);
 793         dmae->rx_channel = dmae->tx_channel = NULL;
 794 }
 795
 796 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
 797 {
 798         struct mmci_dmae_priv *dmae = host->dma_priv;
 799         struct dma_chan *chan;
 800
 801         if (data->flags & MMC_DATA_READ)
 802                 chan = dmae->rx_channel;
 803         else
 804                 chan = dmae->tx_channel;
 805
 806         dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
 807                      mmc_get_dma_dir(data));
 808 }
 809
 810 void mmci_dmae_error(struct mmci_host *host)
 811 {
 812         struct mmci_dmae_priv *dmae = host->dma_priv;
 813
 814         if (!dma_inprogress(host))
 815                 return;
 816
 817         dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
 818         dmaengine_terminate_all(dmae->cur);
 819         host->dma_in_progress = false;
 820         dmae->cur = NULL;
 821         dmae->desc_current = NULL;
 822         host->data->host_cookie = 0;
 823
 824         mmci_dma_unmap(host, host->data);
 825 }
 826
 827 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
 828 {
 829         struct mmci_dmae_priv *dmae = host->dma_priv;
 830         u32 status;
 831         int i;
 832
 833         if (!dma_inprogress(host))
 834                 return;
 835
 836         /* Wait up to 1ms for the DMA to complete */
 837         for (i = 0; ; i++) {
 838                 status = readl(host->base + MMCISTATUS);
 839                 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
 840                         break;
 841                 udelay(10);
 842         }
 843
 844         /*
 845          * Check to see whether we still have some data left in the FIFO -
 846          * this catches DMA controllers which are unable to monitor the
 847          * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
 848          * contiguous buffers.  On TX, we'll get a FIFO underrun error.
 849          */
 850         if (status & MCI_RXDATAAVLBLMASK) {
 851                 mmci_dma_error(host);
 852                 if (!data->error)
 853                         data->error = -EIO;
 854         } else if (!data->host_cookie) {
 855                 mmci_dma_unmap(host, data);
 856         }
 857
 858         /*
 859          * Use of DMA with scatter-gather is impossible.
 860          * Give up with DMA and switch back to PIO mode.
 861          */
 862         if (status & MCI_RXDATAAVLBLMASK) {
 863                 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
 864                 mmci_dma_release(host);
 865         }
 866
 867         host->dma_in_progress = false;
 868         dmae->cur = NULL;
 869         dmae->desc_current = NULL;
 870 }
 871
 872 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
 873 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
 874                                 struct dma_chan **dma_chan,
 875                                 struct dma_async_tx_descriptor **dma_desc)
 876 {
 877         struct mmci_dmae_priv *dmae = host->dma_priv;
 878         struct variant_data *variant = host->variant;
 879         struct dma_slave_config conf = {
 880                 .src_addr = host->phybase + MMCIFIFO,
 881                 .dst_addr = host->phybase + MMCIFIFO,
 882                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 883                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 884                 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
 885                 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
 886                 .device_fc = false,
 887         };
 888         struct dma_chan *chan;
 889         struct dma_device *device;
 890         struct dma_async_tx_descriptor *desc;
 891         int nr_sg;
 892         unsigned long flags = DMA_CTRL_ACK;
 893
 894         if (data->flags & MMC_DATA_READ) {
 895                 conf.direction = DMA_DEV_TO_MEM;
 896                 chan = dmae->rx_channel;
 897         } else {
 898                 conf.direction = DMA_MEM_TO_DEV;
 899                 chan = dmae->tx_channel;
 900         }
 901
 902         /* If there's no DMA channel, fall back to PIO */
 903         if (!chan)
 904                 return -EINVAL;
 905
 906         /* If less than or equal to the fifo size, don't bother with DMA */
 907         if (data->blksz * data->blocks <= variant->fifosize)
 908                 return -EINVAL;
 909
 910         /*
 911          * This is necessary to get SDIO working on the Ux500. We do not yet
 912          * know if this is a bug in:
 913          * - The Ux500 DMA controller (DMA40)
 914          * - The MMCI DMA interface on the Ux500
 915          * some power of two blocks (such as 64 bytes) are sent regularly
 916          * during SDIO traffic and those work fine so for these we enable DMA
 917          * transfers.
 918          */
 919         if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz))
 920                 return -EINVAL;
 921
 922         device = chan->device;
 923         nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
 924                            mmc_get_dma_dir(data));
 925         if (nr_sg == 0)
 926                 return -EINVAL;
 927
 928         if (host->variant->qcom_dml)
 929                 flags |= DMA_PREP_INTERRUPT;
 930
 931         dmaengine_slave_config(chan, &conf);
 932         desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
 933                                             conf.direction, flags);
 934         if (!desc)
 935                 goto unmap_exit;
 936
 937         *dma_chan = chan;
 938         *dma_desc = desc;
 939
 940         return 0;
 941
 942  unmap_exit:
 943         dma_unmap_sg(device->dev, data->sg, data->sg_len,
 944                      mmc_get_dma_dir(data));
 945         return -ENOMEM;
 946 }
 947
 948 int mmci_dmae_prep_data(struct mmci_host *host,
 949                         struct mmc_data *data,
 950                         bool next)
 951 {
 952         struct mmci_dmae_priv *dmae = host->dma_priv;
 953         struct mmci_dmae_next *nd = &dmae->next_data;
 954
 955         if (!host->use_dma)
 956                 return -EINVAL;
 957
 958         if (next)
 959                 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
 960         /* Check if next job is already prepared. */
 961         if (dmae->cur && dmae->desc_current)
 962                 return 0;
 963
 964         /* No job were prepared thus do it now. */
 965         return _mmci_dmae_prep_data(host, data, &dmae->cur,
 966                                     &dmae->desc_current);
 967 }
 968
 969 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
 970 {
 971         struct mmci_dmae_priv *dmae = host->dma_priv;
 972         int ret;
 973
 974         host->dma_in_progress = true;
 975         ret = dma_submit_error(dmaengine_submit(dmae->desc_current));
 976         if (ret < 0) {
 977                 host->dma_in_progress = false;
 978                 return ret;
 979         }
 980         dma_async_issue_pending(dmae->cur);
 981
 982         *datactrl |= MCI_DPSM_DMAENABLE;
 983
 984         return 0;
 985 }
 986
 987 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
 988 {
 989         struct mmci_dmae_priv *dmae = host->dma_priv;
 990         struct mmci_dmae_next *next = &dmae->next_data;
 991
 992         if (!host->use_dma)
 993                 return;
 994
 995         WARN_ON(!data->host_cookie && (next->desc || next->chan));
 996
 997         dmae->desc_current = next->desc;
 998         dmae->cur = next->chan;
 999         next->desc = NULL;
1000         next->chan = NULL;
1001 }
1002
1003 void mmci_dmae_unprep_data(struct mmci_host *host,
1004                            struct mmc_data *data, int err)
1005
1006 {
1007         struct mmci_dmae_priv *dmae = host->dma_priv;
1008
1009         if (!host->use_dma)
1010                 return;
1011
1012         mmci_dma_unmap(host, data);
1013
1014         if (err) {
1015                 struct mmci_dmae_next *next = &dmae->next_data;
1016                 struct dma_chan *chan;
1017                 if (data->flags & MMC_DATA_READ)
1018                         chan = dmae->rx_channel;
1019                 else
1020                         chan = dmae->tx_channel;
1021                 dmaengine_terminate_all(chan);
1022
1023                 if (dmae->desc_current == next->desc)
1024                         dmae->desc_current = NULL;
1025
1026                 if (dmae->cur == next->chan) {
1027                         host->dma_in_progress = false;
1028                         dmae->cur = NULL;
1029                 }
1030
1031                 next->desc = NULL;
1032                 next->chan = NULL;
1033         }
1034 }
1035
1036 static struct mmci_host_ops mmci_variant_ops = {
1037         .prep_data = mmci_dmae_prep_data,
1038         .unprep_data = mmci_dmae_unprep_data,
1039         .get_datactrl_cfg = mmci_get_dctrl_cfg,
1040         .get_next_data = mmci_dmae_get_next_data,
1041         .dma_setup = mmci_dmae_setup,
1042         .dma_release = mmci_dmae_release,
1043         .dma_start = mmci_dmae_start,
1044         .dma_finalize = mmci_dmae_finalize,
1045         .dma_error = mmci_dmae_error,
1046 };
1047 #else
1048 static struct mmci_host_ops mmci_variant_ops = {
1049         .get_datactrl_cfg = mmci_get_dctrl_cfg,
1050 };
1051 #endif
1052
1053 static void mmci_variant_init(struct mmci_host *host)
1054 {
1055         host->ops = &mmci_variant_ops;
1056 }
1057
1058 static void ux500_variant_init(struct mmci_host *host)
1059 {
1060         host->ops = &mmci_variant_ops;
1061         host->ops->busy_complete = ux500_busy_complete;
1062 }
1063
1064 static void ux500v2_variant_init(struct mmci_host *host)
1065 {
1066         host->ops = &mmci_variant_ops;
1067         host->ops->busy_complete = ux500_busy_complete;
1068         host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;
1069 }
1070
1071 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
1072 {
1073         struct mmci_host *host = mmc_priv(mmc);
1074         struct mmc_data *data = mrq->data;
1075
1076         if (!data)
1077                 return;
1078
1079         WARN_ON(data->host_cookie);
1080
1081         if (mmci_validate_data(host, data))
1082                 return;
1083
1084         mmci_prep_data(host, data, true);
1085 }
1086
1087 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
1088                               int err)
1089 {
1090         struct mmci_host *host = mmc_priv(mmc);
1091         struct mmc_data *data = mrq->data;
1092
1093         if (!data || !data->host_cookie)
1094                 return;
1095
1096         mmci_unprep_data(host, data, err);
1097 }
1098
1099 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
1100 {
1101         struct variant_data *variant = host->variant;
1102         unsigned int datactrl, timeout, irqmask;
1103         unsigned long long clks;
1104         void __iomem *base;
1105
1106         dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
1107                 data->blksz, data->blocks, data->flags);
1108
1109         host->data = data;
1110         host->size = data->blksz * data->blocks;
1111         data->bytes_xfered = 0;
1112
1113         clks = (unsigned long long)data->timeout_ns * host->cclk;
1114         do_div(clks, NSEC_PER_SEC);
1115
1116         timeout = data->timeout_clks + (unsigned int)clks;
1117
1118         base = host->base;
1119         writel(timeout, base + MMCIDATATIMER);
1120         writel(host->size, base + MMCIDATALENGTH);
1121
1122         datactrl = host->ops->get_datactrl_cfg(host);
1123         datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0;
1124
1125         if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
1126                 u32 clk;
1127
1128                 datactrl |= variant->datactrl_mask_sdio;
1129
1130                 /*
1131                  * The ST Micro variant for SDIO small write transfers
1132                  * needs to have clock H/W flow control disabled,
1133                  * otherwise the transfer will not start. The threshold
1134                  * depends on the rate of MCLK.
1135                  */
1136                 if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
1137                     (host->size < 8 ||
1138                      (host->size <= 8 && host->mclk > 50000000)))
1139                         clk = host->clk_reg & ~variant->clkreg_enable;
1140                 else
1141                         clk = host->clk_reg | variant->clkreg_enable;
1142
1143                 mmci_write_clkreg(host, clk);
1144         }
1145
1146         if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
1147             host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
1148                 datactrl |= variant->datactrl_mask_ddrmode;
1149
1150         /*
1151          * Attempt to use DMA operation mode, if this
1152          * should fail, fall back to PIO mode
1153          */
1154         if (!mmci_dma_start(host, datactrl))
1155                 return;
1156
1157         /* IRQ mode, map the SG list for CPU reading/writing */
1158         mmci_init_sg(host, data);
1159
1160         if (data->flags & MMC_DATA_READ) {
1161                 irqmask = MCI_RXFIFOHALFFULLMASK;
1162
1163                 /*
1164                  * If we have less than the fifo 'half-full' threshold to
1165                  * transfer, trigger a PIO interrupt as soon as any data
1166                  * is available.
1167                  */
1168                 if (host->size < variant->fifohalfsize)
1169                         irqmask |= MCI_RXDATAAVLBLMASK;
1170         } else {
1171                 /*
1172                  * We don't actually need to include "FIFO empty" here
1173                  * since its implicit in "FIFO half empty".
1174                  */
1175                 irqmask = MCI_TXFIFOHALFEMPTYMASK;
1176         }
1177
1178         mmci_write_datactrlreg(host, datactrl);
1179         writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
1180         mmci_set_mask1(host, irqmask);
1181 }
1182
1183 static void
1184 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
1185 {
1186         void __iomem *base = host->base;
1187         unsigned long long clks;
1188
1189         dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1190             cmd->opcode, cmd->arg, cmd->flags);
1191
1192         if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
1193                 writel(0, base + MMCICOMMAND);
1194                 mmci_reg_delay(host);
1195         }
1196
1197         if (host->variant->cmdreg_stop &&
1198             cmd->opcode == MMC_STOP_TRANSMISSION)
1199                 c |= host->variant->cmdreg_stop;
1200
1201         c |= cmd->opcode | host->variant->cmdreg_cpsm_enable;
1202         if (cmd->flags & MMC_RSP_PRESENT) {
1203                 if (cmd->flags & MMC_RSP_136)
1204                         c |= host->variant->cmdreg_lrsp_crc;
1205                 else if (cmd->flags & MMC_RSP_CRC)
1206                         c |= host->variant->cmdreg_srsp_crc;
1207                 else
1208                         c |= host->variant->cmdreg_srsp;
1209         }
1210
1211         if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) {
1212                 if (!cmd->busy_timeout)
1213                         cmd->busy_timeout = 10 * MSEC_PER_SEC;
1214
1215                 clks = (unsigned long long)cmd->busy_timeout * host->cclk;
1216                 do_div(clks, MSEC_PER_SEC);
1217                 writel_relaxed(clks, host->base + MMCIDATATIMER);
1218         }
1219
1220         if (/*interrupt*/0)
1221                 c |= MCI_CPSM_INTERRUPT;
1222
1223         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
1224                 c |= host->variant->data_cmd_enable;
1225
1226         host->cmd = cmd;
1227
1228         writel(cmd->arg, base + MMCIARGUMENT);
1229         writel(c, base + MMCICOMMAND);
1230 }
1231
1232 static void mmci_stop_command(struct mmci_host *host)
1233 {
1234         host->stop_abort.error = 0;
1235         mmci_start_command(host, &host->stop_abort, 0);
1236 }
1237
1238 static void
1239 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
1240               unsigned int status)
1241 {
1242         unsigned int status_err;
1243
1244         /* Make sure we have data to handle */
1245         if (!data)
1246                 return;
1247
1248         /* First check for errors */
1249         status_err = status & (host->variant->start_err |
1250                                MCI_DATACRCFAIL | MCI_DATATIMEOUT |
1251                                MCI_TXUNDERRUN | MCI_RXOVERRUN);
1252
1253         if (status_err) {
1254                 u32 remain, success;
1255
1256                 /* Terminate the DMA transfer */
1257                 mmci_dma_error(host);
1258
1259                 /*
1260                  * Calculate how far we are into the transfer.  Note that
1261                  * the data counter gives the number of bytes transferred
1262                  * on the MMC bus, not on the host side.  On reads, this
1263                  * can be as much as a FIFO-worth of data ahead.  This
1264                  * matters for FIFO overruns only.
1265                  */
1266                 if (!host->variant->datacnt_useless) {
1267                         remain = readl(host->base + MMCIDATACNT);
1268                         success = data->blksz * data->blocks - remain;
1269                 } else {
1270                         success = 0;
1271                 }
1272
1273                 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
1274                         status_err, success);
1275                 if (status_err & MCI_DATACRCFAIL) {
1276                         /* Last block was not successful */
1277                         success -= 1;
1278                         data->error = -EILSEQ;
1279                 } else if (status_err & MCI_DATATIMEOUT) {
1280                         data->error = -ETIMEDOUT;
1281                 } else if (status_err & MCI_STARTBITERR) {
1282                         data->error = -ECOMM;
1283                 } else if (status_err & MCI_TXUNDERRUN) {
1284                         data->error = -EIO;
1285                 } else if (status_err & MCI_RXOVERRUN) {
1286                         if (success > host->variant->fifosize)
1287                                 success -= host->variant->fifosize;
1288                         else
1289                                 success = 0;
1290                         data->error = -EIO;
1291                 }
1292                 data->bytes_xfered = round_down(success, data->blksz);
1293         }
1294
1295         if (status & MCI_DATABLOCKEND)
1296                 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
1297
1298         if (status & MCI_DATAEND || data->error) {
1299                 mmci_dma_finalize(host, data);
1300
1301                 mmci_stop_data(host);
1302
1303                 if (!data->error)
1304                         /* The error clause is handled above, success! */
1305                         data->bytes_xfered = data->blksz * data->blocks;
1306
1307                 if (!data->stop) {
1308                         if (host->variant->cmdreg_stop && data->error)
1309                                 mmci_stop_command(host);
1310                         else
1311                                 mmci_request_end(host, data->mrq);
1312                 } else if (host->mrq->sbc && !data->error) {
1313                         mmci_request_end(host, data->mrq);
1314                 } else {
1315                         mmci_start_command(host, data->stop, 0);
1316                 }
1317         }
1318 }
1319
1320 static void
1321 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
1322              unsigned int status)
1323 {
1324         u32 err_msk = MCI_CMDCRCFAIL | MCI_CMDTIMEOUT;
1325         void __iomem *base = host->base;
1326         bool sbc, busy_resp;
1327
1328         if (!cmd)
1329                 return;
1330
1331         sbc = (cmd == host->mrq->sbc);
1332         busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
1333
1334         /*
1335          * We need to be one of these interrupts to be considered worth
1336          * handling. Note that we tag on any latent IRQs postponed
1337          * due to waiting for busy status.
1338          */
1339         if (host->variant->busy_timeout && busy_resp)
1340                 err_msk |= MCI_DATATIMEOUT;
1341
1342         if (!((status | host->busy_status) &
1343               (err_msk | MCI_CMDSENT | MCI_CMDRESPEND)))
1344                 return;
1345
1346         /* Handle busy detection on DAT0 if the variant supports it. */
1347         if (busy_resp && host->variant->busy_detect)
1348                 if (!host->ops->busy_complete(host, status, err_msk))
1349                         return;
1350
1351         host->cmd = NULL;
1352
1353         if (status & MCI_CMDTIMEOUT) {
1354                 cmd->error = -ETIMEDOUT;
1355         } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
1356                 cmd->error = -EILSEQ;
1357         } else if (host->variant->busy_timeout && busy_resp &&
1358                    status & MCI_DATATIMEOUT) {
1359                 cmd->error = -ETIMEDOUT;
1360                 host->irq_action = IRQ_WAKE_THREAD;
1361         } else {
1362                 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1363                 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1364                 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1365                 cmd->resp[3] = readl(base + MMCIRESPONSE3);
1366         }
1367
1368         if ((!sbc && !cmd->data) || cmd->error) {
1369                 if (host->data) {
1370                         /* Terminate the DMA transfer */
1371                         mmci_dma_error(host);
1372
1373                         mmci_stop_data(host);
1374                         if (host->variant->cmdreg_stop && cmd->error) {
1375                                 mmci_stop_command(host);
1376                                 return;
1377                         }
1378                 }
1379
1380                 if (host->irq_action != IRQ_WAKE_THREAD)
1381                         mmci_request_end(host, host->mrq);
1382
1383         } else if (sbc) {
1384                 mmci_start_command(host, host->mrq->cmd, 0);
1385         } else if (!host->variant->datactrl_first &&
1386                    !(cmd->data->flags & MMC_DATA_READ)) {
1387                 mmci_start_data(host, cmd->data);
1388         }
1389 }
1390
1391 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1392 {
1393         return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1394 }
1395
1396 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1397 {
1398         /*
1399          * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1400          * from the fifo range should be used
1401          */
1402         if (status & MCI_RXFIFOHALFFULL)
1403                 return host->variant->fifohalfsize;
1404         else if (status & MCI_RXDATAAVLBL)
1405                 return 4;
1406
1407         return 0;
1408 }
1409
1410 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1411 {
1412         void __iomem *base = host->base;
1413         char *ptr = buffer;
1414         u32 status = readl(host->base + MMCISTATUS);
1415         int host_remain = host->size;
1416
1417         do {
1418                 int count = host->get_rx_fifocnt(host, status, host_remain);
1419
1420                 if (count > remain)
1421                         count = remain;
1422
1423                 if (count <= 0)
1424                         break;
1425
1426                 /*
1427                  * SDIO especially may want to send something that is
1428                  * not divisible by 4 (as opposed to card sectors
1429                  * etc). Therefore make sure to always read the last bytes
1430                  * while only doing full 32-bit reads towards the FIFO.
1431                  */
1432                 if (unlikely(count & 0x3)) {
1433                         if (count < 4) {
1434                                 unsigned char buf[4];
1435                                 ioread32_rep(base + MMCIFIFO, buf, 1);
1436                                 memcpy(ptr, buf, count);
1437                         } else {
1438                                 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1439                                 count &= ~0x3;
1440                         }
1441                 } else {
1442                         ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1443                 }
1444
1445                 ptr += count;
1446                 remain -= count;
1447                 host_remain -= count;
1448
1449                 if (remain == 0)
1450                         break;
1451
1452                 status = readl(base + MMCISTATUS);
1453         } while (status & MCI_RXDATAAVLBL);
1454
1455         return ptr - buffer;
1456 }
1457
1458 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1459 {
1460         struct variant_data *variant = host->variant;
1461         void __iomem *base = host->base;
1462         char *ptr = buffer;
1463
1464         do {
1465                 unsigned int count, maxcnt;
1466
1467                 maxcnt = status & MCI_TXFIFOEMPTY ?
1468                          variant->fifosize : variant->fifohalfsize;
1469                 count = min(remain, maxcnt);
1470
1471                 /*
1472                  * SDIO especially may want to send something that is
1473                  * not divisible by 4 (as opposed to card sectors
1474                  * etc), and the FIFO only accept full 32-bit writes.
1475                  * So compensate by adding +3 on the count, a single
1476                  * byte become a 32bit write, 7 bytes will be two
1477                  * 32bit writes etc.
1478                  */
1479                 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1480
1481                 ptr += count;
1482                 remain -= count;
1483
1484                 if (remain == 0)
1485                         break;
1486
1487                 status = readl(base + MMCISTATUS);
1488         } while (status & MCI_TXFIFOHALFEMPTY);
1489
1490         return ptr - buffer;
1491 }
1492
1493 /*
1494  * PIO data transfer IRQ handler.
1495  */
1496 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1497 {
1498         struct mmci_host *host = dev_id;
1499         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1500         struct variant_data *variant = host->variant;
1501         void __iomem *base = host->base;
1502         u32 status;
1503
1504         status = readl(base + MMCISTATUS);
1505
1506         dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1507
1508         do {
1509                 unsigned int remain, len;
1510                 char *buffer;
1511
1512                 /*
1513                  * For write, we only need to test the half-empty flag
1514                  * here - if the FIFO is completely empty, then by
1515                  * definition it is more than half empty.
1516                  *
1517                  * For read, check for data available.
1518                  */
1519                 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1520                         break;
1521
1522                 if (!sg_miter_next(sg_miter))
1523                         break;
1524
1525                 buffer = sg_miter->addr;
1526                 remain = sg_miter->length;
1527
1528                 len = 0;
1529                 if (status & MCI_RXACTIVE)
1530                         len = mmci_pio_read(host, buffer, remain);
1531                 if (status & MCI_TXACTIVE)
1532                         len = mmci_pio_write(host, buffer, remain, status);
1533
1534                 sg_miter->consumed = len;
1535
1536                 host->size -= len;
1537                 remain -= len;
1538
1539                 if (remain)
1540                         break;
1541
1542                 status = readl(base + MMCISTATUS);
1543         } while (1);
1544
1545         sg_miter_stop(sg_miter);
1546
1547         /*
1548          * If we have less than the fifo 'half-full' threshold to transfer,
1549          * trigger a PIO interrupt as soon as any data is available.
1550          */
1551         if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1552                 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1553
1554         /*
1555          * If we run out of data, disable the data IRQs; this
1556          * prevents a race where the FIFO becomes empty before
1557          * the chip itself has disabled the data path, and
1558          * stops us racing with our data end IRQ.
1559          */
1560         if (host->size == 0) {
1561                 mmci_set_mask1(host, 0);
1562                 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1563         }
1564
1565         return IRQ_HANDLED;
1566 }
1567
1568 /*
1569  * Handle completion of command and data transfers.
1570  */
1571 static irqreturn_t mmci_irq(int irq, void *dev_id)
1572 {
1573         struct mmci_host *host = dev_id;
1574         u32 status;
1575
1576         spin_lock(&host->lock);
1577         host->irq_action = IRQ_HANDLED;
1578
1579         do {
1580                 status = readl(host->base + MMCISTATUS);
1581
1582                 if (host->singleirq) {
1583                         if (status & host->mask1_reg)
1584                                 mmci_pio_irq(irq, dev_id);
1585
1586                         status &= ~host->variant->irq_pio_mask;
1587                 }
1588
1589                 /*
1590                  * Busy detection is managed by mmci_cmd_irq(), including to
1591                  * clear the corresponding IRQ.
1592                  */
1593                 status &= readl(host->base + MMCIMASK0);
1594                 if (host->variant->busy_detect)
1595                         writel(status & ~host->variant->busy_detect_mask,
1596                                host->base + MMCICLEAR);
1597                 else
1598                         writel(status, host->base + MMCICLEAR);
1599
1600                 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1601
1602                 if (host->variant->reversed_irq_handling) {
1603                         mmci_data_irq(host, host->data, status);
1604                         mmci_cmd_irq(host, host->cmd, status);
1605                 } else {
1606                         mmci_cmd_irq(host, host->cmd, status);
1607                         mmci_data_irq(host, host->data, status);
1608                 }
1609
1610                 /*
1611                  * Busy detection has been handled by mmci_cmd_irq() above.
1612                  * Clear the status bit to prevent polling in IRQ context.
1613                  */
1614                 if (host->variant->busy_detect_flag)
1615                         status &= ~host->variant->busy_detect_flag;
1616
1617         } while (status);
1618
1619         spin_unlock(&host->lock);
1620
1621         return host->irq_action;
1622 }
1623
1624 /*
1625  * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW.
1626  *
1627  * A reset is needed for some variants, where a datatimeout for a R1B request
1628  * causes the DPSM to stay busy (non-functional).
1629  */
1630 static irqreturn_t mmci_irq_thread(int irq, void *dev_id)
1631 {
1632         struct mmci_host *host = dev_id;
1633         unsigned long flags;
1634
1635         if (host->rst) {
1636                 reset_control_assert(host->rst);
1637                 udelay(2);
1638                 reset_control_deassert(host->rst);
1639         }
1640
1641         spin_lock_irqsave(&host->lock, flags);
1642         writel(host->clk_reg, host->base + MMCICLOCK);
1643         writel(host->pwr_reg, host->base + MMCIPOWER);
1644         writel(MCI_IRQENABLE | host->variant->start_err,
1645                host->base + MMCIMASK0);
1646
1647         host->irq_action = IRQ_HANDLED;
1648         mmci_request_end(host, host->mrq);
1649         spin_unlock_irqrestore(&host->lock, flags);
1650
1651         return host->irq_action;
1652 }
1653
1654 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1655 {
1656         struct mmci_host *host = mmc_priv(mmc);
1657         unsigned long flags;
1658
1659         WARN_ON(host->mrq != NULL);
1660
1661         mrq->cmd->error = mmci_validate_data(host, mrq->data);
1662         if (mrq->cmd->error) {
1663                 mmc_request_done(mmc, mrq);
1664                 return;
1665         }
1666
1667         spin_lock_irqsave(&host->lock, flags);
1668
1669         host->mrq = mrq;
1670
1671         if (mrq->data)
1672                 mmci_get_next_data(host, mrq->data);
1673
1674         if (mrq->data &&
1675             (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ))
1676                 mmci_start_data(host, mrq->data);
1677
1678         if (mrq->sbc)
1679                 mmci_start_command(host, mrq->sbc, 0);
1680         else
1681                 mmci_start_command(host, mrq->cmd, 0);
1682
1683         spin_unlock_irqrestore(&host->lock, flags);
1684 }
1685
1686 static void mmci_set_max_busy_timeout(struct mmc_host *mmc)
1687 {
1688         struct mmci_host *host = mmc_priv(mmc);
1689         u32 max_busy_timeout = 0;
1690
1691         if (!host->variant->busy_detect)
1692                 return;
1693
1694         if (host->variant->busy_timeout && mmc->actual_clock)
1695                 max_busy_timeout = ~0UL / (mmc->actual_clock / MSEC_PER_SEC);
1696
1697         mmc->max_busy_timeout = max_busy_timeout;
1698 }
1699
1700 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1701 {
1702         struct mmci_host *host = mmc_priv(mmc);
1703         struct variant_data *variant = host->variant;
1704         u32 pwr = 0;
1705         unsigned long flags;
1706         int ret;
1707
1708         if (host->plat->ios_handler &&
1709                 host->plat->ios_handler(mmc_dev(mmc), ios))
1710                         dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1711
1712         switch (ios->power_mode) {
1713         case MMC_POWER_OFF:
1714                 if (!IS_ERR(mmc->supply.vmmc))
1715                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1716
1717                 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1718                         regulator_disable(mmc->supply.vqmmc);
1719                         host->vqmmc_enabled = false;
1720                 }
1721
1722                 break;
1723         case MMC_POWER_UP:
1724                 if (!IS_ERR(mmc->supply.vmmc))
1725                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1726
1727                 /*
1728                  * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1729                  * and instead uses MCI_PWR_ON so apply whatever value is
1730                  * configured in the variant data.
1731                  */
1732                 pwr |= variant->pwrreg_powerup;
1733
1734                 break;
1735         case MMC_POWER_ON:
1736                 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1737                         ret = regulator_enable(mmc->supply.vqmmc);
1738                         if (ret < 0)
1739                                 dev_err(mmc_dev(mmc),
1740                                         "failed to enable vqmmc regulator\n");
1741                         else
1742                                 host->vqmmc_enabled = true;
1743                 }
1744
1745                 pwr |= MCI_PWR_ON;
1746                 break;
1747         }
1748
1749         if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1750                 /*
1751                  * The ST Micro variant has some additional bits
1752                  * indicating signal direction for the signals in
1753                  * the SD/MMC bus and feedback-clock usage.
1754                  */
1755                 pwr |= host->pwr_reg_add;
1756
1757                 if (ios->bus_width == MMC_BUS_WIDTH_4)
1758                         pwr &= ~MCI_ST_DATA74DIREN;
1759                 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1760                         pwr &= (~MCI_ST_DATA74DIREN &
1761                                 ~MCI_ST_DATA31DIREN &
1762                                 ~MCI_ST_DATA2DIREN);
1763         }
1764
1765         if (variant->opendrain) {
1766                 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1767                         pwr |= variant->opendrain;
1768         } else {
1769                 /*
1770                  * If the variant cannot configure the pads by its own, then we
1771                  * expect the pinctrl to be able to do that for us
1772                  */
1773                 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1774                         pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1775                 else
1776                         pinctrl_select_default_state(mmc_dev(mmc));
1777         }
1778
1779         /*
1780          * If clock = 0 and the variant requires the MMCIPOWER to be used for
1781          * gating the clock, the MCI_PWR_ON bit is cleared.
1782          */
1783         if (!ios->clock && variant->pwrreg_clkgate)
1784                 pwr &= ~MCI_PWR_ON;
1785
1786         if (host->variant->explicit_mclk_control &&
1787             ios->clock != host->clock_cache) {
1788                 ret = clk_set_rate(host->clk, ios->clock);
1789                 if (ret < 0)
1790                         dev_err(mmc_dev(host->mmc),
1791                                 "Error setting clock rate (%d)\n", ret);
1792                 else
1793                         host->mclk = clk_get_rate(host->clk);
1794         }
1795         host->clock_cache = ios->clock;
1796
1797         spin_lock_irqsave(&host->lock, flags);
1798
1799         if (host->ops && host->ops->set_clkreg)
1800                 host->ops->set_clkreg(host, ios->clock);
1801         else
1802                 mmci_set_clkreg(host, ios->clock);
1803
1804         mmci_set_max_busy_timeout(mmc);
1805
1806         if (host->ops && host->ops->set_pwrreg)
1807                 host->ops->set_pwrreg(host, pwr);
1808         else
1809                 mmci_write_pwrreg(host, pwr);
1810
1811         mmci_reg_delay(host);
1812
1813         spin_unlock_irqrestore(&host->lock, flags);
1814 }
1815
1816 static int mmci_get_cd(struct mmc_host *mmc)
1817 {
1818         struct mmci_host *host = mmc_priv(mmc);
1819         struct mmci_platform_data *plat = host->plat;
1820         unsigned int status = mmc_gpio_get_cd(mmc);
1821
1822         if (status == -ENOSYS) {
1823                 if (!plat->status)
1824                         return 1; /* Assume always present */
1825
1826                 status = plat->status(mmc_dev(host->mmc));
1827         }
1828         return status;
1829 }
1830
1831 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1832 {
1833         int ret = 0;
1834
1835         if (!IS_ERR(mmc->supply.vqmmc)) {
1836
1837                 switch (ios->signal_voltage) {
1838                 case MMC_SIGNAL_VOLTAGE_330:
1839                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1840                                                 2700000, 3600000);
1841                         break;
1842                 case MMC_SIGNAL_VOLTAGE_180:
1843                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1844                                                 1700000, 1950000);
1845                         break;
1846                 case MMC_SIGNAL_VOLTAGE_120:
1847                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1848                                                 1100000, 1300000);
1849                         break;
1850                 }
1851
1852                 if (ret)
1853                         dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1854         }
1855
1856         return ret;
1857 }
1858
1859 static struct mmc_host_ops mmci_ops = {
1860         .request        = mmci_request,
1861         .pre_req        = mmci_pre_request,
1862         .post_req       = mmci_post_request,
1863         .set_ios        = mmci_set_ios,
1864         .get_ro         = mmc_gpio_get_ro,
1865         .get_cd         = mmci_get_cd,
1866         .start_signal_voltage_switch = mmci_sig_volt_switch,
1867 };
1868
1869 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1870 {
1871         struct mmci_host *host = mmc_priv(mmc);
1872         int ret = mmc_of_parse(mmc);
1873
1874         if (ret)
1875                 return ret;
1876
1877         if (of_get_property(np, "st,sig-dir-dat0", NULL))
1878                 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1879         if (of_get_property(np, "st,sig-dir-dat2", NULL))
1880                 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1881         if (of_get_property(np, "st,sig-dir-dat31", NULL))
1882                 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1883         if (of_get_property(np, "st,sig-dir-dat74", NULL))
1884                 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1885         if (of_get_property(np, "st,sig-dir-cmd", NULL))
1886                 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1887         if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1888                 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1889         if (of_get_property(np, "st,sig-dir", NULL))
1890                 host->pwr_reg_add |= MCI_STM32_DIRPOL;
1891         if (of_get_property(np, "st,neg-edge", NULL))
1892                 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
1893         if (of_get_property(np, "st,use-ckin", NULL))
1894                 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
1895
1896         if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1897                 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1898         if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1899                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1900
1901         return 0;
1902 }
1903
1904 static int mmci_probe(struct amba_device *dev,
1905         const struct amba_id *id)
1906 {
1907         struct mmci_platform_data *plat = dev->dev.platform_data;
1908         struct device_node *np = dev->dev.of_node;
1909         struct variant_data *variant = id->data;
1910         struct mmci_host *host;
1911         struct mmc_host *mmc;
1912         int ret;
1913
1914         /* Must have platform data or Device Tree. */
1915         if (!plat && !np) {
1916                 dev_err(&dev->dev, "No plat data or DT found\n");
1917                 return -EINVAL;
1918         }
1919
1920         if (!plat) {
1921                 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1922                 if (!plat)
1923                         return -ENOMEM;
1924         }
1925
1926         mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1927         if (!mmc)
1928                 return -ENOMEM;
1929
1930         ret = mmci_of_parse(np, mmc);
1931         if (ret)
1932                 goto host_free;
1933
1934         host = mmc_priv(mmc);
1935         host->mmc = mmc;
1936
1937         /*
1938          * Some variant (STM32) doesn't have opendrain bit, nevertheless
1939          * pins can be set accordingly using pinctrl
1940          */
1941         if (!variant->opendrain) {
1942                 host->pinctrl = devm_pinctrl_get(&dev->dev);
1943                 if (IS_ERR(host->pinctrl)) {
1944                         dev_err(&dev->dev, "failed to get pinctrl");
1945                         ret = PTR_ERR(host->pinctrl);
1946                         goto host_free;
1947                 }
1948
1949                 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
1950                                                             MMCI_PINCTRL_STATE_OPENDRAIN);
1951                 if (IS_ERR(host->pins_opendrain)) {
1952                         dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
1953                         ret = PTR_ERR(host->pins_opendrain);
1954                         goto host_free;
1955                 }
1956         }
1957
1958         host->hw_designer = amba_manf(dev);
1959         host->hw_revision = amba_rev(dev);
1960         dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1961         dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1962
1963         host->clk = devm_clk_get(&dev->dev, NULL);
1964         if (IS_ERR(host->clk)) {
1965                 ret = PTR_ERR(host->clk);
1966                 goto host_free;
1967         }
1968
1969         ret = clk_prepare_enable(host->clk);
1970         if (ret)
1971                 goto host_free;
1972
1973         if (variant->qcom_fifo)
1974                 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1975         else
1976                 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1977
1978         host->plat = plat;
1979         host->variant = variant;
1980         host->mclk = clk_get_rate(host->clk);
1981         /*
1982          * According to the spec, mclk is max 100 MHz,
1983          * so we try to adjust the clock down to this,
1984          * (if possible).
1985          */
1986         if (host->mclk > variant->f_max) {
1987                 ret = clk_set_rate(host->clk, variant->f_max);
1988                 if (ret < 0)
1989                         goto clk_disable;
1990                 host->mclk = clk_get_rate(host->clk);
1991                 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1992                         host->mclk);
1993         }
1994
1995         host->phybase = dev->res.start;
1996         host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1997         if (IS_ERR(host->base)) {
1998                 ret = PTR_ERR(host->base);
1999                 goto clk_disable;
2000         }
2001
2002         if (variant->init)
2003                 variant->init(host);
2004
2005         /*
2006          * The ARM and ST versions of the block have slightly different
2007          * clock divider equations which means that the minimum divider
2008          * differs too.
2009          * on Qualcomm like controllers get the nearest minimum clock to 100Khz
2010          */
2011         if (variant->st_clkdiv)
2012                 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
2013         else if (variant->stm32_clkdiv)
2014                 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
2015         else if (variant->explicit_mclk_control)
2016                 mmc->f_min = clk_round_rate(host->clk, 100000);
2017         else
2018                 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
2019         /*
2020          * If no maximum operating frequency is supplied, fall back to use
2021          * the module parameter, which has a (low) default value in case it
2022          * is not specified. Either value must not exceed the clock rate into
2023          * the block, of course.
2024          */
2025         if (mmc->f_max)
2026                 mmc->f_max = variant->explicit_mclk_control ?
2027                                 min(variant->f_max, mmc->f_max) :
2028                                 min(host->mclk, mmc->f_max);
2029         else
2030                 mmc->f_max = variant->explicit_mclk_control ?
2031                                 fmax : min(host->mclk, fmax);
2032
2033
2034         dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
2035
2036         host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
2037         if (IS_ERR(host->rst)) {
2038                 ret = PTR_ERR(host->rst);
2039                 goto clk_disable;
2040         }
2041
2042         /* Get regulators and the supported OCR mask */
2043         ret = mmc_regulator_get_supply(mmc);
2044         if (ret)
2045                 goto clk_disable;
2046
2047         if (!mmc->ocr_avail)
2048                 mmc->ocr_avail = plat->ocr_mask;
2049         else if (plat->ocr_mask)
2050                 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
2051
2052         /* We support these capabilities. */
2053         mmc->caps |= MMC_CAP_CMD23;
2054
2055         /*
2056          * Enable busy detection.
2057          */
2058         if (variant->busy_detect) {
2059                 mmci_ops.card_busy = mmci_card_busy;
2060                 /*
2061                  * Not all variants have a flag to enable busy detection
2062                  * in the DPSM, but if they do, set it here.
2063                  */
2064                 if (variant->busy_dpsm_flag)
2065                         mmci_write_datactrlreg(host,
2066                                                host->variant->busy_dpsm_flag);
2067                 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
2068         }
2069
2070         /* Prepare a CMD12 - needed to clear the DPSM on some variants. */
2071         host->stop_abort.opcode = MMC_STOP_TRANSMISSION;
2072         host->stop_abort.arg = 0;
2073         host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC;
2074
2075         mmc->ops = &mmci_ops;
2076
2077         /* We support these PM capabilities. */
2078         mmc->pm_caps |= MMC_PM_KEEP_POWER;
2079
2080         /*
2081          * We can do SGIO
2082          */
2083         mmc->max_segs = NR_SG;
2084
2085         /*
2086          * Since only a certain number of bits are valid in the data length
2087          * register, we must ensure that we don't exceed 2^num-1 bytes in a
2088          * single request.
2089          */
2090         mmc->max_req_size = (1 << variant->datalength_bits) - 1;
2091
2092         /*
2093          * Set the maximum segment size.  Since we aren't doing DMA
2094          * (yet) we are only limited by the data length register.
2095          */
2096         mmc->max_seg_size = mmc->max_req_size;
2097
2098         /*
2099          * Block size can be up to 2048 bytes, but must be a power of two.
2100          */
2101         mmc->max_blk_size = 1 << variant->datactrl_blocksz;
2102
2103         /*
2104          * Limit the number of blocks transferred so that we don't overflow
2105          * the maximum request size.
2106          */
2107         mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz;
2108
2109         spin_lock_init(&host->lock);
2110
2111         writel(0, host->base + MMCIMASK0);
2112
2113         if (variant->mmcimask1)
2114                 writel(0, host->base + MMCIMASK1);
2115
2116         writel(0xfff, host->base + MMCICLEAR);
2117
2118         /*
2119          * If:
2120          * - not using DT but using a descriptor table, or
2121          * - using a table of descriptors ALONGSIDE DT, or
2122          * look up these descriptors named "cd" and "wp" right here, fail
2123          * silently of these do not exist
2124          */
2125         if (!np) {
2126                 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
2127                 if (ret == -EPROBE_DEFER)
2128                         goto clk_disable;
2129
2130                 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0);
2131                 if (ret == -EPROBE_DEFER)
2132                         goto clk_disable;
2133         }
2134
2135         ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq,
2136                                         mmci_irq_thread, IRQF_SHARED,
2137                                         DRIVER_NAME " (cmd)", host);
2138         if (ret)
2139                 goto clk_disable;
2140
2141         if (!dev->irq[1])
2142                 host->singleirq = true;
2143         else {
2144                 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
2145                                 IRQF_SHARED, DRIVER_NAME " (pio)", host);
2146                 if (ret)
2147                         goto clk_disable;
2148         }
2149
2150         writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
2151
2152         amba_set_drvdata(dev, mmc);
2153
2154         dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
2155                  mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
2156                  amba_rev(dev), (unsigned long long)dev->res.start,
2157                  dev->irq[0], dev->irq[1]);
2158
2159         mmci_dma_setup(host);
2160
2161         pm_runtime_set_autosuspend_delay(&dev->dev, 50);
2162         pm_runtime_use_autosuspend(&dev->dev);
2163
2164         mmc_add_host(mmc);
2165
2166         pm_runtime_put(&dev->dev);
2167         return 0;
2168
2169  clk_disable:
2170         clk_disable_unprepare(host->clk);
2171  host_free:
2172         mmc_free_host(mmc);
2173         return ret;
2174 }
2175
2176 static int mmci_remove(struct amba_device *dev)
2177 {
2178         struct mmc_host *mmc = amba_get_drvdata(dev);
2179
2180         if (mmc) {
2181                 struct mmci_host *host = mmc_priv(mmc);
2182                 struct variant_data *variant = host->variant;
2183
2184                 /*
2185                  * Undo pm_runtime_put() in probe.  We use the _sync
2186                  * version here so that we can access the primecell.
2187                  */
2188                 pm_runtime_get_sync(&dev->dev);
2189
2190                 mmc_remove_host(mmc);
2191
2192                 writel(0, host->base + MMCIMASK0);
2193
2194                 if (variant->mmcimask1)
2195                         writel(0, host->base + MMCIMASK1);
2196
2197                 writel(0, host->base + MMCICOMMAND);
2198                 writel(0, host->base + MMCIDATACTRL);
2199
2200                 mmci_dma_release(host);
2201                 clk_disable_unprepare(host->clk);
2202                 mmc_free_host(mmc);
2203         }
2204
2205         return 0;
2206 }
2207
2208 #ifdef CONFIG_PM
2209 static void mmci_save(struct mmci_host *host)
2210 {
2211         unsigned long flags;
2212
2213         spin_lock_irqsave(&host->lock, flags);
2214
2215         writel(0, host->base + MMCIMASK0);
2216         if (host->variant->pwrreg_nopower) {
2217                 writel(0, host->base + MMCIDATACTRL);
2218                 writel(0, host->base + MMCIPOWER);
2219                 writel(0, host->base + MMCICLOCK);
2220         }
2221         mmci_reg_delay(host);
2222
2223         spin_unlock_irqrestore(&host->lock, flags);
2224 }
2225
2226 static void mmci_restore(struct mmci_host *host)
2227 {
2228         unsigned long flags;
2229
2230         spin_lock_irqsave(&host->lock, flags);
2231
2232         if (host->variant->pwrreg_nopower) {
2233                 writel(host->clk_reg, host->base + MMCICLOCK);
2234                 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
2235                 writel(host->pwr_reg, host->base + MMCIPOWER);
2236         }
2237         writel(MCI_IRQENABLE | host->variant->start_err,
2238                host->base + MMCIMASK0);
2239         mmci_reg_delay(host);
2240
2241         spin_unlock_irqrestore(&host->lock, flags);
2242 }
2243
2244 static int mmci_runtime_suspend(struct device *dev)
2245 {
2246         struct amba_device *adev = to_amba_device(dev);
2247         struct mmc_host *mmc = amba_get_drvdata(adev);
2248
2249         if (mmc) {
2250                 struct mmci_host *host = mmc_priv(mmc);
2251                 pinctrl_pm_select_sleep_state(dev);
2252                 mmci_save(host);
2253                 clk_disable_unprepare(host->clk);
2254         }
2255
2256         return 0;
2257 }
2258
2259 static int mmci_runtime_resume(struct device *dev)
2260 {
2261         struct amba_device *adev = to_amba_device(dev);
2262         struct mmc_host *mmc = amba_get_drvdata(adev);
2263
2264         if (mmc) {
2265                 struct mmci_host *host = mmc_priv(mmc);
2266                 clk_prepare_enable(host->clk);
2267                 mmci_restore(host);
2268                 pinctrl_select_default_state(dev);
2269         }
2270
2271         return 0;
2272 }
2273 #endif
2274
2275 static const struct dev_pm_ops mmci_dev_pm_ops = {
2276         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2277                                 pm_runtime_force_resume)
2278         SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
2279 };
2280
2281 static const struct amba_id mmci_ids[] = {
2282         {
2283                 .id     = 0x00041180,
2284                 .mask   = 0xff0fffff,
2285                 .data   = &variant_arm,
2286         },
2287         {
2288                 .id     = 0x01041180,
2289                 .mask   = 0xff0fffff,
2290                 .data   = &variant_arm_extended_fifo,
2291         },
2292         {
2293                 .id     = 0x02041180,
2294                 .mask   = 0xff0fffff,
2295                 .data   = &variant_arm_extended_fifo_hwfc,
2296         },
2297         {
2298                 .id     = 0x00041181,
2299                 .mask   = 0x000fffff,
2300                 .data   = &variant_arm,
2301         },
2302         /* ST Micro variants */
2303         {
2304                 .id     = 0x00180180,
2305                 .mask   = 0x00ffffff,
2306                 .data   = &variant_u300,
2307         },
2308         {
2309                 .id     = 0x10180180,
2310                 .mask   = 0xf0ffffff,
2311                 .data   = &variant_nomadik,
2312         },
2313         {
2314                 .id     = 0x00280180,
2315                 .mask   = 0x00ffffff,
2316                 .data   = &variant_nomadik,
2317         },
2318         {
2319                 .id     = 0x00480180,
2320                 .mask   = 0xf0ffffff,
2321                 .data   = &variant_ux500,
2322         },
2323         {
2324                 .id     = 0x10480180,
2325                 .mask   = 0xf0ffffff,
2326                 .data   = &variant_ux500v2,
2327         },
2328         {
2329                 .id     = 0x00880180,
2330                 .mask   = 0x00ffffff,
2331                 .data   = &variant_stm32,
2332         },
2333         {
2334                 .id     = 0x10153180,
2335                 .mask   = 0xf0ffffff,
2336                 .data   = &variant_stm32_sdmmc,
2337         },
2338         /* Qualcomm variants */
2339         {
2340                 .id     = 0x00051180,
2341                 .mask   = 0x000fffff,
2342                 .data   = &variant_qcom,
2343         },
2344         { 0, 0 },
2345 };
2346
2347 MODULE_DEVICE_TABLE(amba, mmci_ids);
2348
2349 static struct amba_driver mmci_driver = {
2350         .drv            = {
2351                 .name   = DRIVER_NAME,
2352                 .pm     = &mmci_dev_pm_ops,
2353         },
2354         .probe          = mmci_probe,
2355         .remove         = mmci_remove,
2356         .id_table       = mmci_ids,
2357 };
2358
2359 module_amba_driver(mmci_driver);
2360
2361 module_param(fmax, uint, 0444);
2362
2363 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
2364 MODULE_LICENSE("GPL");