2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE | SDMMC_INT_HLE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
59 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
64 #define DESC_RING_BUF_SZ PAGE_SIZE
66 struct idmac_desc_64addr {
67 u32 des0; /* Control Descriptor */
69 u32 des1; /* Reserved */
71 u32 des2; /*Buffer sizes */
72 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
73 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
74 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
76 u32 des3; /* Reserved */
78 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
79 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
81 u32 des6; /* Lower 32-bits of Next Descriptor Address */
82 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86 __le32 des0; /* Control Descriptor */
87 #define IDMAC_DES0_DIC BIT(1)
88 #define IDMAC_DES0_LD BIT(2)
89 #define IDMAC_DES0_FD BIT(3)
90 #define IDMAC_DES0_CH BIT(4)
91 #define IDMAC_DES0_ER BIT(5)
92 #define IDMAC_DES0_CES BIT(30)
93 #define IDMAC_DES0_OWN BIT(31)
95 __le32 des1; /* Buffer sizes */
96 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
97 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
99 __le32 des2; /* buffer 1 physical address */
101 __le32 des3; /* buffer 2 physical address */
104 /* Each descriptor can transfer up to 4KB of data in chained mode */
105 #define DW_MCI_DESC_DATA_LENGTH 0x1000
107 static bool dw_mci_reset(struct dw_mci *host);
108 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
109 static int dw_mci_card_busy(struct mmc_host *mmc);
110 static int dw_mci_get_cd(struct mmc_host *mmc);
112 #if defined(CONFIG_DEBUG_FS)
113 static int dw_mci_req_show(struct seq_file *s, void *v)
115 struct dw_mci_slot *slot = s->private;
116 struct mmc_request *mrq;
117 struct mmc_command *cmd;
118 struct mmc_command *stop;
119 struct mmc_data *data;
121 /* Make sure we get a consistent snapshot */
122 spin_lock_bh(&slot->host->lock);
132 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
133 cmd->opcode, cmd->arg, cmd->flags,
134 cmd->resp[0], cmd->resp[1], cmd->resp[2],
135 cmd->resp[2], cmd->error);
137 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
138 data->bytes_xfered, data->blocks,
139 data->blksz, data->flags, data->error);
142 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
143 stop->opcode, stop->arg, stop->flags,
144 stop->resp[0], stop->resp[1], stop->resp[2],
145 stop->resp[2], stop->error);
148 spin_unlock_bh(&slot->host->lock);
153 static int dw_mci_req_open(struct inode *inode, struct file *file)
155 return single_open(file, dw_mci_req_show, inode->i_private);
158 static const struct file_operations dw_mci_req_fops = {
159 .owner = THIS_MODULE,
160 .open = dw_mci_req_open,
163 .release = single_release,
166 static int dw_mci_regs_show(struct seq_file *s, void *v)
168 struct dw_mci *host = s->private;
170 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
171 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
172 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
173 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
174 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
175 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
180 static int dw_mci_regs_open(struct inode *inode, struct file *file)
182 return single_open(file, dw_mci_regs_show, inode->i_private);
185 static const struct file_operations dw_mci_regs_fops = {
186 .owner = THIS_MODULE,
187 .open = dw_mci_regs_open,
190 .release = single_release,
193 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
195 struct mmc_host *mmc = slot->mmc;
196 struct dw_mci *host = slot->host;
200 root = mmc->debugfs_root;
204 node = debugfs_create_file("regs", S_IRUSR, root, host,
209 node = debugfs_create_file("req", S_IRUSR, root, slot,
214 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
218 node = debugfs_create_x32("pending_events", S_IRUSR, root,
219 (u32 *)&host->pending_events);
223 node = debugfs_create_x32("completed_events", S_IRUSR, root,
224 (u32 *)&host->completed_events);
231 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
233 #endif /* defined(CONFIG_DEBUG_FS) */
235 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
237 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
239 struct dw_mci_slot *slot = mmc_priv(mmc);
240 struct dw_mci *host = slot->host;
243 cmd->error = -EINPROGRESS;
246 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
247 cmd->opcode == MMC_GO_IDLE_STATE ||
248 cmd->opcode == MMC_GO_INACTIVE_STATE ||
249 (cmd->opcode == SD_IO_RW_DIRECT &&
250 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
251 cmdr |= SDMMC_CMD_STOP;
252 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
253 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
255 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
258 /* Special bit makes CMD11 not die */
259 cmdr |= SDMMC_CMD_VOLT_SWITCH;
261 /* Change state to continue to handle CMD11 weirdness */
262 WARN_ON(slot->host->state != STATE_SENDING_CMD);
263 slot->host->state = STATE_SENDING_CMD11;
266 * We need to disable low power mode (automatic clock stop)
267 * while doing voltage switch so we don't confuse the card,
268 * since stopping the clock is a specific part of the UHS
269 * voltage change dance.
271 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
272 * unconditionally turned back on in dw_mci_setup_bus() if it's
273 * ever called with a non-zero clock. That shouldn't happen
274 * until the voltage change is all done.
276 clk_en_a = mci_readl(host, CLKENA);
277 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
278 mci_writel(host, CLKENA, clk_en_a);
279 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
280 SDMMC_CMD_PRV_DAT_WAIT, 0);
283 if (cmd->flags & MMC_RSP_PRESENT) {
284 /* We expect a response, so set this bit */
285 cmdr |= SDMMC_CMD_RESP_EXP;
286 if (cmd->flags & MMC_RSP_136)
287 cmdr |= SDMMC_CMD_RESP_LONG;
290 if (cmd->flags & MMC_RSP_CRC)
291 cmdr |= SDMMC_CMD_RESP_CRC;
294 cmdr |= SDMMC_CMD_DAT_EXP;
295 if (cmd->data->flags & MMC_DATA_WRITE)
296 cmdr |= SDMMC_CMD_DAT_WR;
299 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
300 cmdr |= SDMMC_CMD_USE_HOLD_REG;
305 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
307 struct mmc_command *stop;
313 stop = &host->stop_abort;
315 memset(stop, 0, sizeof(struct mmc_command));
317 if (cmdr == MMC_READ_SINGLE_BLOCK ||
318 cmdr == MMC_READ_MULTIPLE_BLOCK ||
319 cmdr == MMC_WRITE_BLOCK ||
320 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
321 cmdr == MMC_SEND_TUNING_BLOCK ||
322 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
323 stop->opcode = MMC_STOP_TRANSMISSION;
325 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
326 } else if (cmdr == SD_IO_RW_EXTENDED) {
327 stop->opcode = SD_IO_RW_DIRECT;
328 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
329 ((cmd->arg >> 28) & 0x7);
330 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
335 cmdr = stop->opcode | SDMMC_CMD_STOP |
336 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
338 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags))
339 cmdr |= SDMMC_CMD_USE_HOLD_REG;
344 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
346 unsigned long timeout = jiffies + msecs_to_jiffies(500);
349 * Databook says that before issuing a new data transfer command
350 * we need to check to see if the card is busy. Data transfer commands
351 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
353 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
356 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
357 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
358 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
359 if (time_after(jiffies, timeout)) {
360 /* Command will fail; we'll pass error then */
361 dev_err(host->dev, "Busy; trying anyway\n");
369 static void dw_mci_start_command(struct dw_mci *host,
370 struct mmc_command *cmd, u32 cmd_flags)
374 "start command: ARGR=0x%08x CMDR=0x%08x\n",
375 cmd->arg, cmd_flags);
377 mci_writel(host, CMDARG, cmd->arg);
378 wmb(); /* drain writebuffer */
379 dw_mci_wait_while_busy(host, cmd_flags);
381 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
384 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
386 struct mmc_command *stop = &host->stop_abort;
388 dw_mci_start_command(host, stop, host->stop_cmdr);
391 /* DMA interface functions */
392 static void dw_mci_stop_dma(struct dw_mci *host)
394 if (host->using_dma) {
395 host->dma_ops->stop(host);
396 host->dma_ops->cleanup(host);
399 /* Data transfer was stopped by the interrupt handler */
400 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
403 static int dw_mci_get_dma_dir(struct mmc_data *data)
405 if (data->flags & MMC_DATA_WRITE)
406 return DMA_TO_DEVICE;
408 return DMA_FROM_DEVICE;
411 static void dw_mci_dma_cleanup(struct dw_mci *host)
413 struct mmc_data *data = host->data;
415 if (data && data->host_cookie == COOKIE_MAPPED) {
416 dma_unmap_sg(host->dev,
419 dw_mci_get_dma_dir(data));
420 data->host_cookie = COOKIE_UNMAPPED;
424 static void dw_mci_idmac_reset(struct dw_mci *host)
426 u32 bmod = mci_readl(host, BMOD);
427 /* Software reset of DMA */
428 bmod |= SDMMC_IDMAC_SWRESET;
429 mci_writel(host, BMOD, bmod);
432 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
436 /* Disable and reset the IDMAC interface */
437 temp = mci_readl(host, CTRL);
438 temp &= ~SDMMC_CTRL_USE_IDMAC;
439 temp |= SDMMC_CTRL_DMA_RESET;
440 mci_writel(host, CTRL, temp);
442 /* Stop the IDMAC running */
443 temp = mci_readl(host, BMOD);
444 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
445 temp |= SDMMC_IDMAC_SWRESET;
446 mci_writel(host, BMOD, temp);
449 static void dw_mci_dmac_complete_dma(void *arg)
451 struct dw_mci *host = arg;
452 struct mmc_data *data = host->data;
454 dev_vdbg(host->dev, "DMA complete\n");
456 if ((host->use_dma == TRANS_MODE_EDMAC) &&
457 data && (data->flags & MMC_DATA_READ))
458 /* Invalidate cache after read */
459 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
464 host->dma_ops->cleanup(host);
467 * If the card was removed, data will be NULL. No point in trying to
468 * send the stop command or waiting for NBUSY in this case.
471 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
472 tasklet_schedule(&host->tasklet);
476 static int dw_mci_idmac_init(struct dw_mci *host)
480 if (host->dma_64bit_address == 1) {
481 struct idmac_desc_64addr *p;
482 /* Number of descriptors in the ring buffer */
484 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
486 /* Forward link the descriptor list */
487 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
489 p->des6 = (host->sg_dma +
490 (sizeof(struct idmac_desc_64addr) *
491 (i + 1))) & 0xffffffff;
493 p->des7 = (u64)(host->sg_dma +
494 (sizeof(struct idmac_desc_64addr) *
496 /* Initialize reserved and buffer size fields to "0" */
502 /* Set the last descriptor as the end-of-ring descriptor */
503 p->des6 = host->sg_dma & 0xffffffff;
504 p->des7 = (u64)host->sg_dma >> 32;
505 p->des0 = IDMAC_DES0_ER;
508 struct idmac_desc *p;
509 /* Number of descriptors in the ring buffer */
511 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
513 /* Forward link the descriptor list */
514 for (i = 0, p = host->sg_cpu;
515 i < host->ring_size - 1;
517 p->des3 = cpu_to_le32(host->sg_dma +
518 (sizeof(struct idmac_desc) * (i + 1)));
522 /* Set the last descriptor as the end-of-ring descriptor */
523 p->des3 = cpu_to_le32(host->sg_dma);
524 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
527 dw_mci_idmac_reset(host);
529 if (host->dma_64bit_address == 1) {
530 /* Mask out interrupts - get Tx & Rx complete only */
531 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
532 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
533 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
535 /* Set the descriptor base address */
536 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
537 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
540 /* Mask out interrupts - get Tx & Rx complete only */
541 mci_writel(host, IDSTS, IDMAC_INT_CLR);
542 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
543 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
545 /* Set the descriptor base address */
546 mci_writel(host, DBADDR, host->sg_dma);
552 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
553 struct mmc_data *data,
556 unsigned int desc_len;
557 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
558 unsigned long timeout;
561 desc_first = desc_last = desc = host->sg_cpu;
563 for (i = 0; i < sg_len; i++) {
564 unsigned int length = sg_dma_len(&data->sg[i]);
566 u64 mem_addr = sg_dma_address(&data->sg[i]);
568 for ( ; length ; desc++) {
569 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
570 length : DW_MCI_DESC_DATA_LENGTH;
575 * Wait for the former clear OWN bit operation
576 * of IDMAC to make sure that this descriptor
577 * isn't still owned by IDMAC as IDMAC's write
578 * ops and CPU's read ops are asynchronous.
580 timeout = jiffies + msecs_to_jiffies(100);
581 while (readl(&desc->des0) & IDMAC_DES0_OWN) {
582 if (time_after(jiffies, timeout))
588 * Set the OWN bit and disable interrupts
589 * for this descriptor
591 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
595 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
597 /* Physical address to DMA to/from */
598 desc->des4 = mem_addr & 0xffffffff;
599 desc->des5 = mem_addr >> 32;
601 /* Update physical address for the next desc */
602 mem_addr += desc_len;
604 /* Save pointer to the last descriptor */
609 /* Set first descriptor */
610 desc_first->des0 |= IDMAC_DES0_FD;
612 /* Set last descriptor */
613 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
614 desc_last->des0 |= IDMAC_DES0_LD;
618 /* restore the descriptor chain as it's polluted */
619 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
620 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
621 dw_mci_idmac_init(host);
626 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
627 struct mmc_data *data,
630 unsigned int desc_len;
631 struct idmac_desc *desc_first, *desc_last, *desc;
632 unsigned long timeout;
635 desc_first = desc_last = desc = host->sg_cpu;
637 for (i = 0; i < sg_len; i++) {
638 unsigned int length = sg_dma_len(&data->sg[i]);
640 u32 mem_addr = sg_dma_address(&data->sg[i]);
642 for ( ; length ; desc++) {
643 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
644 length : DW_MCI_DESC_DATA_LENGTH;
649 * Wait for the former clear OWN bit operation
650 * of IDMAC to make sure that this descriptor
651 * isn't still owned by IDMAC as IDMAC's write
652 * ops and CPU's read ops are asynchronous.
654 timeout = jiffies + msecs_to_jiffies(100);
655 while (readl(&desc->des0) &
656 cpu_to_le32(IDMAC_DES0_OWN)) {
657 if (time_after(jiffies, timeout))
663 * Set the OWN bit and disable interrupts
664 * for this descriptor
666 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
671 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
673 /* Physical address to DMA to/from */
674 desc->des2 = cpu_to_le32(mem_addr);
676 /* Update physical address for the next desc */
677 mem_addr += desc_len;
679 /* Save pointer to the last descriptor */
684 /* Set first descriptor */
685 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
687 /* Set last descriptor */
688 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
690 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
694 /* restore the descriptor chain as it's polluted */
695 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
696 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
697 dw_mci_idmac_init(host);
701 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
706 if (host->dma_64bit_address == 1)
707 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
709 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
714 /* drain writebuffer */
717 /* Make sure to reset DMA in case we did PIO before this */
718 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
719 dw_mci_idmac_reset(host);
721 /* Select IDMAC interface */
722 temp = mci_readl(host, CTRL);
723 temp |= SDMMC_CTRL_USE_IDMAC;
724 mci_writel(host, CTRL, temp);
726 /* drain writebuffer */
729 /* Enable the IDMAC */
730 temp = mci_readl(host, BMOD);
731 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
732 mci_writel(host, BMOD, temp);
734 /* Start it running */
735 mci_writel(host, PLDMND, 1);
741 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
742 .init = dw_mci_idmac_init,
743 .start = dw_mci_idmac_start_dma,
744 .stop = dw_mci_idmac_stop_dma,
745 .complete = dw_mci_dmac_complete_dma,
746 .cleanup = dw_mci_dma_cleanup,
749 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
751 dmaengine_terminate_async(host->dms->ch);
754 static int dw_mci_edmac_start_dma(struct dw_mci *host,
757 struct dma_slave_config cfg;
758 struct dma_async_tx_descriptor *desc = NULL;
759 struct scatterlist *sgl = host->data->sg;
760 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
761 u32 sg_elems = host->data->sg_len;
763 u32 fifo_offset = host->fifo_reg - host->regs;
766 /* Set external dma config: burst size, burst width */
767 cfg.dst_addr = host->phy_regs + fifo_offset;
768 cfg.src_addr = cfg.dst_addr;
769 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
770 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
772 /* Match burst msize with external dma config */
773 fifoth_val = mci_readl(host, FIFOTH);
774 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
775 cfg.src_maxburst = cfg.dst_maxburst;
777 if (host->data->flags & MMC_DATA_WRITE)
778 cfg.direction = DMA_MEM_TO_DEV;
780 cfg.direction = DMA_DEV_TO_MEM;
782 ret = dmaengine_slave_config(host->dms->ch, &cfg);
784 dev_err(host->dev, "Failed to config edmac.\n");
788 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
789 sg_len, cfg.direction,
790 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
792 dev_err(host->dev, "Can't prepare slave sg.\n");
796 /* Set dw_mci_dmac_complete_dma as callback */
797 desc->callback = dw_mci_dmac_complete_dma;
798 desc->callback_param = (void *)host;
799 dmaengine_submit(desc);
801 /* Flush cache before write */
802 if (host->data->flags & MMC_DATA_WRITE)
803 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
804 sg_elems, DMA_TO_DEVICE);
806 dma_async_issue_pending(host->dms->ch);
811 static int dw_mci_edmac_init(struct dw_mci *host)
813 /* Request external dma channel */
814 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
818 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
819 if (!host->dms->ch) {
820 dev_err(host->dev, "Failed to get external DMA channel.\n");
829 static void dw_mci_edmac_exit(struct dw_mci *host)
833 dma_release_channel(host->dms->ch);
834 host->dms->ch = NULL;
841 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
842 .init = dw_mci_edmac_init,
843 .exit = dw_mci_edmac_exit,
844 .start = dw_mci_edmac_start_dma,
845 .stop = dw_mci_edmac_stop_dma,
846 .complete = dw_mci_dmac_complete_dma,
847 .cleanup = dw_mci_dma_cleanup,
850 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
851 struct mmc_data *data,
854 struct scatterlist *sg;
855 unsigned int i, sg_len;
857 if (data->host_cookie == COOKIE_PRE_MAPPED)
861 * We don't do DMA on "complex" transfers, i.e. with
862 * non-word-aligned buffers or lengths. Also, we don't bother
863 * with all the DMA setup overhead for short transfers.
865 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
871 for_each_sg(data->sg, sg, data->sg_len, i) {
872 if (sg->offset & 3 || sg->length & 3)
876 sg_len = dma_map_sg(host->dev,
879 dw_mci_get_dma_dir(data));
883 data->host_cookie = cookie;
888 static void dw_mci_pre_req(struct mmc_host *mmc,
889 struct mmc_request *mrq,
892 struct dw_mci_slot *slot = mmc_priv(mmc);
893 struct mmc_data *data = mrq->data;
895 if (!slot->host->use_dma || !data)
898 /* This data might be unmapped at this time */
899 data->host_cookie = COOKIE_UNMAPPED;
901 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
902 COOKIE_PRE_MAPPED) < 0)
903 data->host_cookie = COOKIE_UNMAPPED;
906 static void dw_mci_post_req(struct mmc_host *mmc,
907 struct mmc_request *mrq,
910 struct dw_mci_slot *slot = mmc_priv(mmc);
911 struct mmc_data *data = mrq->data;
913 if (!slot->host->use_dma || !data)
916 if (data->host_cookie != COOKIE_UNMAPPED)
917 dma_unmap_sg(slot->host->dev,
920 dw_mci_get_dma_dir(data));
921 data->host_cookie = COOKIE_UNMAPPED;
924 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
926 unsigned int blksz = data->blksz;
927 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
928 u32 fifo_width = 1 << host->data_shift;
929 u32 blksz_depth = blksz / fifo_width, fifoth_val;
930 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
931 int idx = ARRAY_SIZE(mszs) - 1;
933 /* pio should ship this scenario */
937 tx_wmark = (host->fifo_depth) / 2;
938 tx_wmark_invers = host->fifo_depth - tx_wmark;
942 * if blksz is not a multiple of the FIFO width
944 if (blksz % fifo_width)
948 if (!((blksz_depth % mszs[idx]) ||
949 (tx_wmark_invers % mszs[idx]))) {
951 rx_wmark = mszs[idx] - 1;
956 * If idx is '0', it won't be tried
957 * Thus, initial values are uesed
960 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
961 mci_writel(host, FIFOTH, fifoth_val);
964 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
966 unsigned int blksz = data->blksz;
967 u32 blksz_depth, fifo_depth;
972 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
973 * in the FIFO region, so we really shouldn't access it).
975 if (host->verid < DW_MMC_240A ||
976 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
980 * Card write Threshold is introduced since 2.80a
981 * It's used when HS400 mode is enabled.
983 if (data->flags & MMC_DATA_WRITE &&
984 !(host->timing != MMC_TIMING_MMC_HS400))
987 if (data->flags & MMC_DATA_WRITE)
988 enable = SDMMC_CARD_WR_THR_EN;
990 enable = SDMMC_CARD_RD_THR_EN;
992 if (host->timing != MMC_TIMING_MMC_HS200 &&
993 host->timing != MMC_TIMING_UHS_SDR104)
996 blksz_depth = blksz / (1 << host->data_shift);
997 fifo_depth = host->fifo_depth;
999 if (blksz_depth > fifo_depth)
1003 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1004 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1005 * Currently just choose blksz.
1008 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1012 mci_writel(host, CDTHRCTL, 0);
1015 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1017 unsigned long irqflags;
1021 host->using_dma = 0;
1023 /* If we don't have a channel, we can't do DMA */
1027 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1029 host->dma_ops->stop(host);
1033 host->using_dma = 1;
1035 if (host->use_dma == TRANS_MODE_IDMAC)
1037 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1038 (unsigned long)host->sg_cpu,
1039 (unsigned long)host->sg_dma,
1043 * Decide the MSIZE and RX/TX Watermark.
1044 * If current block size is same with previous size,
1045 * no need to update fifoth.
1047 if (host->prev_blksz != data->blksz)
1048 dw_mci_adjust_fifoth(host, data);
1050 /* Enable the DMA interface */
1051 temp = mci_readl(host, CTRL);
1052 temp |= SDMMC_CTRL_DMA_ENABLE;
1053 mci_writel(host, CTRL, temp);
1055 /* Disable RX/TX IRQs, let DMA handle it */
1056 spin_lock_irqsave(&host->irq_lock, irqflags);
1057 temp = mci_readl(host, INTMASK);
1058 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1059 mci_writel(host, INTMASK, temp);
1060 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1062 if (host->dma_ops->start(host, sg_len)) {
1063 host->dma_ops->stop(host);
1064 /* We can't do DMA, try PIO for this one */
1066 "%s: fall back to PIO mode for current transfer\n",
1074 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1076 unsigned long irqflags;
1077 int flags = SG_MITER_ATOMIC;
1080 data->error = -EINPROGRESS;
1082 WARN_ON(host->data);
1086 if (data->flags & MMC_DATA_READ)
1087 host->dir_status = DW_MCI_RECV_STATUS;
1089 host->dir_status = DW_MCI_SEND_STATUS;
1091 dw_mci_ctrl_thld(host, data);
1093 if (dw_mci_submit_data_dma(host, data)) {
1094 if (host->data->flags & MMC_DATA_READ)
1095 flags |= SG_MITER_TO_SG;
1097 flags |= SG_MITER_FROM_SG;
1099 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1100 host->sg = data->sg;
1101 host->part_buf_start = 0;
1102 host->part_buf_count = 0;
1104 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1106 spin_lock_irqsave(&host->irq_lock, irqflags);
1107 temp = mci_readl(host, INTMASK);
1108 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1109 mci_writel(host, INTMASK, temp);
1110 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1112 temp = mci_readl(host, CTRL);
1113 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1114 mci_writel(host, CTRL, temp);
1117 * Use the initial fifoth_val for PIO mode.
1118 * If next issued data may be transfered by DMA mode,
1119 * prev_blksz should be invalidated.
1121 mci_writel(host, FIFOTH, host->fifoth_val);
1122 host->prev_blksz = 0;
1125 * Keep the current block size.
1126 * It will be used to decide whether to update
1127 * fifoth register next time.
1129 host->prev_blksz = data->blksz;
1133 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1135 struct dw_mci *host = slot->host;
1136 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1137 unsigned int cmd_status = 0;
1139 mci_writel(host, CMDARG, arg);
1140 wmb(); /* drain writebuffer */
1141 dw_mci_wait_while_busy(host, cmd);
1142 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1144 while (time_before(jiffies, timeout)) {
1145 cmd_status = mci_readl(host, CMD);
1146 if (!(cmd_status & SDMMC_CMD_START))
1149 dev_err(&slot->mmc->class_dev,
1150 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1151 cmd, arg, cmd_status);
1154 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1156 struct dw_mci *host = slot->host;
1157 unsigned int clock = slot->clock;
1160 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1162 /* We must continue to set bit 28 in CMD until the change is complete */
1163 if (host->state == STATE_WAITING_CMD11_DONE)
1164 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1167 mci_writel(host, CLKENA, 0);
1168 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1169 } else if (clock != host->current_speed || force_clkinit) {
1170 div = host->bus_hz / clock;
1171 if (host->bus_hz % clock && host->bus_hz > clock)
1173 * move the + 1 after the divide to prevent
1174 * over-clocking the card.
1178 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1180 if (clock != slot->__clk_old || force_clkinit)
1181 dev_info(&slot->mmc->class_dev,
1182 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1183 slot->id, host->bus_hz, clock,
1184 div ? ((host->bus_hz / div) >> 1) :
1188 mci_writel(host, CLKENA, 0);
1189 mci_writel(host, CLKSRC, 0);
1192 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1194 /* set clock to desired speed */
1195 mci_writel(host, CLKDIV, div);
1198 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1200 /* enable clock; only low power if no SDIO */
1201 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1202 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1203 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1204 mci_writel(host, CLKENA, clk_en_a);
1207 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1209 /* keep the last clock value that was requested from core */
1210 slot->__clk_old = clock;
1213 host->current_speed = clock;
1215 /* Set the current slot bus width */
1216 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1219 static void __dw_mci_start_request(struct dw_mci *host,
1220 struct dw_mci_slot *slot,
1221 struct mmc_command *cmd)
1223 struct mmc_request *mrq;
1224 struct mmc_data *data;
1229 host->cur_slot = slot;
1232 host->pending_events = 0;
1233 host->completed_events = 0;
1234 host->cmd_status = 0;
1235 host->data_status = 0;
1236 host->dir_status = 0;
1240 mci_writel(host, TMOUT, 0xFFFFFFFF);
1241 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1242 mci_writel(host, BLKSIZ, data->blksz);
1245 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1247 /* this is the first command, send the initialization clock */
1248 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1249 cmdflags |= SDMMC_CMD_INIT;
1252 dw_mci_submit_data(host, data);
1253 wmb(); /* drain writebuffer */
1256 dw_mci_start_command(host, cmd, cmdflags);
1258 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1259 unsigned long irqflags;
1262 * Databook says to fail after 2ms w/ no response, but evidence
1263 * shows that sometimes the cmd11 interrupt takes over 130ms.
1264 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1265 * is just about to roll over.
1267 * We do this whole thing under spinlock and only if the
1268 * command hasn't already completed (indicating the the irq
1269 * already ran so we don't want the timeout).
1271 spin_lock_irqsave(&host->irq_lock, irqflags);
1272 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1273 mod_timer(&host->cmd11_timer,
1274 jiffies + msecs_to_jiffies(500) + 1);
1275 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1278 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1281 static void dw_mci_start_request(struct dw_mci *host,
1282 struct dw_mci_slot *slot)
1284 struct mmc_request *mrq = slot->mrq;
1285 struct mmc_command *cmd;
1287 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1288 __dw_mci_start_request(host, slot, cmd);
1291 /* must be called with host->lock held */
1292 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1293 struct mmc_request *mrq)
1295 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1300 if (host->state == STATE_WAITING_CMD11_DONE) {
1301 dev_warn(&slot->mmc->class_dev,
1302 "Voltage change didn't complete\n");
1304 * this case isn't expected to happen, so we can
1305 * either crash here or just try to continue on
1306 * in the closest possible state
1308 host->state = STATE_IDLE;
1311 if (host->state == STATE_IDLE) {
1312 host->state = STATE_SENDING_CMD;
1313 dw_mci_start_request(host, slot);
1315 list_add_tail(&slot->queue_node, &host->queue);
1319 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1321 struct dw_mci_slot *slot = mmc_priv(mmc);
1322 struct dw_mci *host = slot->host;
1327 * The check for card presence and queueing of the request must be
1328 * atomic, otherwise the card could be removed in between and the
1329 * request wouldn't fail until another card was inserted.
1332 if (!dw_mci_get_cd(mmc)) {
1333 mrq->cmd->error = -ENOMEDIUM;
1334 mmc_request_done(mmc, mrq);
1338 spin_lock_bh(&host->lock);
1340 dw_mci_queue_request(host, slot, mrq);
1342 spin_unlock_bh(&host->lock);
1345 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1347 struct dw_mci_slot *slot = mmc_priv(mmc);
1348 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1352 switch (ios->bus_width) {
1353 case MMC_BUS_WIDTH_4:
1354 slot->ctype = SDMMC_CTYPE_4BIT;
1356 case MMC_BUS_WIDTH_8:
1357 slot->ctype = SDMMC_CTYPE_8BIT;
1360 /* set default 1 bit mode */
1361 slot->ctype = SDMMC_CTYPE_1BIT;
1364 regs = mci_readl(slot->host, UHS_REG);
1367 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1368 ios->timing == MMC_TIMING_UHS_DDR50 ||
1369 ios->timing == MMC_TIMING_MMC_HS400)
1370 regs |= ((0x1 << slot->id) << 16);
1372 regs &= ~((0x1 << slot->id) << 16);
1374 mci_writel(slot->host, UHS_REG, regs);
1375 slot->host->timing = ios->timing;
1378 * Use mirror of ios->clock to prevent race with mmc
1379 * core ios update when finding the minimum.
1381 slot->clock = ios->clock;
1383 if (drv_data && drv_data->set_ios)
1384 drv_data->set_ios(slot->host, ios);
1386 switch (ios->power_mode) {
1388 if (!IS_ERR(mmc->supply.vmmc)) {
1389 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1392 dev_err(slot->host->dev,
1393 "failed to enable vmmc regulator\n");
1394 /*return, if failed turn on vmmc*/
1398 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1399 regs = mci_readl(slot->host, PWREN);
1400 regs |= (1 << slot->id);
1401 mci_writel(slot->host, PWREN, regs);
1404 if (!slot->host->vqmmc_enabled) {
1405 if (!IS_ERR(mmc->supply.vqmmc)) {
1406 ret = regulator_enable(mmc->supply.vqmmc);
1408 dev_err(slot->host->dev,
1409 "failed to enable vqmmc\n");
1411 slot->host->vqmmc_enabled = true;
1414 /* Keep track so we don't reset again */
1415 slot->host->vqmmc_enabled = true;
1418 /* Reset our state machine after powering on */
1419 dw_mci_ctrl_reset(slot->host,
1420 SDMMC_CTRL_ALL_RESET_FLAGS);
1423 /* Adjust clock / bus width after power is up */
1424 dw_mci_setup_bus(slot, false);
1428 /* Turn clock off before power goes down */
1429 dw_mci_setup_bus(slot, false);
1431 if (!IS_ERR(mmc->supply.vmmc))
1432 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1434 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1435 regulator_disable(mmc->supply.vqmmc);
1436 slot->host->vqmmc_enabled = false;
1438 regs = mci_readl(slot->host, PWREN);
1439 regs &= ~(1 << slot->id);
1440 mci_writel(slot->host, PWREN, regs);
1446 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1447 slot->host->state = STATE_IDLE;
1450 static int dw_mci_card_busy(struct mmc_host *mmc)
1452 struct dw_mci_slot *slot = mmc_priv(mmc);
1456 * Check the busy bit which is low when DAT[3:0]
1457 * (the data lines) are 0000
1459 status = mci_readl(slot->host, STATUS);
1461 return !!(status & SDMMC_STATUS_BUSY);
1464 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1466 struct dw_mci_slot *slot = mmc_priv(mmc);
1467 struct dw_mci *host = slot->host;
1468 const struct dw_mci_drv_data *drv_data = host->drv_data;
1470 u32 v18 = SDMMC_UHS_18V << slot->id;
1473 if (drv_data && drv_data->switch_voltage)
1474 return drv_data->switch_voltage(mmc, ios);
1477 * Program the voltage. Note that some instances of dw_mmc may use
1478 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1479 * does no harm but you need to set the regulator directly. Try both.
1481 uhs = mci_readl(host, UHS_REG);
1482 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1487 if (!IS_ERR(mmc->supply.vqmmc)) {
1488 ret = mmc_regulator_set_vqmmc(mmc, ios);
1491 dev_dbg(&mmc->class_dev,
1492 "Regulator set error %d - %s V\n",
1493 ret, uhs & v18 ? "1.8" : "3.3");
1497 mci_writel(host, UHS_REG, uhs);
1502 static int dw_mci_get_ro(struct mmc_host *mmc)
1505 struct dw_mci_slot *slot = mmc_priv(mmc);
1506 int gpio_ro = mmc_gpio_get_ro(mmc);
1508 /* Use platform get_ro function, else try on board write protect */
1510 read_only = gpio_ro;
1513 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1515 dev_dbg(&mmc->class_dev, "card is %s\n",
1516 read_only ? "read-only" : "read-write");
1521 static int dw_mci_get_cd(struct mmc_host *mmc)
1524 struct dw_mci_slot *slot = mmc_priv(mmc);
1525 struct dw_mci *host = slot->host;
1526 int gpio_cd = mmc_gpio_get_cd(mmc);
1528 /* Use platform get_cd function, else try onboard card detect */
1529 if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
1531 else if (gpio_cd >= 0)
1534 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1537 spin_lock_bh(&host->lock);
1538 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1539 dev_dbg(&mmc->class_dev, "card is present\n");
1540 else if (!test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1541 dev_dbg(&mmc->class_dev, "card is not present\n");
1542 spin_unlock_bh(&host->lock);
1547 static void dw_mci_hw_reset(struct mmc_host *mmc)
1549 struct dw_mci_slot *slot = mmc_priv(mmc);
1550 struct dw_mci *host = slot->host;
1553 if (host->use_dma == TRANS_MODE_IDMAC)
1554 dw_mci_idmac_reset(host);
1556 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1557 SDMMC_CTRL_FIFO_RESET))
1561 * According to eMMC spec, card reset procedure:
1562 * tRstW >= 1us: RST_n pulse width
1563 * tRSCA >= 200us: RST_n to Command time
1564 * tRSTH >= 1us: RST_n high period
1566 reset = mci_readl(host, RST_N);
1567 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1568 mci_writel(host, RST_N, reset);
1570 reset |= SDMMC_RST_HWACTIVE << slot->id;
1571 mci_writel(host, RST_N, reset);
1572 usleep_range(200, 300);
1575 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1577 struct dw_mci_slot *slot = mmc_priv(mmc);
1578 struct dw_mci *host = slot->host;
1581 * Low power mode will stop the card clock when idle. According to the
1582 * description of the CLKENA register we should disable low power mode
1583 * for SDIO cards if we need SDIO interrupts to work.
1585 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1586 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1590 clk_en_a_old = mci_readl(host, CLKENA);
1592 if (card->type == MMC_TYPE_SDIO ||
1593 card->type == MMC_TYPE_SD_COMBO) {
1594 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1595 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1597 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1598 clk_en_a = clk_en_a_old | clken_low_pwr;
1601 if (clk_en_a != clk_en_a_old) {
1602 mci_writel(host, CLKENA, clk_en_a);
1603 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1604 SDMMC_CMD_PRV_DAT_WAIT, 0);
1609 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1611 struct dw_mci_slot *slot = mmc_priv(mmc);
1612 struct dw_mci *host = slot->host;
1613 unsigned long irqflags;
1616 spin_lock_irqsave(&host->irq_lock, irqflags);
1618 /* Enable/disable Slot Specific SDIO interrupt */
1619 int_mask = mci_readl(host, INTMASK);
1621 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1623 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1624 mci_writel(host, INTMASK, int_mask);
1626 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1629 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1631 struct dw_mci_slot *slot = mmc_priv(mmc);
1632 struct dw_mci *host = slot->host;
1633 const struct dw_mci_drv_data *drv_data = host->drv_data;
1636 if (drv_data && drv_data->execute_tuning)
1637 err = drv_data->execute_tuning(slot, opcode);
1641 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1642 struct mmc_ios *ios)
1644 struct dw_mci_slot *slot = mmc_priv(mmc);
1645 struct dw_mci *host = slot->host;
1646 const struct dw_mci_drv_data *drv_data = host->drv_data;
1648 if (drv_data && drv_data->prepare_hs400_tuning)
1649 return drv_data->prepare_hs400_tuning(host, ios);
1654 static const struct mmc_host_ops dw_mci_ops = {
1655 .request = dw_mci_request,
1656 .pre_req = dw_mci_pre_req,
1657 .post_req = dw_mci_post_req,
1658 .set_ios = dw_mci_set_ios,
1659 .get_ro = dw_mci_get_ro,
1660 .get_cd = dw_mci_get_cd,
1661 .hw_reset = dw_mci_hw_reset,
1662 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1663 .execute_tuning = dw_mci_execute_tuning,
1664 .card_busy = dw_mci_card_busy,
1665 .start_signal_voltage_switch = dw_mci_switch_voltage,
1666 .init_card = dw_mci_init_card,
1667 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1670 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1671 __releases(&host->lock)
1672 __acquires(&host->lock)
1674 struct dw_mci_slot *slot;
1675 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1677 WARN_ON(host->cmd || host->data);
1679 host->cur_slot->mrq = NULL;
1681 if (!list_empty(&host->queue)) {
1682 slot = list_entry(host->queue.next,
1683 struct dw_mci_slot, queue_node);
1684 list_del(&slot->queue_node);
1685 dev_vdbg(host->dev, "list not empty: %s is next\n",
1686 mmc_hostname(slot->mmc));
1687 host->state = STATE_SENDING_CMD;
1688 dw_mci_start_request(host, slot);
1690 dev_vdbg(host->dev, "list empty\n");
1692 if (host->state == STATE_SENDING_CMD11)
1693 host->state = STATE_WAITING_CMD11_DONE;
1695 host->state = STATE_IDLE;
1698 spin_unlock(&host->lock);
1699 mmc_request_done(prev_mmc, mrq);
1700 spin_lock(&host->lock);
1703 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1705 u32 status = host->cmd_status;
1707 host->cmd_status = 0;
1709 /* Read the response from the card (up to 16 bytes) */
1710 if (cmd->flags & MMC_RSP_PRESENT) {
1711 if (cmd->flags & MMC_RSP_136) {
1712 cmd->resp[3] = mci_readl(host, RESP0);
1713 cmd->resp[2] = mci_readl(host, RESP1);
1714 cmd->resp[1] = mci_readl(host, RESP2);
1715 cmd->resp[0] = mci_readl(host, RESP3);
1717 cmd->resp[0] = mci_readl(host, RESP0);
1724 if (status & SDMMC_INT_RTO)
1725 cmd->error = -ETIMEDOUT;
1726 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1727 cmd->error = -EILSEQ;
1728 else if (status & SDMMC_INT_RESP_ERR)
1736 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1738 u32 status = host->data_status;
1740 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1741 if (status & SDMMC_INT_DRTO) {
1742 data->error = -ETIMEDOUT;
1743 } else if (status & SDMMC_INT_DCRC) {
1744 data->error = -EILSEQ;
1745 } else if (status & SDMMC_INT_EBE) {
1746 if (host->dir_status ==
1747 DW_MCI_SEND_STATUS) {
1749 * No data CRC status was returned.
1750 * The number of bytes transferred
1751 * will be exaggerated in PIO mode.
1753 data->bytes_xfered = 0;
1754 data->error = -ETIMEDOUT;
1755 } else if (host->dir_status ==
1756 DW_MCI_RECV_STATUS) {
1757 data->error = -EILSEQ;
1760 /* SDMMC_INT_SBE is included */
1761 data->error = -EILSEQ;
1764 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1767 * After an error, there may be data lingering
1772 data->bytes_xfered = data->blocks * data->blksz;
1779 static void dw_mci_set_drto(struct dw_mci *host)
1781 unsigned int drto_clks;
1782 unsigned int drto_ms;
1784 drto_clks = mci_readl(host, TMOUT) >> 8;
1785 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1787 /* add a bit spare time */
1790 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1793 static void dw_mci_tasklet_func(unsigned long priv)
1795 struct dw_mci *host = (struct dw_mci *)priv;
1796 struct mmc_data *data;
1797 struct mmc_command *cmd;
1798 struct mmc_request *mrq;
1799 enum dw_mci_state state;
1800 enum dw_mci_state prev_state;
1803 spin_lock(&host->lock);
1805 state = host->state;
1814 case STATE_WAITING_CMD11_DONE:
1817 case STATE_SENDING_CMD11:
1818 case STATE_SENDING_CMD:
1819 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1820 &host->pending_events))
1825 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1826 err = dw_mci_command_complete(host, cmd);
1827 if (cmd == mrq->sbc && !err) {
1828 prev_state = state = STATE_SENDING_CMD;
1829 __dw_mci_start_request(host, host->cur_slot,
1834 if (cmd->data && err) {
1836 * During UHS tuning sequence, sending the stop
1837 * command after the response CRC error would
1838 * throw the system into a confused state
1839 * causing all future tuning phases to report
1842 * In such case controller will move into a data
1843 * transfer state after a response error or
1844 * response CRC error. Let's let that finish
1845 * before trying to send a stop, so we'll go to
1846 * STATE_SENDING_DATA.
1848 * Although letting the data transfer take place
1849 * will waste a bit of time (we already know
1850 * the command was bad), it can't cause any
1851 * errors since it's possible it would have
1852 * taken place anyway if this tasklet got
1853 * delayed. Allowing the transfer to take place
1854 * avoids races and keeps things simple.
1856 if ((err != -ETIMEDOUT) &&
1857 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1858 state = STATE_SENDING_DATA;
1862 dw_mci_stop_dma(host);
1863 send_stop_abort(host, data);
1864 state = STATE_SENDING_STOP;
1868 if (!cmd->data || err) {
1869 dw_mci_request_end(host, mrq);
1873 prev_state = state = STATE_SENDING_DATA;
1876 case STATE_SENDING_DATA:
1878 * We could get a data error and never a transfer
1879 * complete so we'd better check for it here.
1881 * Note that we don't really care if we also got a
1882 * transfer complete; stopping the DMA and sending an
1885 if (test_and_clear_bit(EVENT_DATA_ERROR,
1886 &host->pending_events)) {
1887 dw_mci_stop_dma(host);
1888 if (!(host->data_status & (SDMMC_INT_DRTO |
1890 send_stop_abort(host, data);
1891 state = STATE_DATA_ERROR;
1895 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1896 &host->pending_events)) {
1898 * If all data-related interrupts don't come
1899 * within the given time in reading data state.
1901 if (host->dir_status == DW_MCI_RECV_STATUS)
1902 dw_mci_set_drto(host);
1906 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1909 * Handle an EVENT_DATA_ERROR that might have shown up
1910 * before the transfer completed. This might not have
1911 * been caught by the check above because the interrupt
1912 * could have gone off between the previous check and
1913 * the check for transfer complete.
1915 * Technically this ought not be needed assuming we
1916 * get a DATA_COMPLETE eventually (we'll notice the
1917 * error and end the request), but it shouldn't hurt.
1919 * This has the advantage of sending the stop command.
1921 if (test_and_clear_bit(EVENT_DATA_ERROR,
1922 &host->pending_events)) {
1923 dw_mci_stop_dma(host);
1924 if (!(host->data_status & (SDMMC_INT_DRTO |
1926 send_stop_abort(host, data);
1927 state = STATE_DATA_ERROR;
1930 prev_state = state = STATE_DATA_BUSY;
1934 case STATE_DATA_BUSY:
1935 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1936 &host->pending_events)) {
1938 * If data error interrupt comes but data over
1939 * interrupt doesn't come within the given time.
1940 * in reading data state.
1942 if (host->dir_status == DW_MCI_RECV_STATUS)
1943 dw_mci_set_drto(host);
1948 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1949 err = dw_mci_data_complete(host, data);
1952 if (!data->stop || mrq->sbc) {
1953 if (mrq->sbc && data->stop)
1954 data->stop->error = 0;
1955 dw_mci_request_end(host, mrq);
1959 /* stop command for open-ended transfer*/
1961 send_stop_abort(host, data);
1964 * If we don't have a command complete now we'll
1965 * never get one since we just reset everything;
1966 * better end the request.
1968 * If we do have a command complete we'll fall
1969 * through to the SENDING_STOP command and
1970 * everything will be peachy keen.
1972 if (!test_bit(EVENT_CMD_COMPLETE,
1973 &host->pending_events)) {
1975 dw_mci_request_end(host, mrq);
1981 * If err has non-zero,
1982 * stop-abort command has been already issued.
1984 prev_state = state = STATE_SENDING_STOP;
1988 case STATE_SENDING_STOP:
1989 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1990 &host->pending_events))
1993 /* CMD error in data command */
1994 if (mrq->cmd->error && mrq->data)
2000 if (!mrq->sbc && mrq->stop)
2001 dw_mci_command_complete(host, mrq->stop);
2003 host->cmd_status = 0;
2005 dw_mci_request_end(host, mrq);
2008 case STATE_DATA_ERROR:
2009 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2010 &host->pending_events))
2013 state = STATE_DATA_BUSY;
2016 } while (state != prev_state);
2018 host->state = state;
2020 spin_unlock(&host->lock);
2024 /* push final bytes to part_buf, only use during push */
2025 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2027 memcpy((void *)&host->part_buf, buf, cnt);
2028 host->part_buf_count = cnt;
2031 /* append bytes to part_buf, only use during push */
2032 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2034 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2035 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2036 host->part_buf_count += cnt;
2040 /* pull first bytes from part_buf, only use during pull */
2041 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2043 cnt = min_t(int, cnt, host->part_buf_count);
2045 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2047 host->part_buf_count -= cnt;
2048 host->part_buf_start += cnt;
2053 /* pull final bytes from the part_buf, assuming it's just been filled */
2054 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2056 memcpy(buf, &host->part_buf, cnt);
2057 host->part_buf_start = cnt;
2058 host->part_buf_count = (1 << host->data_shift) - cnt;
2061 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2063 struct mmc_data *data = host->data;
2066 /* try and push anything in the part_buf */
2067 if (unlikely(host->part_buf_count)) {
2068 int len = dw_mci_push_part_bytes(host, buf, cnt);
2072 if (host->part_buf_count == 2) {
2073 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2074 host->part_buf_count = 0;
2077 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2078 if (unlikely((unsigned long)buf & 0x1)) {
2080 u16 aligned_buf[64];
2081 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2082 int items = len >> 1;
2084 /* memcpy from input buffer into aligned buffer */
2085 memcpy(aligned_buf, buf, len);
2088 /* push data from aligned buffer into fifo */
2089 for (i = 0; i < items; ++i)
2090 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2097 for (; cnt >= 2; cnt -= 2)
2098 mci_fifo_writew(host->fifo_reg, *pdata++);
2101 /* put anything remaining in the part_buf */
2103 dw_mci_set_part_bytes(host, buf, cnt);
2104 /* Push data if we have reached the expected data length */
2105 if ((data->bytes_xfered + init_cnt) ==
2106 (data->blksz * data->blocks))
2107 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2111 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2113 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2114 if (unlikely((unsigned long)buf & 0x1)) {
2116 /* pull data from fifo into aligned buffer */
2117 u16 aligned_buf[64];
2118 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2119 int items = len >> 1;
2122 for (i = 0; i < items; ++i)
2123 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2124 /* memcpy from aligned buffer into output buffer */
2125 memcpy(buf, aligned_buf, len);
2134 for (; cnt >= 2; cnt -= 2)
2135 *pdata++ = mci_fifo_readw(host->fifo_reg);
2139 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2140 dw_mci_pull_final_bytes(host, buf, cnt);
2144 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2146 struct mmc_data *data = host->data;
2149 /* try and push anything in the part_buf */
2150 if (unlikely(host->part_buf_count)) {
2151 int len = dw_mci_push_part_bytes(host, buf, cnt);
2155 if (host->part_buf_count == 4) {
2156 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2157 host->part_buf_count = 0;
2160 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2161 if (unlikely((unsigned long)buf & 0x3)) {
2163 u32 aligned_buf[32];
2164 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2165 int items = len >> 2;
2167 /* memcpy from input buffer into aligned buffer */
2168 memcpy(aligned_buf, buf, len);
2171 /* push data from aligned buffer into fifo */
2172 for (i = 0; i < items; ++i)
2173 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2180 for (; cnt >= 4; cnt -= 4)
2181 mci_fifo_writel(host->fifo_reg, *pdata++);
2184 /* put anything remaining in the part_buf */
2186 dw_mci_set_part_bytes(host, buf, cnt);
2187 /* Push data if we have reached the expected data length */
2188 if ((data->bytes_xfered + init_cnt) ==
2189 (data->blksz * data->blocks))
2190 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2194 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2196 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2197 if (unlikely((unsigned long)buf & 0x3)) {
2199 /* pull data from fifo into aligned buffer */
2200 u32 aligned_buf[32];
2201 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2202 int items = len >> 2;
2205 for (i = 0; i < items; ++i)
2206 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2207 /* memcpy from aligned buffer into output buffer */
2208 memcpy(buf, aligned_buf, len);
2217 for (; cnt >= 4; cnt -= 4)
2218 *pdata++ = mci_fifo_readl(host->fifo_reg);
2222 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2223 dw_mci_pull_final_bytes(host, buf, cnt);
2227 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2229 struct mmc_data *data = host->data;
2232 /* try and push anything in the part_buf */
2233 if (unlikely(host->part_buf_count)) {
2234 int len = dw_mci_push_part_bytes(host, buf, cnt);
2239 if (host->part_buf_count == 8) {
2240 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2241 host->part_buf_count = 0;
2244 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2245 if (unlikely((unsigned long)buf & 0x7)) {
2247 u64 aligned_buf[16];
2248 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2249 int items = len >> 3;
2251 /* memcpy from input buffer into aligned buffer */
2252 memcpy(aligned_buf, buf, len);
2255 /* push data from aligned buffer into fifo */
2256 for (i = 0; i < items; ++i)
2257 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2264 for (; cnt >= 8; cnt -= 8)
2265 mci_fifo_writeq(host->fifo_reg, *pdata++);
2268 /* put anything remaining in the part_buf */
2270 dw_mci_set_part_bytes(host, buf, cnt);
2271 /* Push data if we have reached the expected data length */
2272 if ((data->bytes_xfered + init_cnt) ==
2273 (data->blksz * data->blocks))
2274 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2278 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2280 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2281 if (unlikely((unsigned long)buf & 0x7)) {
2283 /* pull data from fifo into aligned buffer */
2284 u64 aligned_buf[16];
2285 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2286 int items = len >> 3;
2289 for (i = 0; i < items; ++i)
2290 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2292 /* memcpy from aligned buffer into output buffer */
2293 memcpy(buf, aligned_buf, len);
2302 for (; cnt >= 8; cnt -= 8)
2303 *pdata++ = mci_fifo_readq(host->fifo_reg);
2307 host->part_buf = mci_fifo_readq(host->fifo_reg);
2308 dw_mci_pull_final_bytes(host, buf, cnt);
2312 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2316 /* get remaining partial bytes */
2317 len = dw_mci_pull_part_bytes(host, buf, cnt);
2318 if (unlikely(len == cnt))
2323 /* get the rest of the data */
2324 host->pull_data(host, buf, cnt);
2327 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2329 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2331 unsigned int offset;
2332 struct mmc_data *data = host->data;
2333 int shift = host->data_shift;
2336 unsigned int remain, fcnt;
2339 if (!sg_miter_next(sg_miter))
2342 host->sg = sg_miter->piter.sg;
2343 buf = sg_miter->addr;
2344 remain = sg_miter->length;
2348 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2349 << shift) + host->part_buf_count;
2350 len = min(remain, fcnt);
2353 dw_mci_pull_data(host, (void *)(buf + offset), len);
2354 data->bytes_xfered += len;
2359 sg_miter->consumed = offset;
2360 status = mci_readl(host, MINTSTS);
2361 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2362 /* if the RXDR is ready read again */
2363 } while ((status & SDMMC_INT_RXDR) ||
2364 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2367 if (!sg_miter_next(sg_miter))
2369 sg_miter->consumed = 0;
2371 sg_miter_stop(sg_miter);
2375 sg_miter_stop(sg_miter);
2377 smp_wmb(); /* drain writebuffer */
2378 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2381 static void dw_mci_write_data_pio(struct dw_mci *host)
2383 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2385 unsigned int offset;
2386 struct mmc_data *data = host->data;
2387 int shift = host->data_shift;
2390 unsigned int fifo_depth = host->fifo_depth;
2391 unsigned int remain, fcnt;
2394 if (!sg_miter_next(sg_miter))
2397 host->sg = sg_miter->piter.sg;
2398 buf = sg_miter->addr;
2399 remain = sg_miter->length;
2403 fcnt = ((fifo_depth -
2404 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2405 << shift) - host->part_buf_count;
2406 len = min(remain, fcnt);
2409 host->push_data(host, (void *)(buf + offset), len);
2410 data->bytes_xfered += len;
2415 sg_miter->consumed = offset;
2416 status = mci_readl(host, MINTSTS);
2417 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2418 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2421 if (!sg_miter_next(sg_miter))
2423 sg_miter->consumed = 0;
2425 sg_miter_stop(sg_miter);
2429 sg_miter_stop(sg_miter);
2431 smp_wmb(); /* drain writebuffer */
2432 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2435 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2437 if (!host->cmd_status)
2438 host->cmd_status = status;
2440 smp_wmb(); /* drain writebuffer */
2442 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2443 tasklet_schedule(&host->tasklet);
2446 static void dw_mci_handle_cd(struct dw_mci *host)
2450 for (i = 0; i < host->num_slots; i++) {
2451 struct dw_mci_slot *slot = host->slot[i];
2456 if (slot->mmc->ops->card_event)
2457 slot->mmc->ops->card_event(slot->mmc);
2458 mmc_detect_change(slot->mmc,
2459 msecs_to_jiffies(host->pdata->detect_delay_ms));
2463 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2465 struct dw_mci *host = dev_id;
2469 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2472 /* Check volt switch first, since it can look like an error */
2473 if ((host->state == STATE_SENDING_CMD11) &&
2474 (pending & SDMMC_INT_VOLT_SWITCH)) {
2475 unsigned long irqflags;
2477 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2478 pending &= ~SDMMC_INT_VOLT_SWITCH;
2481 * Hold the lock; we know cmd11_timer can't be kicked
2482 * off after the lock is released, so safe to delete.
2484 spin_lock_irqsave(&host->irq_lock, irqflags);
2485 dw_mci_cmd_interrupt(host, pending);
2486 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2488 del_timer(&host->cmd11_timer);
2491 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2492 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2493 host->cmd_status = pending;
2494 smp_wmb(); /* drain writebuffer */
2495 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2498 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2499 /* if there is an error report DATA_ERROR */
2500 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2501 host->data_status = pending;
2502 smp_wmb(); /* drain writebuffer */
2503 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2504 tasklet_schedule(&host->tasklet);
2507 if (pending & SDMMC_INT_DATA_OVER) {
2508 del_timer(&host->dto_timer);
2510 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2511 if (!host->data_status)
2512 host->data_status = pending;
2513 smp_wmb(); /* drain writebuffer */
2514 if (host->dir_status == DW_MCI_RECV_STATUS) {
2515 if (host->sg != NULL)
2516 dw_mci_read_data_pio(host, true);
2518 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2519 tasklet_schedule(&host->tasklet);
2522 if (pending & SDMMC_INT_RXDR) {
2523 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2524 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2525 dw_mci_read_data_pio(host, false);
2528 if (pending & SDMMC_INT_TXDR) {
2529 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2530 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2531 dw_mci_write_data_pio(host);
2534 if (pending & SDMMC_INT_CMD_DONE) {
2535 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2536 dw_mci_cmd_interrupt(host, pending);
2539 if (pending & SDMMC_INT_CD) {
2540 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2541 dw_mci_handle_cd(host);
2544 /* Handle SDIO Interrupts */
2545 for (i = 0; i < host->num_slots; i++) {
2546 struct dw_mci_slot *slot = host->slot[i];
2551 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2552 mci_writel(host, RINTSTS,
2553 SDMMC_INT_SDIO(slot->sdio_id));
2554 mmc_signal_sdio_irq(slot->mmc);
2560 if (host->use_dma != TRANS_MODE_IDMAC)
2563 /* Handle IDMA interrupts */
2564 if (host->dma_64bit_address == 1) {
2565 pending = mci_readl(host, IDSTS64);
2566 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2567 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2568 SDMMC_IDMAC_INT_RI);
2569 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2570 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2571 host->dma_ops->complete((void *)host);
2574 pending = mci_readl(host, IDSTS);
2575 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2576 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2577 SDMMC_IDMAC_INT_RI);
2578 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2579 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2580 host->dma_ops->complete((void *)host);
2587 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2589 struct mmc_host *mmc;
2590 struct dw_mci_slot *slot;
2591 const struct dw_mci_drv_data *drv_data = host->drv_data;
2595 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2599 slot = mmc_priv(mmc);
2601 slot->sdio_id = host->sdio_id0 + id;
2604 host->slot[id] = slot;
2606 mmc->ops = &dw_mci_ops;
2607 if (of_property_read_u32_array(host->dev->of_node,
2608 "clock-freq-min-max", freq, 2)) {
2609 mmc->f_min = DW_MCI_FREQ_MIN;
2610 mmc->f_max = DW_MCI_FREQ_MAX;
2613 "'clock-freq-min-max' property was deprecated.\n");
2614 mmc->f_min = freq[0];
2615 mmc->f_max = freq[1];
2618 /*if there are external regulators, get them*/
2619 ret = mmc_regulator_get_supply(mmc);
2620 if (ret == -EPROBE_DEFER)
2621 goto err_host_allocated;
2623 if (!mmc->ocr_avail)
2624 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2626 if (host->pdata->caps)
2627 mmc->caps = host->pdata->caps;
2630 * Support MMC_CAP_ERASE by default.
2631 * It needs to use trim/discard/erase commands.
2633 mmc->caps |= MMC_CAP_ERASE;
2635 if (host->pdata->pm_caps)
2636 mmc->pm_caps = host->pdata->pm_caps;
2638 if (host->dev->of_node) {
2639 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2643 ctrl_id = to_platform_device(host->dev)->id;
2645 if (drv_data && drv_data->caps)
2646 mmc->caps |= drv_data->caps[ctrl_id];
2648 if (host->pdata->caps2)
2649 mmc->caps2 = host->pdata->caps2;
2651 ret = mmc_of_parse(mmc);
2653 goto err_host_allocated;
2655 /* Useful defaults if platform data is unset. */
2656 if (host->use_dma == TRANS_MODE_IDMAC) {
2657 mmc->max_segs = host->ring_size;
2658 mmc->max_blk_size = 65535;
2659 mmc->max_seg_size = 0x1000;
2660 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2661 mmc->max_blk_count = mmc->max_req_size / 512;
2662 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2664 mmc->max_blk_size = 65535;
2665 mmc->max_blk_count = 65535;
2667 mmc->max_blk_size * mmc->max_blk_count;
2668 mmc->max_seg_size = mmc->max_req_size;
2670 /* TRANS_MODE_PIO */
2672 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2673 mmc->max_blk_count = 512;
2674 mmc->max_req_size = mmc->max_blk_size *
2676 mmc->max_seg_size = mmc->max_req_size;
2681 ret = mmc_add_host(mmc);
2683 goto err_host_allocated;
2685 #if defined(CONFIG_DEBUG_FS)
2686 dw_mci_init_debugfs(slot);
2696 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2698 /* Debugfs stuff is cleaned up by mmc core */
2699 mmc_remove_host(slot->mmc);
2700 slot->host->slot[id] = NULL;
2701 mmc_free_host(slot->mmc);
2704 static void dw_mci_init_dma(struct dw_mci *host)
2707 struct device *dev = host->dev;
2708 struct device_node *np = dev->of_node;
2711 * Check tansfer mode from HCON[17:16]
2712 * Clear the ambiguous description of dw_mmc databook:
2713 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2714 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2715 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2716 * 2b'11: Non DW DMA Interface -> pio only
2717 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2718 * simpler request/acknowledge handshake mechanism and both of them
2719 * are regarded as external dma master for dw_mmc.
2721 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2722 if (host->use_dma == DMA_INTERFACE_IDMA) {
2723 host->use_dma = TRANS_MODE_IDMAC;
2724 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2725 host->use_dma == DMA_INTERFACE_GDMA) {
2726 host->use_dma = TRANS_MODE_EDMAC;
2731 /* Determine which DMA interface to use */
2732 if (host->use_dma == TRANS_MODE_IDMAC) {
2734 * Check ADDR_CONFIG bit in HCON to find
2735 * IDMAC address bus width
2737 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2739 if (addr_config == 1) {
2740 /* host supports IDMAC in 64-bit address mode */
2741 host->dma_64bit_address = 1;
2743 "IDMAC supports 64-bit address mode.\n");
2744 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2745 dma_set_coherent_mask(host->dev,
2748 /* host supports IDMAC in 32-bit address mode */
2749 host->dma_64bit_address = 0;
2751 "IDMAC supports 32-bit address mode.\n");
2754 /* Alloc memory for sg translation */
2755 host->sg_cpu = dmam_alloc_coherent(host->dev,
2757 &host->sg_dma, GFP_KERNEL);
2758 if (!host->sg_cpu) {
2760 "%s: could not alloc DMA memory\n",
2765 host->dma_ops = &dw_mci_idmac_ops;
2766 dev_info(host->dev, "Using internal DMA controller.\n");
2768 /* TRANS_MODE_EDMAC: check dma bindings again */
2769 if ((of_property_count_strings(np, "dma-names") < 0) ||
2770 (!of_find_property(np, "dmas", NULL))) {
2773 host->dma_ops = &dw_mci_edmac_ops;
2774 dev_info(host->dev, "Using external DMA controller.\n");
2777 if (host->dma_ops->init && host->dma_ops->start &&
2778 host->dma_ops->stop && host->dma_ops->cleanup) {
2779 if (host->dma_ops->init(host)) {
2780 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2785 dev_err(host->dev, "DMA initialization not found.\n");
2792 dev_info(host->dev, "Using PIO mode.\n");
2793 host->use_dma = TRANS_MODE_PIO;
2796 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2798 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2801 ctrl = mci_readl(host, CTRL);
2803 mci_writel(host, CTRL, ctrl);
2805 /* wait till resets clear */
2807 ctrl = mci_readl(host, CTRL);
2808 if (!(ctrl & reset))
2810 } while (time_before(jiffies, timeout));
2813 "Timeout resetting block (ctrl reset %#x)\n",
2819 static bool dw_mci_reset(struct dw_mci *host)
2821 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2825 * Reseting generates a block interrupt, hence setting
2826 * the scatter-gather pointer to NULL.
2829 sg_miter_stop(&host->sg_miter);
2834 flags |= SDMMC_CTRL_DMA_RESET;
2836 if (dw_mci_ctrl_reset(host, flags)) {
2838 * In all cases we clear the RAWINTS register to clear any
2841 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2843 /* if using dma we wait for dma_req to clear */
2844 if (host->use_dma) {
2845 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2849 status = mci_readl(host, STATUS);
2850 if (!(status & SDMMC_STATUS_DMA_REQ))
2853 } while (time_before(jiffies, timeout));
2855 if (status & SDMMC_STATUS_DMA_REQ) {
2857 "%s: Timeout waiting for dma_req to clear during reset\n",
2862 /* when using DMA next we reset the fifo again */
2863 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2867 /* if the controller reset bit did clear, then set clock regs */
2868 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2870 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2876 if (host->use_dma == TRANS_MODE_IDMAC)
2877 /* It is also recommended that we reset and reprogram idmac */
2878 dw_mci_idmac_reset(host);
2883 /* After a CTRL reset we need to have CIU set clock registers */
2884 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2889 static void dw_mci_cmd11_timer(unsigned long arg)
2891 struct dw_mci *host = (struct dw_mci *)arg;
2893 if (host->state != STATE_SENDING_CMD11) {
2894 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2898 host->cmd_status = SDMMC_INT_RTO;
2899 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2900 tasklet_schedule(&host->tasklet);
2903 static void dw_mci_dto_timer(unsigned long arg)
2905 struct dw_mci *host = (struct dw_mci *)arg;
2907 switch (host->state) {
2908 case STATE_SENDING_DATA:
2909 case STATE_DATA_BUSY:
2911 * If DTO interrupt does NOT come in sending data state,
2912 * we should notify the driver to terminate current transfer
2913 * and report a data timeout to the core.
2915 host->data_status = SDMMC_INT_DRTO;
2916 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2917 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2918 tasklet_schedule(&host->tasklet);
2926 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2928 struct dw_mci_board *pdata;
2929 struct device *dev = host->dev;
2930 struct device_node *np = dev->of_node;
2931 const struct dw_mci_drv_data *drv_data = host->drv_data;
2933 u32 clock_frequency;
2935 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2937 return ERR_PTR(-ENOMEM);
2939 /* find reset controller when exist */
2940 pdata->rstc = devm_reset_control_get_optional(dev, "reset");
2941 if (IS_ERR(pdata->rstc)) {
2942 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2943 return ERR_PTR(-EPROBE_DEFER);
2946 /* find out number of slots supported */
2947 of_property_read_u32(np, "num-slots", &pdata->num_slots);
2949 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2951 "fifo-depth property not found, using value of FIFOTH register as default\n");
2953 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2955 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2956 pdata->bus_hz = clock_frequency;
2958 if (drv_data && drv_data->parse_dt) {
2959 ret = drv_data->parse_dt(host);
2961 return ERR_PTR(ret);
2967 #else /* CONFIG_OF */
2968 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2970 return ERR_PTR(-EINVAL);
2972 #endif /* CONFIG_OF */
2974 static void dw_mci_enable_cd(struct dw_mci *host)
2976 unsigned long irqflags;
2979 struct dw_mci_slot *slot;
2982 * No need for CD if all slots have a non-error GPIO
2983 * as well as broken card detection is found.
2985 for (i = 0; i < host->num_slots; i++) {
2986 slot = host->slot[i];
2987 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
2990 if (mmc_gpio_get_cd(slot->mmc) < 0)
2993 if (i == host->num_slots)
2996 spin_lock_irqsave(&host->irq_lock, irqflags);
2997 temp = mci_readl(host, INTMASK);
2998 temp |= SDMMC_INT_CD;
2999 mci_writel(host, INTMASK, temp);
3000 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3003 int dw_mci_probe(struct dw_mci *host)
3005 const struct dw_mci_drv_data *drv_data = host->drv_data;
3006 int width, i, ret = 0;
3011 host->pdata = dw_mci_parse_dt(host);
3012 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3013 return -EPROBE_DEFER;
3014 } else if (IS_ERR(host->pdata)) {
3015 dev_err(host->dev, "platform data not available\n");
3020 host->biu_clk = devm_clk_get(host->dev, "biu");
3021 if (IS_ERR(host->biu_clk)) {
3022 dev_dbg(host->dev, "biu clock not available\n");
3024 ret = clk_prepare_enable(host->biu_clk);
3026 dev_err(host->dev, "failed to enable biu clock\n");
3031 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3032 if (IS_ERR(host->ciu_clk)) {
3033 dev_dbg(host->dev, "ciu clock not available\n");
3034 host->bus_hz = host->pdata->bus_hz;
3036 ret = clk_prepare_enable(host->ciu_clk);
3038 dev_err(host->dev, "failed to enable ciu clock\n");
3042 if (host->pdata->bus_hz) {
3043 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3046 "Unable to set bus rate to %uHz\n",
3047 host->pdata->bus_hz);
3049 host->bus_hz = clk_get_rate(host->ciu_clk);
3052 if (!host->bus_hz) {
3054 "Platform data must supply bus speed\n");
3059 if (drv_data && drv_data->init) {
3060 ret = drv_data->init(host);
3063 "implementation specific init failed\n");
3068 if (!IS_ERR(host->pdata->rstc)) {
3069 reset_control_assert(host->pdata->rstc);
3070 usleep_range(10, 50);
3071 reset_control_deassert(host->pdata->rstc);
3074 setup_timer(&host->cmd11_timer,
3075 dw_mci_cmd11_timer, (unsigned long)host);
3077 setup_timer(&host->dto_timer,
3078 dw_mci_dto_timer, (unsigned long)host);
3080 spin_lock_init(&host->lock);
3081 spin_lock_init(&host->irq_lock);
3082 INIT_LIST_HEAD(&host->queue);
3085 * Get the host data width - this assumes that HCON has been set with
3086 * the correct values.
3088 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3090 host->push_data = dw_mci_push_data16;
3091 host->pull_data = dw_mci_pull_data16;
3093 host->data_shift = 1;
3094 } else if (i == 2) {
3095 host->push_data = dw_mci_push_data64;
3096 host->pull_data = dw_mci_pull_data64;
3098 host->data_shift = 3;
3100 /* Check for a reserved value, and warn if it is */
3102 "HCON reports a reserved host data width!\n"
3103 "Defaulting to 32-bit access.\n");
3104 host->push_data = dw_mci_push_data32;
3105 host->pull_data = dw_mci_pull_data32;
3107 host->data_shift = 2;
3110 /* Reset all blocks */
3111 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3116 host->dma_ops = host->pdata->dma_ops;
3117 dw_mci_init_dma(host);
3119 /* Clear the interrupts for the host controller */
3120 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3121 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3123 /* Put in max timeout */
3124 mci_writel(host, TMOUT, 0xFFFFFFFF);
3127 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3128 * Tx Mark = fifo_size / 2 DMA Size = 8
3130 if (!host->pdata->fifo_depth) {
3132 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3133 * have been overwritten by the bootloader, just like we're
3134 * about to do, so if you know the value for your hardware, you
3135 * should put it in the platform data.
3137 fifo_size = mci_readl(host, FIFOTH);
3138 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3140 fifo_size = host->pdata->fifo_depth;
3142 host->fifo_depth = fifo_size;
3144 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3145 mci_writel(host, FIFOTH, host->fifoth_val);
3147 /* disable clock to CIU */
3148 mci_writel(host, CLKENA, 0);
3149 mci_writel(host, CLKSRC, 0);
3152 * In 2.40a spec, Data offset is changed.
3153 * Need to check the version-id and set data-offset for DATA register.
3155 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3156 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3158 if (host->verid < DW_MMC_240A)
3159 host->fifo_reg = host->regs + DATA_OFFSET;
3161 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3163 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3164 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3165 host->irq_flags, "dw-mci", host);
3169 if (host->pdata->num_slots)
3170 host->num_slots = host->pdata->num_slots;
3172 host->num_slots = 1;
3174 if (host->num_slots < 1 ||
3175 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3177 "Platform data must supply correct num_slots.\n");
3183 * Enable interrupts for command done, data over, data empty,
3184 * receive ready and error such as transmit, receive timeout, crc error
3186 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3187 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3188 DW_MCI_ERROR_FLAGS);
3189 /* Enable mci interrupt */
3190 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3193 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3194 host->irq, width, fifo_size);
3196 /* We need at least one slot to succeed */
3197 for (i = 0; i < host->num_slots; i++) {
3198 ret = dw_mci_init_slot(host, i);
3200 dev_dbg(host->dev, "slot %d init failed\n", i);
3206 dev_info(host->dev, "%d slots initialized\n", init_slots);
3209 "attempted to initialize %d slots, but failed on all\n",
3214 /* Now that slots are all setup, we can enable card detect */
3215 dw_mci_enable_cd(host);
3220 if (host->use_dma && host->dma_ops->exit)
3221 host->dma_ops->exit(host);
3223 if (!IS_ERR(host->pdata->rstc))
3224 reset_control_assert(host->pdata->rstc);
3227 clk_disable_unprepare(host->ciu_clk);
3230 clk_disable_unprepare(host->biu_clk);
3234 EXPORT_SYMBOL(dw_mci_probe);
3236 void dw_mci_remove(struct dw_mci *host)
3240 for (i = 0; i < host->num_slots; i++) {
3241 dev_dbg(host->dev, "remove slot %d\n", i);
3243 dw_mci_cleanup_slot(host->slot[i], i);
3246 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3247 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3249 /* disable clock to CIU */
3250 mci_writel(host, CLKENA, 0);
3251 mci_writel(host, CLKSRC, 0);
3253 if (host->use_dma && host->dma_ops->exit)
3254 host->dma_ops->exit(host);
3256 if (!IS_ERR(host->pdata->rstc))
3257 reset_control_assert(host->pdata->rstc);
3259 clk_disable_unprepare(host->ciu_clk);
3260 clk_disable_unprepare(host->biu_clk);
3262 EXPORT_SYMBOL(dw_mci_remove);
3267 int dw_mci_runtime_suspend(struct device *dev)
3269 struct dw_mci *host = dev_get_drvdata(dev);
3271 if (host->use_dma && host->dma_ops->exit)
3272 host->dma_ops->exit(host);
3274 clk_disable_unprepare(host->ciu_clk);
3276 if (host->cur_slot &&
3277 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3278 !mmc_card_is_removable(host->cur_slot->mmc)))
3279 clk_disable_unprepare(host->biu_clk);
3283 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3285 int dw_mci_runtime_resume(struct device *dev)
3288 struct dw_mci *host = dev_get_drvdata(dev);
3290 if (host->cur_slot &&
3291 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3292 !mmc_card_is_removable(host->cur_slot->mmc))) {
3293 ret = clk_prepare_enable(host->biu_clk);
3298 ret = clk_prepare_enable(host->ciu_clk);
3302 if (host->use_dma && host->dma_ops->init)
3303 host->dma_ops->init(host);
3306 * Restore the initial value at FIFOTH register
3307 * And Invalidate the prev_blksz with zero
3309 mci_writel(host, FIFOTH, host->fifoth_val);
3310 host->prev_blksz = 0;
3312 /* Put in max timeout */
3313 mci_writel(host, TMOUT, 0xFFFFFFFF);
3315 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3316 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3317 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3318 DW_MCI_ERROR_FLAGS);
3319 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3321 for (i = 0; i < host->num_slots; i++) {
3322 struct dw_mci_slot *slot = host->slot[i];
3326 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3327 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3328 dw_mci_setup_bus(slot, true);
3332 /* Now that slots are all setup, we can enable card detect */
3333 dw_mci_enable_cd(host);
3337 EXPORT_SYMBOL(dw_mci_runtime_resume);
3338 #endif /* CONFIG_PM */
3340 static int __init dw_mci_init(void)
3342 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3346 static void __exit dw_mci_exit(void)
3350 module_init(dw_mci_init);
3351 module_exit(dw_mci_exit);
3353 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3354 MODULE_AUTHOR("NXP Semiconductor VietNam");
3355 MODULE_AUTHOR("Imagination Technologies Ltd");
3356 MODULE_LICENSE("GPL v2");