drivers/mmc/host/au1xmmc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
   4  *
   5  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
   6  *
   7  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
   8  *  the following copyright notices:
   9  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
  10  *     Portions Copyright (C) 2002 Embedix, Inc
  11  *     Copyright 2002 Hewlett-Packard Company
  12
  13  *  2.6 version of this driver inspired by:
  14  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  15  *     All Rights Reserved.
  16  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  17  *     All Rights Reserved.
  18  *
  19
  20  */
  21
  22 /* Why don't we use the SD controllers' carddetect feature?
  23  *
  24  * From the AU1100 MMC application guide:
  25  * If the Au1100-based design is intended to support both MultiMediaCards
  26  * and 1- or 4-data bit SecureDigital cards, then the solution is to
  27  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  28  * In doing so, a MMC card never enters SPI-mode communications,
  29  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  30  * (the low to high transition will not occur).
  31  */
  32
  33 #include <linux/clk.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/mm.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/scatterlist.h>
  41 #include <linux/highmem.h>
  42 #include <linux/leds.h>
  43 #include <linux/mmc/host.h>
  44 #include <linux/slab.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/mach-au1x00/au1000.h>
  48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  49 #include <asm/mach-au1x00/au1100_mmc.h>
  50
  51 #define DRIVER_NAME "au1xxx-mmc"
  52
  53 /* Set this to enable special debugging macros */
  54 /* #define DEBUG */
  55
  56 #ifdef DEBUG
  57 #define DBG(fmt, idx, args...)  \
  58         pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args)
  59 #else
  60 #define DBG(fmt, idx, args...) do {} while (0)
  61 #endif
  62
  63 /* Hardware definitions */
  64 #define AU1XMMC_DESCRIPTOR_COUNT 1
  65
  66 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
  67 #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
  68 #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
  69
  70 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
  71                      MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
  72                      MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
  73
  74 /* This gives us a hard value for the stop command that we can write directly
  75  * to the command register.
  76  */
  77 #define STOP_CMD        \
  78         (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
  79
  80 /* This is the set of interrupts that we configure by default. */
  81 #define AU1XMMC_INTERRUPTS                              \
  82         (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT |  \
  83          SD_CONFIG_CR | SD_CONFIG_I)
  84
  85 /* The poll event (looking for insert/remove events runs twice a second. */
  86 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
  87
  88 struct au1xmmc_host {
  89         struct mmc_host *mmc;
  90         struct mmc_request *mrq;
  91
  92         u32 flags;
  93         void __iomem *iobase;
  94         u32 clock;
  95         u32 bus_width;
  96         u32 power_mode;
  97
  98         int status;
  99
 100         struct {
 101                 int len;
 102                 int dir;
 103         } dma;
 104
 105         struct {
 106                 int index;
 107                 int offset;
 108                 int len;
 109         } pio;
 110
 111         u32 tx_chan;
 112         u32 rx_chan;
 113
 114         int irq;
 115
 116         struct tasklet_struct finish_task;
 117         struct tasklet_struct data_task;
 118         struct au1xmmc_platform_data *platdata;
 119         struct platform_device *pdev;
 120         struct resource *ioarea;
 121         struct clk *clk;
 122 };
 123
 124 /* Status flags used by the host structure */
 125 #define HOST_F_XMIT     0x0001
 126 #define HOST_F_RECV     0x0002
 127 #define HOST_F_DMA      0x0010
 128 #define HOST_F_DBDMA    0x0020
 129 #define HOST_F_ACTIVE   0x0100
 130 #define HOST_F_STOP     0x1000
 131
 132 #define HOST_S_IDLE     0x0001
 133 #define HOST_S_CMD      0x0002
 134 #define HOST_S_DATA     0x0003
 135 #define HOST_S_STOP     0x0004
 136
 137 /* Easy access macros */
 138 #define HOST_STATUS(h)  ((h)->iobase + SD_STATUS)
 139 #define HOST_CONFIG(h)  ((h)->iobase + SD_CONFIG)
 140 #define HOST_ENABLE(h)  ((h)->iobase + SD_ENABLE)
 141 #define HOST_TXPORT(h)  ((h)->iobase + SD_TXPORT)
 142 #define HOST_RXPORT(h)  ((h)->iobase + SD_RXPORT)
 143 #define HOST_CMDARG(h)  ((h)->iobase + SD_CMDARG)
 144 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
 145 #define HOST_CMD(h)     ((h)->iobase + SD_CMD)
 146 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
 147 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
 148 #define HOST_DEBUG(h)   ((h)->iobase + SD_DEBUG)
 149
 150 #define DMA_CHANNEL(h)  \
 151         (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
 152
 153 static inline int has_dbdma(void)
 154 {
 155         switch (alchemy_get_cputype()) {
 156         case ALCHEMY_CPU_AU1200:
 157         case ALCHEMY_CPU_AU1300:
 158                 return 1;
 159         default:
 160                 return 0;
 161         }
 162 }
 163
 164 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
 165 {
 166         u32 val = __raw_readl(HOST_CONFIG(host));
 167         val |= mask;
 168         __raw_writel(val, HOST_CONFIG(host));
 169         wmb(); /* drain writebuffer */
 170 }
 171
 172 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
 173 {
 174         u32 val = __raw_readl(HOST_CONFIG2(host));
 175
 176         __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
 177         wmb(); /* drain writebuffer */
 178         mdelay(1);
 179
 180         /* SEND_STOP will turn off clock control - this re-enables it */
 181         val &= ~SD_CONFIG2_DF;
 182
 183         __raw_writel(val, HOST_CONFIG2(host));
 184         wmb(); /* drain writebuffer */
 185 }
 186
 187 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
 188 {
 189         u32 val = __raw_readl(HOST_CONFIG(host));
 190         val &= ~mask;
 191         __raw_writel(val, HOST_CONFIG(host));
 192         wmb(); /* drain writebuffer */
 193 }
 194
 195 static inline void SEND_STOP(struct au1xmmc_host *host)
 196 {
 197         u32 config2;
 198
 199         WARN_ON(host->status != HOST_S_DATA);
 200         host->status = HOST_S_STOP;
 201
 202         config2 = __raw_readl(HOST_CONFIG2(host));
 203         __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
 204         wmb(); /* drain writebuffer */
 205
 206         /* Send the stop command */
 207         __raw_writel(STOP_CMD, HOST_CMD(host));
 208         wmb(); /* drain writebuffer */
 209 }
 210
 211 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
 212 {
 213         if (host->platdata && host->platdata->set_power)
 214                 host->platdata->set_power(host->mmc, state);
 215 }
 216
 217 static int au1xmmc_card_inserted(struct mmc_host *mmc)
 218 {
 219         struct au1xmmc_host *host = mmc_priv(mmc);
 220
 221         if (host->platdata && host->platdata->card_inserted)
 222                 return !!host->platdata->card_inserted(host->mmc);
 223
 224         return -ENOSYS;
 225 }
 226
 227 static int au1xmmc_card_readonly(struct mmc_host *mmc)
 228 {
 229         struct au1xmmc_host *host = mmc_priv(mmc);
 230
 231         if (host->platdata && host->platdata->card_readonly)
 232                 return !!host->platdata->card_readonly(mmc);
 233
 234         return -ENOSYS;
 235 }
 236
 237 static void au1xmmc_finish_request(struct au1xmmc_host *host)
 238 {
 239         struct mmc_request *mrq = host->mrq;
 240
 241         host->mrq = NULL;
 242         host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
 243
 244         host->dma.len = 0;
 245         host->dma.dir = 0;
 246
 247         host->pio.index  = 0;
 248         host->pio.offset = 0;
 249         host->pio.len = 0;
 250
 251         host->status = HOST_S_IDLE;
 252
 253         mmc_request_done(host->mmc, mrq);
 254 }
 255
 256 static void au1xmmc_tasklet_finish(unsigned long param)
 257 {
 258         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 259         au1xmmc_finish_request(host);
 260 }
 261
 262 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
 263                                 struct mmc_command *cmd, struct mmc_data *data)
 264 {
 265         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
 266
 267         switch (mmc_resp_type(cmd)) {
 268         case MMC_RSP_NONE:
 269                 break;
 270         case MMC_RSP_R1:
 271                 mmccmd |= SD_CMD_RT_1;
 272                 break;
 273         case MMC_RSP_R1B:
 274                 mmccmd |= SD_CMD_RT_1B;
 275                 break;
 276         case MMC_RSP_R2:
 277                 mmccmd |= SD_CMD_RT_2;
 278                 break;
 279         case MMC_RSP_R3:
 280                 mmccmd |= SD_CMD_RT_3;
 281                 break;
 282         default:
 283                 pr_info("au1xmmc: unhandled response type %02x\n",
 284                         mmc_resp_type(cmd));
 285                 return -EINVAL;
 286         }
 287
 288         if (data) {
 289                 if (data->flags & MMC_DATA_READ) {
 290                         if (data->blocks > 1)
 291                                 mmccmd |= SD_CMD_CT_4;
 292                         else
 293                                 mmccmd |= SD_CMD_CT_2;
 294                 } else if (data->flags & MMC_DATA_WRITE) {
 295                         if (data->blocks > 1)
 296                                 mmccmd |= SD_CMD_CT_3;
 297                         else
 298                                 mmccmd |= SD_CMD_CT_1;
 299                 }
 300         }
 301
 302         __raw_writel(cmd->arg, HOST_CMDARG(host));
 303         wmb(); /* drain writebuffer */
 304
 305         if (wait)
 306                 IRQ_OFF(host, SD_CONFIG_CR);
 307
 308         __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
 309         wmb(); /* drain writebuffer */
 310
 311         /* Wait for the command to go on the line */
 312         while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)
 313                 /* nop */;
 314
 315         /* Wait for the command to come back */
 316         if (wait) {
 317                 u32 status = __raw_readl(HOST_STATUS(host));
 318
 319                 while (!(status & SD_STATUS_CR))
 320                         status = __raw_readl(HOST_STATUS(host));
 321
 322                 /* Clear the CR status */
 323                 __raw_writel(SD_STATUS_CR, HOST_STATUS(host));
 324
 325                 IRQ_ON(host, SD_CONFIG_CR);
 326         }
 327
 328         return 0;
 329 }
 330
 331 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
 332 {
 333         struct mmc_request *mrq = host->mrq;
 334         struct mmc_data *data;
 335         u32 crc;
 336
 337         WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
 338
 339         if (host->mrq == NULL)
 340                 return;
 341
 342         data = mrq->cmd->data;
 343
 344         if (status == 0)
 345                 status = __raw_readl(HOST_STATUS(host));
 346
 347         /* The transaction is really over when the SD_STATUS_DB bit is clear */
 348         while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
 349                 status = __raw_readl(HOST_STATUS(host));
 350
 351         data->error = 0;
 352         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
 353
 354         /* Process any errors */
 355         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
 356         if (host->flags & HOST_F_XMIT)
 357                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
 358
 359         if (crc)
 360                 data->error = -EILSEQ;
 361
 362         /* Clear the CRC bits */
 363         __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
 364
 365         data->bytes_xfered = 0;
 366
 367         if (!data->error) {
 368                 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
 369                         u32 chan = DMA_CHANNEL(host);
 370
 371                         chan_tab_t *c = *((chan_tab_t **)chan);
 372                         au1x_dma_chan_t *cp = c->chan_ptr;
 373                         data->bytes_xfered = cp->ddma_bytecnt;
 374                 } else
 375                         data->bytes_xfered =
 376                                 (data->blocks * data->blksz) - host->pio.len;
 377         }
 378
 379         au1xmmc_finish_request(host);
 380 }
 381
 382 static void au1xmmc_tasklet_data(unsigned long param)
 383 {
 384         struct au1xmmc_host *host = (struct au1xmmc_host *)param;
 385
 386         u32 status = __raw_readl(HOST_STATUS(host));
 387         au1xmmc_data_complete(host, status);
 388 }
 389
 390 #define AU1XMMC_MAX_TRANSFER 8
 391
 392 static void au1xmmc_send_pio(struct au1xmmc_host *host)
 393 {
 394         struct mmc_data *data;
 395         int sg_len, max, count;
 396         unsigned char *sg_ptr, val;
 397         u32 status;
 398         struct scatterlist *sg;
 399
 400         data = host->mrq->data;
 401
 402         if (!(host->flags & HOST_F_XMIT))
 403                 return;
 404
 405         /* This is the pointer to the data buffer */
 406         sg = &data->sg[host->pio.index];
 407         sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset;
 408
 409         /* This is the space left inside the buffer */
 410         sg_len = data->sg[host->pio.index].length - host->pio.offset;
 411
 412         /* Check if we need less than the size of the sg_buffer */
 413         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
 414         if (max > AU1XMMC_MAX_TRANSFER)
 415                 max = AU1XMMC_MAX_TRANSFER;
 416
 417         for (count = 0; count < max; count++) {
 418                 status = __raw_readl(HOST_STATUS(host));
 419
 420                 if (!(status & SD_STATUS_TH))
 421                         break;
 422
 423                 val = sg_ptr[count];
 424
 425                 __raw_writel((unsigned long)val, HOST_TXPORT(host));
 426                 wmb(); /* drain writebuffer */
 427         }
 428         kunmap_atomic(sg_ptr);
 429
 430         host->pio.len -= count;
 431         host->pio.offset += count;
 432
 433         if (count == sg_len) {
 434                 host->pio.index++;
 435                 host->pio.offset = 0;
 436         }
 437
 438         if (host->pio.len == 0) {
 439                 IRQ_OFF(host, SD_CONFIG_TH);
 440
 441                 if (host->flags & HOST_F_STOP)
 442                         SEND_STOP(host);
 443
 444                 tasklet_schedule(&host->data_task);
 445         }
 446 }
 447
 448 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
 449 {
 450         struct mmc_data *data;
 451         int max, count, sg_len = 0;
 452         unsigned char *sg_ptr = NULL;
 453         u32 status, val;
 454         struct scatterlist *sg;
 455
 456         data = host->mrq->data;
 457
 458         if (!(host->flags & HOST_F_RECV))
 459                 return;
 460
 461         max = host->pio.len;
 462
 463         if (host->pio.index < host->dma.len) {
 464                 sg = &data->sg[host->pio.index];
 465                 sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset;
 466
 467                 /* This is the space left inside the buffer */
 468                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
 469
 470                 /* Check if we need less than the size of the sg_buffer */
 471                 if (sg_len < max)
 472                         max = sg_len;
 473         }
 474
 475         if (max > AU1XMMC_MAX_TRANSFER)
 476                 max = AU1XMMC_MAX_TRANSFER;
 477
 478         for (count = 0; count < max; count++) {
 479                 status = __raw_readl(HOST_STATUS(host));
 480
 481                 if (!(status & SD_STATUS_NE))
 482                         break;
 483
 484                 if (status & SD_STATUS_RC) {
 485                         DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
 486                                         host->pio.len, count);
 487                         break;
 488                 }
 489
 490                 if (status & SD_STATUS_RO) {
 491                         DBG("RX Overrun [%d + %d]\n", host->pdev->id,
 492                                         host->pio.len, count);
 493                         break;
 494                 }
 495                 else if (status & SD_STATUS_RU) {
 496                         DBG("RX Underrun [%d + %d]\n", host->pdev->id,
 497                                         host->pio.len,  count);
 498                         break;
 499                 }
 500
 501                 val = __raw_readl(HOST_RXPORT(host));
 502
 503                 if (sg_ptr)
 504                         sg_ptr[count] = (unsigned char)(val & 0xFF);
 505         }
 506         if (sg_ptr)
 507                 kunmap_atomic(sg_ptr);
 508
 509         host->pio.len -= count;
 510         host->pio.offset += count;
 511
 512         if (sg_len && count == sg_len) {
 513                 host->pio.index++;
 514                 host->pio.offset = 0;
 515         }
 516
 517         if (host->pio.len == 0) {
 518                 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 519                 IRQ_OFF(host, SD_CONFIG_NE);
 520
 521                 if (host->flags & HOST_F_STOP)
 522                         SEND_STOP(host);
 523
 524                 tasklet_schedule(&host->data_task);
 525         }
 526 }
 527
 528 /* This is called when a command has been completed - grab the response
 529  * and check for errors.  Then start the data transfer if it is indicated.
 530  */
 531 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
 532 {
 533         struct mmc_request *mrq = host->mrq;
 534         struct mmc_command *cmd;
 535         u32 r[4];
 536         int i, trans;
 537
 538         if (!host->mrq)
 539                 return;
 540
 541         cmd = mrq->cmd;
 542         cmd->error = 0;
 543
 544         if (cmd->flags & MMC_RSP_PRESENT) {
 545                 if (cmd->flags & MMC_RSP_136) {
 546                         r[0] = __raw_readl(host->iobase + SD_RESP3);
 547                         r[1] = __raw_readl(host->iobase + SD_RESP2);
 548                         r[2] = __raw_readl(host->iobase + SD_RESP1);
 549                         r[3] = __raw_readl(host->iobase + SD_RESP0);
 550
 551                         /* The CRC is omitted from the response, so really
 552                          * we only got 120 bytes, but the engine expects
 553                          * 128 bits, so we have to shift things up.
 554                          */
 555                         for (i = 0; i < 4; i++) {
 556                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
 557                                 if (i != 3)
 558                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
 559                         }
 560                 } else {
 561                         /* Techincally, we should be getting all 48 bits of
 562                          * the response (SD_RESP1 + SD_RESP2), but because
 563                          * our response omits the CRC, our data ends up
 564                          * being shifted 8 bits to the right.  In this case,
 565                          * that means that the OSR data starts at bit 31,
 566                          * so we can just read RESP0 and return that.
 567                          */
 568                         cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);
 569                 }
 570         }
 571
 572         /* Figure out errors */
 573         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
 574                 cmd->error = -EILSEQ;
 575
 576         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
 577
 578         if (!trans || cmd->error) {
 579                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
 580                 tasklet_schedule(&host->finish_task);
 581                 return;
 582         }
 583
 584         host->status = HOST_S_DATA;
 585
 586         if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
 587                 u32 channel = DMA_CHANNEL(host);
 588
 589                 /* Start the DBDMA as soon as the buffer gets something in it */
 590
 591                 if (host->flags & HOST_F_RECV) {
 592                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
 593
 594                         while((status & mask) != mask)
 595                                 status = __raw_readl(HOST_STATUS(host));
 596                 }
 597
 598                 au1xxx_dbdma_start(channel);
 599         }
 600 }
 601
 602 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
 603 {
 604         unsigned int pbus = clk_get_rate(host->clk);
 605         unsigned int divisor = ((pbus / rate) / 2) - 1;
 606         u32 config;
 607
 608         config = __raw_readl(HOST_CONFIG(host));
 609
 610         config &= ~(SD_CONFIG_DIV);
 611         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
 612
 613         __raw_writel(config, HOST_CONFIG(host));
 614         wmb(); /* drain writebuffer */
 615 }
 616
 617 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
 618                                 struct mmc_data *data)
 619 {
 620         int datalen = data->blocks * data->blksz;
 621
 622         if (data->flags & MMC_DATA_READ)
 623                 host->flags |= HOST_F_RECV;
 624         else
 625                 host->flags |= HOST_F_XMIT;
 626
 627         if (host->mrq->stop)
 628                 host->flags |= HOST_F_STOP;
 629
 630         host->dma.dir = DMA_BIDIRECTIONAL;
 631
 632         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 633                                    data->sg_len, host->dma.dir);
 634
 635         if (host->dma.len == 0)
 636                 return -ETIMEDOUT;
 637
 638         __raw_writel(data->blksz - 1, HOST_BLKSIZE(host));
 639
 640         if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
 641                 int i;
 642                 u32 channel = DMA_CHANNEL(host);
 643
 644                 au1xxx_dbdma_stop(channel);
 645
 646                 for (i = 0; i < host->dma.len; i++) {
 647                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
 648                         struct scatterlist *sg = &data->sg[i];
 649                         int sg_len = sg->length;
 650
 651                         int len = (datalen > sg_len) ? sg_len : datalen;
 652
 653                         if (i == host->dma.len - 1)
 654                                 flags = DDMA_FLAGS_IE;
 655
 656                         if (host->flags & HOST_F_XMIT) {
 657                                 ret = au1xxx_dbdma_put_source(channel,
 658                                         sg_phys(sg), len, flags);
 659                         } else {
 660                                 ret = au1xxx_dbdma_put_dest(channel,
 661                                         sg_phys(sg), len, flags);
 662                         }
 663
 664                         if (!ret)
 665                                 goto dataerr;
 666
 667                         datalen -= len;
 668                 }
 669         } else {
 670                 host->pio.index = 0;
 671                 host->pio.offset = 0;
 672                 host->pio.len = datalen;
 673
 674                 if (host->flags & HOST_F_XMIT)
 675                         IRQ_ON(host, SD_CONFIG_TH);
 676                 else
 677                         IRQ_ON(host, SD_CONFIG_NE);
 678                         /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 679         }
 680
 681         return 0;
 682
 683 dataerr:
 684         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 685                         host->dma.dir);
 686         return -ETIMEDOUT;
 687 }
 688
 689 /* This actually starts a command or data transaction */
 690 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
 691 {
 692         struct au1xmmc_host *host = mmc_priv(mmc);
 693         int ret = 0;
 694
 695         WARN_ON(irqs_disabled());
 696         WARN_ON(host->status != HOST_S_IDLE);
 697
 698         host->mrq = mrq;
 699         host->status = HOST_S_CMD;
 700
 701         /* fail request immediately if no card is present */
 702         if (0 == au1xmmc_card_inserted(mmc)) {
 703                 mrq->cmd->error = -ENOMEDIUM;
 704                 au1xmmc_finish_request(host);
 705                 return;
 706         }
 707
 708         if (mrq->data) {
 709                 FLUSH_FIFO(host);
 710                 ret = au1xmmc_prepare_data(host, mrq->data);
 711         }
 712
 713         if (!ret)
 714                 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
 715
 716         if (ret) {
 717                 mrq->cmd->error = ret;
 718                 au1xmmc_finish_request(host);
 719         }
 720 }
 721
 722 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
 723 {
 724         /* Apply the clock */
 725         __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));
 726         wmb(); /* drain writebuffer */
 727         mdelay(1);
 728
 729         __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
 730         wmb(); /* drain writebuffer */
 731         mdelay(5);
 732
 733         __raw_writel(~0, HOST_STATUS(host));
 734         wmb(); /* drain writebuffer */
 735
 736         __raw_writel(0, HOST_BLKSIZE(host));
 737         __raw_writel(0x001fffff, HOST_TIMEOUT(host));
 738         wmb(); /* drain writebuffer */
 739
 740         __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 741         wmb(); /* drain writebuffer */
 742
 743         __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
 744         wmb(); /* drain writebuffer */
 745         mdelay(1);
 746
 747         __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 748         wmb(); /* drain writebuffer */
 749
 750         /* Configure interrupts */
 751         __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
 752         wmb(); /* drain writebuffer */
 753 }
 754
 755
 756 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 757 {
 758         struct au1xmmc_host *host = mmc_priv(mmc);
 759         u32 config2;
 760
 761         if (ios->power_mode == MMC_POWER_OFF)
 762                 au1xmmc_set_power(host, 0);
 763         else if (ios->power_mode == MMC_POWER_ON) {
 764                 au1xmmc_set_power(host, 1);
 765         }
 766
 767         if (ios->clock && ios->clock != host->clock) {
 768                 au1xmmc_set_clock(host, ios->clock);
 769                 host->clock = ios->clock;
 770         }
 771
 772         config2 = __raw_readl(HOST_CONFIG2(host));
 773         switch (ios->bus_width) {
 774         case MMC_BUS_WIDTH_8:
 775                 config2 |= SD_CONFIG2_BB;
 776                 break;
 777         case MMC_BUS_WIDTH_4:
 778                 config2 &= ~SD_CONFIG2_BB;
 779                 config2 |= SD_CONFIG2_WB;
 780                 break;
 781         case MMC_BUS_WIDTH_1:
 782                 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
 783                 break;
 784         }
 785         __raw_writel(config2, HOST_CONFIG2(host));
 786         wmb(); /* drain writebuffer */
 787 }
 788
 789 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
 790 #define STATUS_DATA_IN  (SD_STATUS_NE)
 791 #define STATUS_DATA_OUT (SD_STATUS_TH)
 792
 793 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
 794 {
 795         struct au1xmmc_host *host = dev_id;
 796         u32 status;
 797
 798         status = __raw_readl(HOST_STATUS(host));
 799
 800         if (!(status & SD_STATUS_I))
 801                 return IRQ_NONE;        /* not ours */
 802
 803         if (status & SD_STATUS_SI)      /* SDIO */
 804                 mmc_signal_sdio_irq(host->mmc);
 805
 806         if (host->mrq && (status & STATUS_TIMEOUT)) {
 807                 if (status & SD_STATUS_RAT)
 808                         host->mrq->cmd->error = -ETIMEDOUT;
 809                 else if (status & SD_STATUS_DT)
 810                         host->mrq->data->error = -ETIMEDOUT;
 811
 812                 /* In PIO mode, interrupts might still be enabled */
 813                 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
 814
 815                 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
 816                 tasklet_schedule(&host->finish_task);
 817         }
 818 #if 0
 819         else if (status & SD_STATUS_DD) {
 820                 /* Sometimes we get a DD before a NE in PIO mode */
 821                 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
 822                         au1xmmc_receive_pio(host);
 823                 else {
 824                         au1xmmc_data_complete(host, status);
 825                         /* tasklet_schedule(&host->data_task); */
 826                 }
 827         }
 828 #endif
 829         else if (status & SD_STATUS_CR) {
 830                 if (host->status == HOST_S_CMD)
 831                         au1xmmc_cmd_complete(host, status);
 832
 833         } else if (!(host->flags & HOST_F_DMA)) {
 834                 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
 835                         au1xmmc_send_pio(host);
 836                 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
 837                         au1xmmc_receive_pio(host);
 838
 839         } else if (status & 0x203F3C70) {
 840                         DBG("Unhandled status %8.8x\n", host->pdev->id,
 841                                 status);
 842         }
 843
 844         __raw_writel(status, HOST_STATUS(host));
 845         wmb(); /* drain writebuffer */
 846
 847         return IRQ_HANDLED;
 848 }
 849
 850 /* 8bit memory DMA device */
 851 static dbdev_tab_t au1xmmc_mem_dbdev = {
 852         .dev_id         = DSCR_CMD0_ALWAYS,
 853         .dev_flags      = DEV_FLAGS_ANYUSE,
 854         .dev_tsize      = 0,
 855         .dev_devwidth   = 8,
 856         .dev_physaddr   = 0x00000000,
 857         .dev_intlevel   = 0,
 858         .dev_intpolarity = 0,
 859 };
 860 static int memid;
 861
 862 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
 863 {
 864         struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
 865
 866         /* Avoid spurious interrupts */
 867         if (!host->mrq)
 868                 return;
 869
 870         if (host->flags & HOST_F_STOP)
 871                 SEND_STOP(host);
 872
 873         tasklet_schedule(&host->data_task);
 874 }
 875
 876 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
 877 {
 878         struct resource *res;
 879         int txid, rxid;
 880
 881         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
 882         if (!res)
 883                 return -ENODEV;
 884         txid = res->start;
 885
 886         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
 887         if (!res)
 888                 return -ENODEV;
 889         rxid = res->start;
 890
 891         if (!memid)
 892                 return -ENODEV;
 893
 894         host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
 895                                 au1xmmc_dbdma_callback, (void *)host);
 896         if (!host->tx_chan) {
 897                 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
 898                 return -ENODEV;
 899         }
 900
 901         host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
 902                                 au1xmmc_dbdma_callback, (void *)host);
 903         if (!host->rx_chan) {
 904                 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
 905                 au1xxx_dbdma_chan_free(host->tx_chan);
 906                 return -ENODEV;
 907         }
 908
 909         au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
 910         au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
 911
 912         au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 913         au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 914
 915         /* DBDMA is good to go */
 916         host->flags |= HOST_F_DMA | HOST_F_DBDMA;
 917
 918         return 0;
 919 }
 920
 921 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
 922 {
 923         if (host->flags & HOST_F_DMA) {
 924                 host->flags &= ~HOST_F_DMA;
 925                 au1xxx_dbdma_chan_free(host->tx_chan);
 926                 au1xxx_dbdma_chan_free(host->rx_chan);
 927         }
 928 }
 929
 930 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
 931 {
 932         struct au1xmmc_host *host = mmc_priv(mmc);
 933
 934         if (en)
 935                 IRQ_ON(host, SD_CONFIG_SI);
 936         else
 937                 IRQ_OFF(host, SD_CONFIG_SI);
 938 }
 939
 940 static const struct mmc_host_ops au1xmmc_ops = {
 941         .request        = au1xmmc_request,
 942         .set_ios        = au1xmmc_set_ios,
 943         .get_ro         = au1xmmc_card_readonly,
 944         .get_cd         = au1xmmc_card_inserted,
 945         .enable_sdio_irq = au1xmmc_enable_sdio_irq,
 946 };
 947
 948 static int au1xmmc_probe(struct platform_device *pdev)
 949 {
 950         struct mmc_host *mmc;
 951         struct au1xmmc_host *host;
 952         struct resource *r;
 953         int ret, iflag;
 954
 955         mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
 956         if (!mmc) {
 957                 dev_err(&pdev->dev, "no memory for mmc_host\n");
 958                 ret = -ENOMEM;
 959                 goto out0;
 960         }
 961
 962         host = mmc_priv(mmc);
 963         host->mmc = mmc;
 964         host->platdata = pdev->dev.platform_data;
 965         host->pdev = pdev;
 966
 967         ret = -ENODEV;
 968         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 969         if (!r) {
 970                 dev_err(&pdev->dev, "no mmio defined\n");
 971                 goto out1;
 972         }
 973
 974         host->ioarea = request_mem_region(r->start, resource_size(r),
 975                                            pdev->name);
 976         if (!host->ioarea) {
 977                 dev_err(&pdev->dev, "mmio already in use\n");
 978                 goto out1;
 979         }
 980
 981         host->iobase = ioremap(r->start, 0x3c);
 982         if (!host->iobase) {
 983                 dev_err(&pdev->dev, "cannot remap mmio\n");
 984                 goto out2;
 985         }
 986
 987         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 988         if (!r) {
 989                 dev_err(&pdev->dev, "no IRQ defined\n");
 990                 goto out3;
 991         }
 992         host->irq = r->start;
 993
 994         mmc->ops = &au1xmmc_ops;
 995
 996         mmc->f_min =   450000;
 997         mmc->f_max = 24000000;
 998
 999         mmc->max_blk_size = 2048;
1000         mmc->max_blk_count = 512;
1001
1002         mmc->ocr_avail = AU1XMMC_OCR;
1003         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1004         mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1005
1006         iflag = IRQF_SHARED;    /* Au1100/Au1200: one int for both ctrls */
1007
1008         switch (alchemy_get_cputype()) {
1009         case ALCHEMY_CPU_AU1100:
1010                 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
1011                 break;
1012         case ALCHEMY_CPU_AU1200:
1013                 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1014                 break;
1015         case ALCHEMY_CPU_AU1300:
1016                 iflag = 0;      /* nothing is shared */
1017                 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1018                 mmc->f_max = 52000000;
1019                 if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
1020                         mmc->caps |= MMC_CAP_8_BIT_DATA;
1021                 break;
1022         }
1023
1024         ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
1025         if (ret) {
1026                 dev_err(&pdev->dev, "cannot grab IRQ\n");
1027                 goto out3;
1028         }
1029
1030         host->clk = clk_get(&pdev->dev, ALCHEMY_PERIPH_CLK);
1031         if (IS_ERR(host->clk)) {
1032                 dev_err(&pdev->dev, "cannot find clock\n");
1033                 ret = PTR_ERR(host->clk);
1034                 goto out_irq;
1035         }
1036
1037         ret = clk_prepare_enable(host->clk);
1038         if (ret) {
1039                 dev_err(&pdev->dev, "cannot enable clock\n");
1040                 goto out_clk;
1041         }
1042
1043         host->status = HOST_S_IDLE;
1044
1045         /* board-specific carddetect setup, if any */
1046         if (host->platdata && host->platdata->cd_setup) {
1047                 ret = host->platdata->cd_setup(mmc, 1);
1048                 if (ret) {
1049                         dev_warn(&pdev->dev, "board CD setup failed\n");
1050                         mmc->caps |= MMC_CAP_NEEDS_POLL;
1051                 }
1052         } else
1053                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1054
1055         /* platform may not be able to use all advertised caps */
1056         if (host->platdata)
1057                 mmc->caps &= ~(host->platdata->mask_host_caps);
1058
1059         tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1060                         (unsigned long)host);
1061
1062         tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1063                         (unsigned long)host);
1064
1065         if (has_dbdma()) {
1066                 ret = au1xmmc_dbdma_init(host);
1067                 if (ret)
1068                         pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n");
1069         }
1070
1071 #ifdef CONFIG_LEDS_CLASS
1072         if (host->platdata && host->platdata->led) {
1073                 struct led_classdev *led = host->platdata->led;
1074                 led->name = mmc_hostname(mmc);
1075                 led->brightness = LED_OFF;
1076                 led->default_trigger = mmc_hostname(mmc);
1077                 ret = led_classdev_register(mmc_dev(mmc), led);
1078                 if (ret)
1079                         goto out5;
1080         }
1081 #endif
1082
1083         au1xmmc_reset_controller(host);
1084
1085         ret = mmc_add_host(mmc);
1086         if (ret) {
1087                 dev_err(&pdev->dev, "cannot add mmc host\n");
1088                 goto out6;
1089         }
1090
1091         platform_set_drvdata(pdev, host);
1092
1093         pr_info(DRIVER_NAME ": MMC Controller %d set up at %p"
1094                 " (mode=%s)\n", pdev->id, host->iobase,
1095                 host->flags & HOST_F_DMA ? "dma" : "pio");
1096
1097         return 0;       /* all ok */
1098
1099 out6:
1100 #ifdef CONFIG_LEDS_CLASS
1101         if (host->platdata && host->platdata->led)
1102                 led_classdev_unregister(host->platdata->led);
1103 out5:
1104 #endif
1105         __raw_writel(0, HOST_ENABLE(host));
1106         __raw_writel(0, HOST_CONFIG(host));
1107         __raw_writel(0, HOST_CONFIG2(host));
1108         wmb(); /* drain writebuffer */
1109
1110         if (host->flags & HOST_F_DBDMA)
1111                 au1xmmc_dbdma_shutdown(host);
1112
1113         tasklet_kill(&host->data_task);
1114         tasklet_kill(&host->finish_task);
1115
1116         if (host->platdata && host->platdata->cd_setup &&
1117             !(mmc->caps & MMC_CAP_NEEDS_POLL))
1118                 host->platdata->cd_setup(mmc, 0);
1119 out_clk:
1120         clk_disable_unprepare(host->clk);
1121         clk_put(host->clk);
1122 out_irq:
1123         free_irq(host->irq, host);
1124 out3:
1125         iounmap((void *)host->iobase);
1126 out2:
1127         release_resource(host->ioarea);
1128         kfree(host->ioarea);
1129 out1:
1130         mmc_free_host(mmc);
1131 out0:
1132         return ret;
1133 }
1134
1135 static int au1xmmc_remove(struct platform_device *pdev)
1136 {
1137         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1138
1139         if (host) {
1140                 mmc_remove_host(host->mmc);
1141
1142 #ifdef CONFIG_LEDS_CLASS
1143                 if (host->platdata && host->platdata->led)
1144                         led_classdev_unregister(host->platdata->led);
1145 #endif
1146
1147                 if (host->platdata && host->platdata->cd_setup &&
1148                     !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1149                         host->platdata->cd_setup(host->mmc, 0);
1150
1151                 __raw_writel(0, HOST_ENABLE(host));
1152                 __raw_writel(0, HOST_CONFIG(host));
1153                 __raw_writel(0, HOST_CONFIG2(host));
1154                 wmb(); /* drain writebuffer */
1155
1156                 tasklet_kill(&host->data_task);
1157                 tasklet_kill(&host->finish_task);
1158
1159                 if (host->flags & HOST_F_DBDMA)
1160                         au1xmmc_dbdma_shutdown(host);
1161
1162                 au1xmmc_set_power(host, 0);
1163
1164                 clk_disable_unprepare(host->clk);
1165                 clk_put(host->clk);
1166
1167                 free_irq(host->irq, host);
1168                 iounmap((void *)host->iobase);
1169                 release_resource(host->ioarea);
1170                 kfree(host->ioarea);
1171
1172                 mmc_free_host(host->mmc);
1173         }
1174         return 0;
1175 }
1176
1177 #ifdef CONFIG_PM
1178 static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1179 {
1180         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1181
1182         __raw_writel(0, HOST_CONFIG2(host));
1183         __raw_writel(0, HOST_CONFIG(host));
1184         __raw_writel(0xffffffff, HOST_STATUS(host));
1185         __raw_writel(0, HOST_ENABLE(host));
1186         wmb(); /* drain writebuffer */
1187
1188         return 0;
1189 }
1190
1191 static int au1xmmc_resume(struct platform_device *pdev)
1192 {
1193         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1194
1195         au1xmmc_reset_controller(host);
1196
1197         return 0;
1198 }
1199 #else
1200 #define au1xmmc_suspend NULL
1201 #define au1xmmc_resume NULL
1202 #endif
1203
1204 static struct platform_driver au1xmmc_driver = {
1205         .probe         = au1xmmc_probe,
1206         .remove        = au1xmmc_remove,
1207         .suspend       = au1xmmc_suspend,
1208         .resume        = au1xmmc_resume,
1209         .driver        = {
1210                 .name  = DRIVER_NAME,
1211         },
1212 };
1213
1214 static int __init au1xmmc_init(void)
1215 {
1216         if (has_dbdma()) {
1217                 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1218                 * of 8 bits.  And since devices are shared, we need to create
1219                 * our own to avoid freaking out other devices.
1220                 */
1221                 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1222                 if (!memid)
1223                         pr_err("au1xmmc: cannot add memory dbdma\n");
1224         }
1225         return platform_driver_register(&au1xmmc_driver);
1226 }
1227
1228 static void __exit au1xmmc_exit(void)
1229 {
1230         if (has_dbdma() && memid)
1231                 au1xxx_ddma_del_device(memid);
1232
1233         platform_driver_unregister(&au1xmmc_driver);
1234 }
1235
1236 module_init(au1xmmc_init);
1237 module_exit(au1xmmc_exit);
1238
1239 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1240 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1241 MODULE_LICENSE("GPL");
1242 MODULE_ALIAS("platform:au1xxx-mmc");