drivers/misc/mei/pci-me.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
   4  * Intel Management Engine Interface (Intel MEI) Linux driver
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/kernel.h>
   9 #include <linux/device.h>
  10 #include <linux/errno.h>
  11 #include <linux/types.h>
  12 #include <linux/pci.h>
  13 #include <linux/sched.h>
  14 #include <linux/interrupt.h>
  15
  16 #include <linux/pm_domain.h>
  17 #include <linux/pm_runtime.h>
  18
  19 #include <linux/mei.h>
  20
  21 #include "mei_dev.h"
  22 #include "client.h"
  23 #include "hw-me-regs.h"
  24 #include "hw-me.h"
  25
  26 /* mei_pci_tbl - PCI Device ID Table */
  27 static const struct pci_device_id mei_me_pci_tbl[] = {
  28         {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
  29         {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
  30         {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
  31         {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
  32         {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
  33         {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
  34         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
  35         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
  36         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
  37         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
  38         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
  39
  40         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
  41         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
  42         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
  43         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
  44         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
  45         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
  46         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
  47         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
  48         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
  49
  50         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
  51         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
  52         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
  53         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
  54
  55         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
  56         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
  57         {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
  58         {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
  59         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
  60         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
  61         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
  62         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
  63         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
  64         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
  65         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
  66         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
  67         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
  68
  69         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  70         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  71         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
  72         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
  73         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
  74         {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
  75
  76         {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
  77         {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
  78
  79         {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
  80
  81         {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
  82
  83         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
  84         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
  85         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
  86
  87         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
  88         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
  89         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
  90         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
  91
  92         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
  93         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
  94         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
  95         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
  96         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
  97
  98         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
  99
 100         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
 101         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
 102
 103         {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
 104
 105         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
 106         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
 107
 108         {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
 109
 110         /* required last entry */
 111         {0, }
 112 };
 113
 114 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
 115
 116 #ifdef CONFIG_PM
 117 static inline void mei_me_set_pm_domain(struct mei_device *dev);
 118 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
 119 #else
 120 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
 121 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
 122 #endif /* CONFIG_PM */
 123
 124 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
 125 {
 126         struct pci_dev *pdev = to_pci_dev(dev->dev);
 127
 128         return pci_read_config_dword(pdev, where, val);
 129 }
 130
 131 /**
 132  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 133  *
 134  * @pdev: PCI device structure
 135  * @cfg: per generation config
 136  *
 137  * Return: true if ME Interface is valid, false otherwise
 138  */
 139 static bool mei_me_quirk_probe(struct pci_dev *pdev,
 140                                 const struct mei_cfg *cfg)
 141 {
 142         if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
 143                 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
 144                 return false;
 145         }
 146
 147         return true;
 148 }
 149
 150 /**
 151  * mei_me_probe - Device Initialization Routine
 152  *
 153  * @pdev: PCI device structure
 154  * @ent: entry in kcs_pci_tbl
 155  *
 156  * Return: 0 on success, <0 on failure.
 157  */
 158 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 159 {
 160         const struct mei_cfg *cfg;
 161         struct mei_device *dev;
 162         struct mei_me_hw *hw;
 163         unsigned int irqflags;
 164         int err;
 165
 166         cfg = mei_me_get_cfg(ent->driver_data);
 167         if (!cfg)
 168                 return -ENODEV;
 169
 170         if (!mei_me_quirk_probe(pdev, cfg))
 171                 return -ENODEV;
 172
 173         /* enable pci dev */
 174         err = pcim_enable_device(pdev);
 175         if (err) {
 176                 dev_err(&pdev->dev, "failed to enable pci device.\n");
 177                 goto end;
 178         }
 179         /* set PCI host mastering  */
 180         pci_set_master(pdev);
 181         /* pci request regions and mapping IO device memory for mei driver */
 182         err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
 183         if (err) {
 184                 dev_err(&pdev->dev, "failed to get pci regions.\n");
 185                 goto end;
 186         }
 187
 188         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
 189             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
 190
 191                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 192                 if (err)
 193                         err = dma_set_coherent_mask(&pdev->dev,
 194                                                     DMA_BIT_MASK(32));
 195         }
 196         if (err) {
 197                 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
 198                 goto end;
 199         }
 200
 201         /* allocates and initializes the mei dev structure */
 202         dev = mei_me_dev_init(&pdev->dev, cfg);
 203         if (!dev) {
 204                 err = -ENOMEM;
 205                 goto end;
 206         }
 207         hw = to_me_hw(dev);
 208         hw->mem_addr = pcim_iomap_table(pdev)[0];
 209         hw->read_fws = mei_me_read_fws;
 210
 211         pci_enable_msi(pdev);
 212
 213         hw->irq = pdev->irq;
 214
 215          /* request and enable interrupt */
 216         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 217
 218         err = request_threaded_irq(pdev->irq,
 219                         mei_me_irq_quick_handler,
 220                         mei_me_irq_thread_handler,
 221                         irqflags, KBUILD_MODNAME, dev);
 222         if (err) {
 223                 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
 224                        pdev->irq);
 225                 goto end;
 226         }
 227
 228         if (mei_start(dev)) {
 229                 dev_err(&pdev->dev, "init hw failure.\n");
 230                 err = -ENODEV;
 231                 goto release_irq;
 232         }
 233
 234         pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
 235         pm_runtime_use_autosuspend(&pdev->dev);
 236
 237         err = mei_register(dev, &pdev->dev);
 238         if (err)
 239                 goto stop;
 240
 241         pci_set_drvdata(pdev, dev);
 242
 243         /*
 244          * MEI requires to resume from runtime suspend mode
 245          * in order to perform link reset flow upon system suspend.
 246          */
 247         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 248
 249         /*
 250          * ME maps runtime suspend/resume to D0i states,
 251          * hence we need to go around native PCI runtime service which
 252          * eventually brings the device into D3cold/hot state,
 253          * but the mei device cannot wake up from D3 unlike from D0i3.
 254          * To get around the PCI device native runtime pm,
 255          * ME uses runtime pm domain handlers which take precedence
 256          * over the driver's pm handlers.
 257          */
 258         mei_me_set_pm_domain(dev);
 259
 260         if (mei_pg_is_enabled(dev)) {
 261                 pm_runtime_put_noidle(&pdev->dev);
 262                 if (hw->d0i3_supported)
 263                         pm_runtime_allow(&pdev->dev);
 264         }
 265
 266         dev_dbg(&pdev->dev, "initialization successful.\n");
 267
 268         return 0;
 269
 270 stop:
 271         mei_stop(dev);
 272 release_irq:
 273         mei_cancel_work(dev);
 274         mei_disable_interrupts(dev);
 275         free_irq(pdev->irq, dev);
 276 end:
 277         dev_err(&pdev->dev, "initialization failed.\n");
 278         return err;
 279 }
 280
 281 /**
 282  * mei_me_shutdown - Device Removal Routine
 283  *
 284  * @pdev: PCI device structure
 285  *
 286  * mei_me_shutdown is called from the reboot notifier
 287  * it's a simplified version of remove so we go down
 288  * faster.
 289  */
 290 static void mei_me_shutdown(struct pci_dev *pdev)
 291 {
 292         struct mei_device *dev;
 293
 294         dev = pci_get_drvdata(pdev);
 295         if (!dev)
 296                 return;
 297
 298         dev_dbg(&pdev->dev, "shutdown\n");
 299         mei_stop(dev);
 300
 301         mei_me_unset_pm_domain(dev);
 302
 303         mei_disable_interrupts(dev);
 304         free_irq(pdev->irq, dev);
 305 }
 306
 307 /**
 308  * mei_me_remove - Device Removal Routine
 309  *
 310  * @pdev: PCI device structure
 311  *
 312  * mei_me_remove is called by the PCI subsystem to alert the driver
 313  * that it should release a PCI device.
 314  */
 315 static void mei_me_remove(struct pci_dev *pdev)
 316 {
 317         struct mei_device *dev;
 318
 319         dev = pci_get_drvdata(pdev);
 320         if (!dev)
 321                 return;
 322
 323         if (mei_pg_is_enabled(dev))
 324                 pm_runtime_get_noresume(&pdev->dev);
 325
 326         dev_dbg(&pdev->dev, "stop\n");
 327         mei_stop(dev);
 328
 329         mei_me_unset_pm_domain(dev);
 330
 331         mei_disable_interrupts(dev);
 332
 333         free_irq(pdev->irq, dev);
 334
 335         mei_deregister(dev);
 336 }
 337
 338 #ifdef CONFIG_PM_SLEEP
 339 static int mei_me_pci_suspend(struct device *device)
 340 {
 341         struct pci_dev *pdev = to_pci_dev(device);
 342         struct mei_device *dev = pci_get_drvdata(pdev);
 343
 344         if (!dev)
 345                 return -ENODEV;
 346
 347         dev_dbg(&pdev->dev, "suspend\n");
 348
 349         mei_stop(dev);
 350
 351         mei_disable_interrupts(dev);
 352
 353         free_irq(pdev->irq, dev);
 354         pci_disable_msi(pdev);
 355
 356         return 0;
 357 }
 358
 359 static int mei_me_pci_resume(struct device *device)
 360 {
 361         struct pci_dev *pdev = to_pci_dev(device);
 362         struct mei_device *dev;
 363         unsigned int irqflags;
 364         int err;
 365
 366         dev = pci_get_drvdata(pdev);
 367         if (!dev)
 368                 return -ENODEV;
 369
 370         pci_enable_msi(pdev);
 371
 372         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 373
 374         /* request and enable interrupt */
 375         err = request_threaded_irq(pdev->irq,
 376                         mei_me_irq_quick_handler,
 377                         mei_me_irq_thread_handler,
 378                         irqflags, KBUILD_MODNAME, dev);
 379
 380         if (err) {
 381                 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
 382                                 pdev->irq);
 383                 return err;
 384         }
 385
 386         err = mei_restart(dev);
 387         if (err)
 388                 return err;
 389
 390         /* Start timer if stopped in suspend */
 391         schedule_delayed_work(&dev->timer_work, HZ);
 392
 393         return 0;
 394 }
 395 #endif /* CONFIG_PM_SLEEP */
 396
 397 #ifdef CONFIG_PM
 398 static int mei_me_pm_runtime_idle(struct device *device)
 399 {
 400         struct mei_device *dev;
 401
 402         dev_dbg(device, "rpm: me: runtime_idle\n");
 403
 404         dev = dev_get_drvdata(device);
 405         if (!dev)
 406                 return -ENODEV;
 407         if (mei_write_is_idle(dev))
 408                 pm_runtime_autosuspend(device);
 409
 410         return -EBUSY;
 411 }
 412
 413 static int mei_me_pm_runtime_suspend(struct device *device)
 414 {
 415         struct mei_device *dev;
 416         int ret;
 417
 418         dev_dbg(device, "rpm: me: runtime suspend\n");
 419
 420         dev = dev_get_drvdata(device);
 421         if (!dev)
 422                 return -ENODEV;
 423
 424         mutex_lock(&dev->device_lock);
 425
 426         if (mei_write_is_idle(dev))
 427                 ret = mei_me_pg_enter_sync(dev);
 428         else
 429                 ret = -EAGAIN;
 430
 431         mutex_unlock(&dev->device_lock);
 432
 433         dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
 434
 435         if (ret && ret != -EAGAIN)
 436                 schedule_work(&dev->reset_work);
 437
 438         return ret;
 439 }
 440
 441 static int mei_me_pm_runtime_resume(struct device *device)
 442 {
 443         struct mei_device *dev;
 444         int ret;
 445
 446         dev_dbg(device, "rpm: me: runtime resume\n");
 447
 448         dev = dev_get_drvdata(device);
 449         if (!dev)
 450                 return -ENODEV;
 451
 452         mutex_lock(&dev->device_lock);
 453
 454         ret = mei_me_pg_exit_sync(dev);
 455
 456         mutex_unlock(&dev->device_lock);
 457
 458         dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
 459
 460         if (ret)
 461                 schedule_work(&dev->reset_work);
 462
 463         return ret;
 464 }
 465
 466 /**
 467  * mei_me_set_pm_domain - fill and set pm domain structure for device
 468  *
 469  * @dev: mei_device
 470  */
 471 static inline void mei_me_set_pm_domain(struct mei_device *dev)
 472 {
 473         struct pci_dev *pdev  = to_pci_dev(dev->dev);
 474
 475         if (pdev->dev.bus && pdev->dev.bus->pm) {
 476                 dev->pg_domain.ops = *pdev->dev.bus->pm;
 477
 478                 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
 479                 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
 480                 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
 481
 482                 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
 483         }
 484 }
 485
 486 /**
 487  * mei_me_unset_pm_domain - clean pm domain structure for device
 488  *
 489  * @dev: mei_device
 490  */
 491 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
 492 {
 493         /* stop using pm callbacks if any */
 494         dev_pm_domain_set(dev->dev, NULL);
 495 }
 496
 497 static const struct dev_pm_ops mei_me_pm_ops = {
 498         SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
 499                                 mei_me_pci_resume)
 500         SET_RUNTIME_PM_OPS(
 501                 mei_me_pm_runtime_suspend,
 502                 mei_me_pm_runtime_resume,
 503                 mei_me_pm_runtime_idle)
 504 };
 505
 506 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
 507 #else
 508 #define MEI_ME_PM_OPS   NULL
 509 #endif /* CONFIG_PM */
 510 /*
 511  *  PCI driver structure
 512  */
 513 static struct pci_driver mei_me_driver = {
 514         .name = KBUILD_MODNAME,
 515         .id_table = mei_me_pci_tbl,
 516         .probe = mei_me_probe,
 517         .remove = mei_me_remove,
 518         .shutdown = mei_me_shutdown,
 519         .driver.pm = MEI_ME_PM_OPS,
 520         .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 521 };
 522
 523 module_pci_driver(mei_me_driver);
 524
 525 MODULE_AUTHOR("Intel Corporation");
 526 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
 527 MODULE_LICENSE("GPL v2");