1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
7 #include <linux/module.h>
8 #include <linux/moduleparam.h>
9 #include <linux/kernel.h>
10 #include <linux/device.h>
12 #include <linux/errno.h>
13 #include <linux/types.h>
14 #include <linux/fcntl.h>
15 #include <linux/pci.h>
16 #include <linux/poll.h>
17 #include <linux/ioctl.h>
18 #include <linux/cdev.h>
19 #include <linux/sched.h>
20 #include <linux/uuid.h>
21 #include <linux/compat.h>
22 #include <linux/jiffies.h>
23 #include <linux/interrupt.h>
25 #include <linux/pm_domain.h>
26 #include <linux/pm_runtime.h>
28 #include <linux/mei.h>
32 #include "hw-me-regs.h"
35 /* mei_pci_tbl - PCI Device ID Table */
36 static const struct pci_device_id mei_me_pci_tbl[] = {
37 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
38 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
39 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
40 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
41 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
42 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
50 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
56 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
57 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH_CFG)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH_CFG)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
67 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH_CFG)},
69 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH_CFG)},
70 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH_CFG)},
71 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
72 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
76 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
79 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
80 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
81 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
82 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},
84 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
85 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
87 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
89 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
91 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
92 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
94 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
95 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
96 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)},
97 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},
99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
101 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH12_CFG)},
102 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
104 /* required last entry */
108 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
111 static inline void mei_me_set_pm_domain(struct mei_device *dev);
112 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
114 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
115 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
116 #endif /* CONFIG_PM */
119 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
121 * @pdev: PCI device structure
122 * @cfg: per generation config
124 * Return: true if ME Interface is valid, false otherwise
126 static bool mei_me_quirk_probe(struct pci_dev *pdev,
127 const struct mei_cfg *cfg)
129 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
130 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
138 * mei_me_probe - Device Initialization Routine
140 * @pdev: PCI device structure
141 * @ent: entry in kcs_pci_tbl
143 * Return: 0 on success, <0 on failure.
145 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
147 const struct mei_cfg *cfg;
148 struct mei_device *dev;
149 struct mei_me_hw *hw;
150 unsigned int irqflags;
153 cfg = mei_me_get_cfg(ent->driver_data);
157 if (!mei_me_quirk_probe(pdev, cfg))
161 err = pcim_enable_device(pdev);
163 dev_err(&pdev->dev, "failed to enable pci device.\n");
166 /* set PCI host mastering */
167 pci_set_master(pdev);
168 /* pci request regions and mapping IO device memory for mei driver */
169 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
171 dev_err(&pdev->dev, "failed to get pci regions.\n");
175 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
176 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
178 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
180 err = dma_set_coherent_mask(&pdev->dev,
184 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
188 /* allocates and initializes the mei dev structure */
189 dev = mei_me_dev_init(pdev, cfg);
195 hw->mem_addr = pcim_iomap_table(pdev)[0];
197 pci_enable_msi(pdev);
199 /* request and enable interrupt */
200 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
202 err = request_threaded_irq(pdev->irq,
203 mei_me_irq_quick_handler,
204 mei_me_irq_thread_handler,
205 irqflags, KBUILD_MODNAME, dev);
207 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
212 if (mei_start(dev)) {
213 dev_err(&pdev->dev, "init hw failure.\n");
218 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
219 pm_runtime_use_autosuspend(&pdev->dev);
221 err = mei_register(dev, &pdev->dev);
225 pci_set_drvdata(pdev, dev);
228 * MEI requires to resume from runtime suspend mode
229 * in order to perform link reset flow upon system suspend.
231 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
234 * ME maps runtime suspend/resume to D0i states,
235 * hence we need to go around native PCI runtime service which
236 * eventually brings the device into D3cold/hot state,
237 * but the mei device cannot wake up from D3 unlike from D0i3.
238 * To get around the PCI device native runtime pm,
239 * ME uses runtime pm domain handlers which take precedence
240 * over the driver's pm handlers.
242 mei_me_set_pm_domain(dev);
244 if (mei_pg_is_enabled(dev)) {
245 pm_runtime_put_noidle(&pdev->dev);
246 if (hw->d0i3_supported)
247 pm_runtime_allow(&pdev->dev);
250 dev_dbg(&pdev->dev, "initialization successful.\n");
257 mei_cancel_work(dev);
258 mei_disable_interrupts(dev);
259 free_irq(pdev->irq, dev);
261 dev_err(&pdev->dev, "initialization failed.\n");
266 * mei_me_shutdown - Device Removal Routine
268 * @pdev: PCI device structure
270 * mei_me_shutdown is called from the reboot notifier
271 * it's a simplified version of remove so we go down
274 static void mei_me_shutdown(struct pci_dev *pdev)
276 struct mei_device *dev;
278 dev = pci_get_drvdata(pdev);
282 dev_dbg(&pdev->dev, "shutdown\n");
285 mei_me_unset_pm_domain(dev);
287 mei_disable_interrupts(dev);
288 free_irq(pdev->irq, dev);
292 * mei_me_remove - Device Removal Routine
294 * @pdev: PCI device structure
296 * mei_me_remove is called by the PCI subsystem to alert the driver
297 * that it should release a PCI device.
299 static void mei_me_remove(struct pci_dev *pdev)
301 struct mei_device *dev;
303 dev = pci_get_drvdata(pdev);
307 if (mei_pg_is_enabled(dev))
308 pm_runtime_get_noresume(&pdev->dev);
310 dev_dbg(&pdev->dev, "stop\n");
313 mei_me_unset_pm_domain(dev);
315 mei_disable_interrupts(dev);
317 free_irq(pdev->irq, dev);
322 #ifdef CONFIG_PM_SLEEP
323 static int mei_me_pci_suspend(struct device *device)
325 struct pci_dev *pdev = to_pci_dev(device);
326 struct mei_device *dev = pci_get_drvdata(pdev);
331 dev_dbg(&pdev->dev, "suspend\n");
335 mei_disable_interrupts(dev);
337 free_irq(pdev->irq, dev);
338 pci_disable_msi(pdev);
343 static int mei_me_pci_resume(struct device *device)
345 struct pci_dev *pdev = to_pci_dev(device);
346 struct mei_device *dev;
347 unsigned int irqflags;
350 dev = pci_get_drvdata(pdev);
354 pci_enable_msi(pdev);
356 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
358 /* request and enable interrupt */
359 err = request_threaded_irq(pdev->irq,
360 mei_me_irq_quick_handler,
361 mei_me_irq_thread_handler,
362 irqflags, KBUILD_MODNAME, dev);
365 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
370 err = mei_restart(dev);
374 /* Start timer if stopped in suspend */
375 schedule_delayed_work(&dev->timer_work, HZ);
379 #endif /* CONFIG_PM_SLEEP */
382 static int mei_me_pm_runtime_idle(struct device *device)
384 struct pci_dev *pdev = to_pci_dev(device);
385 struct mei_device *dev;
387 dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
389 dev = pci_get_drvdata(pdev);
392 if (mei_write_is_idle(dev))
393 pm_runtime_autosuspend(device);
398 static int mei_me_pm_runtime_suspend(struct device *device)
400 struct pci_dev *pdev = to_pci_dev(device);
401 struct mei_device *dev;
404 dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
406 dev = pci_get_drvdata(pdev);
410 mutex_lock(&dev->device_lock);
412 if (mei_write_is_idle(dev))
413 ret = mei_me_pg_enter_sync(dev);
417 mutex_unlock(&dev->device_lock);
419 dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
421 if (ret && ret != -EAGAIN)
422 schedule_work(&dev->reset_work);
427 static int mei_me_pm_runtime_resume(struct device *device)
429 struct pci_dev *pdev = to_pci_dev(device);
430 struct mei_device *dev;
433 dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
435 dev = pci_get_drvdata(pdev);
439 mutex_lock(&dev->device_lock);
441 ret = mei_me_pg_exit_sync(dev);
443 mutex_unlock(&dev->device_lock);
445 dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
448 schedule_work(&dev->reset_work);
454 * mei_me_set_pm_domain - fill and set pm domain structure for device
458 static inline void mei_me_set_pm_domain(struct mei_device *dev)
460 struct pci_dev *pdev = to_pci_dev(dev->dev);
462 if (pdev->dev.bus && pdev->dev.bus->pm) {
463 dev->pg_domain.ops = *pdev->dev.bus->pm;
465 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
466 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
467 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
469 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
474 * mei_me_unset_pm_domain - clean pm domain structure for device
478 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
480 /* stop using pm callbacks if any */
481 dev_pm_domain_set(dev->dev, NULL);
484 static const struct dev_pm_ops mei_me_pm_ops = {
485 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
488 mei_me_pm_runtime_suspend,
489 mei_me_pm_runtime_resume,
490 mei_me_pm_runtime_idle)
493 #define MEI_ME_PM_OPS (&mei_me_pm_ops)
495 #define MEI_ME_PM_OPS NULL
496 #endif /* CONFIG_PM */
498 * PCI driver structure
500 static struct pci_driver mei_me_driver = {
501 .name = KBUILD_MODNAME,
502 .id_table = mei_me_pci_tbl,
503 .probe = mei_me_probe,
504 .remove = mei_me_remove,
505 .shutdown = mei_me_shutdown,
506 .driver.pm = MEI_ME_PM_OPS,
507 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
510 module_pci_driver(mei_me_driver);
512 MODULE_AUTHOR("Intel Corporation");
513 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
514 MODULE_LICENSE("GPL v2");