1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2020 HabanaLabs, Ltd.
11 #include "asic_reg/gaudi_regs.h"
13 /* Useful masks for bits in various registers */
14 #define PCI_DMA_QMAN_ENABLE (\
15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
19 #define QMAN_EXTERNAL_MAKE_TRUSTED (\
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
25 #define QMAN_INTERNAL_MAKE_TRUSTED (\
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
29 #define HBM_DMA_QMAN_ENABLE (\
30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
31 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
32 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
34 #define QMAN_MME_ENABLE (\
35 (FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
36 (FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
37 (FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
39 #define QMAN_TPC_ENABLE (\
40 (FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
41 (FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
42 (FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
44 #define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\
45 (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
46 (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
47 (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \
48 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
50 #define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\
51 (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
52 (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
53 (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \
54 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
56 #define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
57 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
58 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
59 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
61 #define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
62 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
63 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
64 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)))
66 #define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
67 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
68 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
69 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
71 #define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
72 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
73 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
74 (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))
76 #define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
77 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
78 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
79 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
81 #define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
82 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
83 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
84 (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))
86 #define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
87 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
88 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
89 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
91 #define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
92 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
93 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
94 (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))
96 #define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA))
98 /* RESET registers configuration */
99 #define CFG_RST_L_PSOC_MASK BIT_MASK(0)
100 #define CFG_RST_L_PCIE_MASK BIT_MASK(1)
101 #define CFG_RST_L_PCIE_IF_MASK BIT_MASK(2)
102 #define CFG_RST_L_HBM_S_PLL_MASK BIT_MASK(3)
103 #define CFG_RST_L_TPC_S_PLL_MASK BIT_MASK(4)
104 #define CFG_RST_L_MME_S_PLL_MASK BIT_MASK(5)
105 #define CFG_RST_L_CPU_PLL_MASK BIT_MASK(6)
106 #define CFG_RST_L_PCIE_PLL_MASK BIT_MASK(7)
107 #define CFG_RST_L_NIC_S_PLL_MASK BIT_MASK(8)
108 #define CFG_RST_L_HBM_N_PLL_MASK BIT_MASK(9)
109 #define CFG_RST_L_TPC_N_PLL_MASK BIT_MASK(10)
110 #define CFG_RST_L_MME_N_PLL_MASK BIT_MASK(11)
111 #define CFG_RST_L_NIC_N_PLL_MASK BIT_MASK(12)
112 #define CFG_RST_L_DMA_W_PLL_MASK BIT_MASK(13)
113 #define CFG_RST_L_SIF_W_PLL_MASK BIT_MASK(14)
114 #define CFG_RST_L_MESH_W_PLL_MASK BIT_MASK(15)
115 #define CFG_RST_L_SRAM_W_PLL_MASK BIT_MASK(16)
116 #define CFG_RST_L_DMA_E_PLL_MASK BIT_MASK(17)
117 #define CFG_RST_L_SIF_E_PLL_MASK BIT_MASK(18)
118 #define CFG_RST_L_MESH_E_PLL_MASK BIT_MASK(19)
119 #define CFG_RST_L_SRAM_E_PLL_MASK BIT_MASK(20)
121 #define CFG_RST_L_IF_1_MASK BIT_MASK(21)
122 #define CFG_RST_L_IF_0_MASK BIT_MASK(22)
123 #define CFG_RST_L_IF_2_MASK BIT_MASK(23)
124 #define CFG_RST_L_IF_3_MASK BIT_MASK(24)
125 #define CFG_RST_L_IF_MASK GENMASK(24, 21)
127 #define CFG_RST_L_TPC_0_MASK BIT_MASK(25)
128 #define CFG_RST_L_TPC_1_MASK BIT_MASK(26)
129 #define CFG_RST_L_TPC_2_MASK BIT_MASK(27)
130 #define CFG_RST_L_TPC_3_MASK BIT_MASK(28)
131 #define CFG_RST_L_TPC_4_MASK BIT_MASK(29)
132 #define CFG_RST_L_TPC_5_MASK BIT_MASK(30)
133 #define CFG_RST_L_TPC_6_MASK BIT_MASK(31)
134 #define CFG_RST_L_TPC_MASK GENMASK(31, 25)
136 #define CFG_RST_H_TPC_7_MASK BIT_MASK(0)
138 #define CFG_RST_H_MME_0_MASK BIT_MASK(1)
139 #define CFG_RST_H_MME_1_MASK BIT_MASK(2)
140 #define CFG_RST_H_MME_2_MASK BIT_MASK(3)
141 #define CFG_RST_H_MME_3_MASK BIT_MASK(4)
142 #define CFG_RST_H_MME_MASK GENMASK(4, 1)
144 #define CFG_RST_H_HBM_0_MASK BIT_MASK(5)
145 #define CFG_RST_H_HBM_1_MASK BIT_MASK(6)
146 #define CFG_RST_H_HBM_2_MASK BIT_MASK(7)
147 #define CFG_RST_H_HBM_3_MASK BIT_MASK(8)
148 #define CFG_RST_H_HBM_MASK GENMASK(8, 5)
150 #define CFG_RST_H_NIC_0_MASK BIT_MASK(9)
151 #define CFG_RST_H_NIC_1_MASK BIT_MASK(10)
152 #define CFG_RST_H_NIC_2_MASK BIT_MASK(11)
153 #define CFG_RST_H_NIC_3_MASK BIT_MASK(12)
154 #define CFG_RST_H_NIC_4_MASK BIT_MASK(13)
155 #define CFG_RST_H_NIC_MASK GENMASK(13, 9)
157 #define CFG_RST_H_SM_0_MASK BIT_MASK(14)
158 #define CFG_RST_H_SM_1_MASK BIT_MASK(15)
159 #define CFG_RST_H_SM_2_MASK BIT_MASK(16)
160 #define CFG_RST_H_SM_3_MASK BIT_MASK(17)
161 #define CFG_RST_H_SM_MASK GENMASK(17, 14)
163 #define CFG_RST_H_DMA_0_MASK BIT_MASK(18)
164 #define CFG_RST_H_DMA_1_MASK BIT_MASK(19)
165 #define CFG_RST_H_DMA_MASK GENMASK(19, 18)
167 #define CFG_RST_H_CPU_MASK BIT_MASK(20)
168 #define CFG_RST_H_MMU_MASK BIT_MASK(21)
170 #define UNIT_RST_L_PSOC_SHIFT 0
171 #define UNIT_RST_L_PCIE_SHIFT 1
172 #define UNIT_RST_L_PCIE_IF_SHIFT 2
173 #define UNIT_RST_L_HBM_S_PLL_SHIFT 3
174 #define UNIT_RST_L_TPC_S_PLL_SHIFT 4
175 #define UNIT_RST_L_MME_S_PLL_SHIFT 5
176 #define UNIT_RST_L_CPU_PLL_SHIFT 6
177 #define UNIT_RST_L_PCIE_PLL_SHIFT 7
178 #define UNIT_RST_L_NIC_S_PLL_SHIFT 8
179 #define UNIT_RST_L_HBM_N_PLL_SHIFT 9
180 #define UNIT_RST_L_TPC_N_PLL_SHIFT 10
181 #define UNIT_RST_L_MME_N_PLL_SHIFT 11
182 #define UNIT_RST_L_NIC_N_PLL_SHIFT 12
183 #define UNIT_RST_L_DMA_W_PLL_SHIFT 13
184 #define UNIT_RST_L_SIF_W_PLL_SHIFT 14
185 #define UNIT_RST_L_MESH_W_PLL_SHIFT 15
186 #define UNIT_RST_L_SRAM_W_PLL_SHIFT 16
187 #define UNIT_RST_L_DMA_E_PLL_SHIFT 17
188 #define UNIT_RST_L_SIF_E_PLL_SHIFT 18
189 #define UNIT_RST_L_MESH_E_PLL_SHIFT 19
190 #define UNIT_RST_L_SRAM_E_PLL_SHIFT 20
191 #define UNIT_RST_L_TPC_0_SHIFT 21
192 #define UNIT_RST_L_TPC_1_SHIFT 22
193 #define UNIT_RST_L_TPC_2_SHIFT 23
194 #define UNIT_RST_L_TPC_3_SHIFT 24
195 #define UNIT_RST_L_TPC_4_SHIFT 25
196 #define UNIT_RST_L_TPC_5_SHIFT 26
197 #define UNIT_RST_L_TPC_6_SHIFT 27
198 #define UNIT_RST_L_TPC_7_SHIFT 28
199 #define UNIT_RST_L_MME_0_SHIFT 29
200 #define UNIT_RST_L_MME_1_SHIFT 30
201 #define UNIT_RST_L_MME_2_SHIFT 31
203 #define UNIT_RST_H_MME_3_SHIFT 0
204 #define UNIT_RST_H_HBM_0_SHIFT 1
205 #define UNIT_RST_H_HBM_1_SHIFT 2
206 #define UNIT_RST_H_HBM_2_SHIFT 3
207 #define UNIT_RST_H_HBM_3_SHIFT 4
208 #define UNIT_RST_H_NIC_0_SHIFT 5
209 #define UNIT_RST_H_NIC_1_SHIFT 6
210 #define UNIT_RST_H_NIC_2_SHIFT 7
211 #define UNIT_RST_H_NIC_3_SHIFT 8
212 #define UNIT_RST_H_NIC_4_SHIFT 9
213 #define UNIT_RST_H_SM_0_SHIFT 10
214 #define UNIT_RST_H_SM_1_SHIFT 11
215 #define UNIT_RST_H_SM_2_SHIFT 12
216 #define UNIT_RST_H_SM_3_SHIFT 13
217 #define UNIT_RST_H_IF_0_SHIFT 14
218 #define UNIT_RST_H_IF_1_SHIFT 15
219 #define UNIT_RST_H_IF_2_SHIFT 16
220 #define UNIT_RST_H_IF_3_SHIFT 17
221 #define UNIT_RST_H_DMA_0_SHIFT 18
222 #define UNIT_RST_H_DMA_1_SHIFT 19
223 #define UNIT_RST_H_CPU_SHIFT 20
224 #define UNIT_RST_H_MMU_SHIFT 21
226 #define UNIT_RST_H_HBM_MASK ((1 << UNIT_RST_H_HBM_0_SHIFT) | \
227 (1 << UNIT_RST_H_HBM_1_SHIFT) | \
228 (1 << UNIT_RST_H_HBM_2_SHIFT) | \
229 (1 << UNIT_RST_H_HBM_3_SHIFT))
231 #define UNIT_RST_H_NIC_MASK ((1 << UNIT_RST_H_NIC_0_SHIFT) | \
232 (1 << UNIT_RST_H_NIC_1_SHIFT) | \
233 (1 << UNIT_RST_H_NIC_2_SHIFT) | \
234 (1 << UNIT_RST_H_NIC_3_SHIFT) | \
235 (1 << UNIT_RST_H_NIC_4_SHIFT))
237 #define UNIT_RST_H_SM_MASK ((1 << UNIT_RST_H_SM_0_SHIFT) | \
238 (1 << UNIT_RST_H_SM_1_SHIFT) | \
239 (1 << UNIT_RST_H_SM_2_SHIFT) | \
240 (1 << UNIT_RST_H_SM_3_SHIFT))
242 #define UNIT_RST_H_MME_MASK ((1 << UNIT_RST_H_MME_0_SHIFT) | \
243 (1 << UNIT_RST_H_MME_1_SHIFT) | \
244 (1 << UNIT_RST_H_MME_2_SHIFT))
246 #define UNIT_RST_L_MME_MASK (1 << UNIT_RST_L_MME_3_SHIFT)
248 #define UNIT_RST_L_IF_MASK ((1 << UNIT_RST_L_IF_0_SHIFT) | \
249 (1 << UNIT_RST_L_IF_1_SHIFT) | \
250 (1 << UNIT_RST_L_IF_2_SHIFT) | \
251 (1 << UNIT_RST_L_IF_3_SHIFT))
253 #define UNIT_RST_L_TPC_MASK ((1 << UNIT_RST_L_TPC_0_SHIFT) | \
254 (1 << UNIT_RST_L_TPC_1_SHIFT) | \
255 (1 << UNIT_RST_L_TPC_2_SHIFT) | \
256 (1 << UNIT_RST_L_TPC_3_SHIFT) | \
257 (1 << UNIT_RST_L_TPC_4_SHIFT) | \
258 (1 << UNIT_RST_L_TPC_5_SHIFT) | \
259 (1 << UNIT_RST_L_TPC_6_SHIFT) | \
260 (1 << UNIT_RST_L_TPC_7_SHIFT))
262 /* CPU_CA53_CFG_ARM_RST_CONTROL */
263 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
264 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3
265 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4
266 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30
267 #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8
268 #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100
269 #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12
270 #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000
271 #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16
272 #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000
273 #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20
274 #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000
276 #define CPU_RESET_ASSERT (\
277 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)
279 #define CPU_RESET_CORE0_DEASSERT (\
280 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\
281 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\
282 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\
283 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)
285 /* QM_IDLE_MASK is valid for all engines QM idle check */
286 #define QM_IDLE_MASK (DMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \
287 DMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \
288 DMA0_QM_GLBL_STS0_CP_IDLE_MASK)
290 /* CGM_IDLE_MASK is valid for all engines CGM idle check */
291 #define CGM_IDLE_MASK DMA0_QM_CGM_STS_AGENT_IDLE_MASK
293 #define TPC_IDLE_MASK ((1 << TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT) | \
294 (1 << TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT) | \
295 (1 << TPC0_CFG_STATUS_IQ_EMPTY_SHIFT) | \
296 (1 << TPC0_CFG_STATUS_SB_EMPTY_SHIFT) | \
297 (1 << TPC0_CFG_STATUS_QM_IDLE_SHIFT) | \
298 (1 << TPC0_CFG_STATUS_QM_RDY_SHIFT))
300 #define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
301 #define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
302 #define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000
304 #define MME_ARCH_IDLE_MASK (MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK | \
305 MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK | \
306 MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK)
308 #define IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) \
309 ((((qm_glbl_sts0) & QM_IDLE_MASK) == QM_IDLE_MASK) && \
310 (((qm_cgm_sts) & CGM_IDLE_MASK) == CGM_IDLE_MASK))
312 #define IS_DMA_IDLE(dma_core_sts0) \
313 !(dma_core_sts0 & DMA0_CORE_STS0_BUSY_MASK)
315 #define IS_TPC_IDLE(tpc_cfg_sts) \
316 (((tpc_cfg_sts) & TPC_IDLE_MASK) == TPC_IDLE_MASK)
318 #define IS_MME_IDLE(mme_arch_sts) \
319 (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
325 AXI_ID_NIC, /* Local NIC */
330 AXI_ID_NIC_FT /* Feed-Through NIC */
333 /* RAZWI initiator ID is built from the location in the chip and the AXI ID */
335 #define RAZWI_INITIATOR_AXI_ID_SHIFT 20
336 #define RAZWI_INITIATOR_AXI_ID_MASK 0xF
337 #define RAZWI_INITIATOR_X_SHIFT 24
338 #define RAZWI_INITIATOR_X_MASK 0xF
339 #define RAZWI_INITIATOR_Y_SHIFT 28
340 #define RAZWI_INITIATOR_Y_MASK 0x7
342 #define RAZWI_INITIATOR_ID_AXI_ID(axi_id) \
343 (((axi_id) & RAZWI_INITIATOR_AXI_ID_MASK) << \
344 RAZWI_INITIATOR_AXI_ID_SHIFT)
346 #define RAZWI_INITIATOR_ID_X_Y(x, y) \
347 ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \
348 (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT))
350 #define RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0 RAZWI_INITIATOR_ID_X_Y(1, 1)
351 #define RAZWI_INITIATOR_ID_X_Y_TPC1 RAZWI_INITIATOR_ID_X_Y(2, 1)
352 #define RAZWI_INITIATOR_ID_X_Y_MME0_0 RAZWI_INITIATOR_ID_X_Y(3, 1)
353 #define RAZWI_INITIATOR_ID_X_Y_MME0_1 RAZWI_INITIATOR_ID_X_Y(4, 1)
354 #define RAZWI_INITIATOR_ID_X_Y_MME1_0 RAZWI_INITIATOR_ID_X_Y(5, 1)
355 #define RAZWI_INITIATOR_ID_X_Y_MME1_1 RAZWI_INITIATOR_ID_X_Y(6, 1)
356 #define RAZWI_INITIATOR_ID_X_Y_TPC2 RAZWI_INITIATOR_ID_X_Y(7, 1)
357 #define RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC \
358 RAZWI_INITIATOR_ID_X_Y(8, 1)
359 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1)
360 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0 RAZWI_INITIATOR_ID_X_Y(9, 1)
361 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2)
362 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1 RAZWI_INITIATOR_ID_X_Y(9, 2)
363 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3)
364 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0 RAZWI_INITIATOR_ID_X_Y(9, 3)
365 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4)
366 #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1 RAZWI_INITIATOR_ID_X_Y(9, 4)
367 #define RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2 RAZWI_INITIATOR_ID_X_Y(1, 6)
368 #define RAZWI_INITIATOR_ID_X_Y_TPC5 RAZWI_INITIATOR_ID_X_Y(2, 6)
369 #define RAZWI_INITIATOR_ID_X_Y_MME2_0 RAZWI_INITIATOR_ID_X_Y(3, 6)
370 #define RAZWI_INITIATOR_ID_X_Y_MME2_1 RAZWI_INITIATOR_ID_X_Y(4, 6)
371 #define RAZWI_INITIATOR_ID_X_Y_MME3_0 RAZWI_INITIATOR_ID_X_Y(5, 6)
372 #define RAZWI_INITIATOR_ID_X_Y_MME3_1 RAZWI_INITIATOR_ID_X_Y(6, 6)
373 #define RAZWI_INITIATOR_ID_X_Y_TPC6 RAZWI_INITIATOR_ID_X_Y(7, 6)
374 #define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5 RAZWI_INITIATOR_ID_X_Y(8, 6)
376 #define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1
379 #define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
380 #define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
381 #define STLB_CACHE_INV_INDEX_MASK_SHIFT 8
382 #define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00
384 #define MME_ACC_ACC_STALL_R_SHIFT 0
385 #define MME_SBAB_SB_STALL_R_SHIFT 0
387 #define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700
388 #define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000
390 #define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0
391 #define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0
393 /* DMA_IF_HBM_CRED_EN */
394 #define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0
395 #define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1
396 #define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT 1
397 #define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2
399 #define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0
400 #define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0
401 #define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0
402 #define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0
404 #define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0
405 #define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0
407 #define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0
408 #define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0
410 /* MMU_UP_PAGE_ERROR_CAPTURE */
411 #define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
412 #define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
414 /* MMU_UP_ACCESS_ERROR_CAPTURE */
415 #define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
416 #define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
418 #define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
419 #define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
420 #define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
422 #define QM_ARB_ERR_MSG_EN_MASK (\
423 QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\
424 QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK)
426 #define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1
427 #define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2
429 #endif /* GAUDI_MASKS_H_ */