drivers/misc/habanalabs/include/common/hl_boot_if.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2018-2020 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef HL_BOOT_IF_H
   9 #define HL_BOOT_IF_H
  10
  11 #define LKD_HARD_RESET_MAGIC            0xED7BD694 /* deprecated - do not use */
  12 #define HL_POWER9_HOST_MAGIC            0x1DA30009
  13
  14 #define BOOT_FIT_SRAM_OFFSET            0x200000
  15
  16 #define VERSION_MAX_LEN                 128
  17
  18 enum cpu_boot_err {
  19         CPU_BOOT_ERR_DRAM_INIT_FAIL = 0,
  20         CPU_BOOT_ERR_FIT_CORRUPTED = 1,
  21         CPU_BOOT_ERR_TS_INIT_FAIL = 2,
  22         CPU_BOOT_ERR_DRAM_SKIPPED = 3,
  23         CPU_BOOT_ERR_BMC_WAIT_SKIPPED = 4,
  24         CPU_BOOT_ERR_NIC_DATA_NOT_RDY = 5,
  25         CPU_BOOT_ERR_NIC_FW_FAIL = 6,
  26         CPU_BOOT_ERR_SECURITY_NOT_RDY = 7,
  27         CPU_BOOT_ERR_SECURITY_FAIL = 8,
  28         CPU_BOOT_ERR_EFUSE_FAIL = 9,
  29         CPU_BOOT_ERR_PRI_IMG_VER_FAIL = 10,
  30         CPU_BOOT_ERR_SEC_IMG_VER_FAIL = 11,
  31         CPU_BOOT_ERR_PLL_FAIL = 12,
  32         CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL = 13,
  33         CPU_BOOT_ERR_BOOT_FW_CRIT_ERR = 18,
  34         CPU_BOOT_ERR_BINNING_FAIL = 19,
  35         CPU_BOOT_ERR_TPM_FAIL = 20,
  36         CPU_BOOT_ERR_ENABLED = 31,
  37         CPU_BOOT_ERR_SCND_EN = 63,
  38         CPU_BOOT_ERR_LAST = 64 /* we have 2 registers of 32 bits */
  39 };
  40
  41 /*
  42  * CPU error bits in BOOT_ERROR registers
  43  *
  44  * CPU_BOOT_ERR0_DRAM_INIT_FAIL         DRAM initialization failed.
  45  *                                      DRAM is not reliable to use.
  46  *
  47  * CPU_BOOT_ERR0_FIT_CORRUPTED          FIT data integrity verification of the
  48  *                                      image provided by the host has failed.
  49  *
  50  * CPU_BOOT_ERR0_TS_INIT_FAIL           Thermal Sensor initialization failed.
  51  *                                      Boot continues as usual, but keep in
  52  *                                      mind this is a warning.
  53  *
  54  * CPU_BOOT_ERR0_DRAM_SKIPPED           DRAM initialization has been skipped.
  55  *                                      Skipping DRAM initialization has been
  56  *                                      requested (e.g. strap, command, etc.)
  57  *                                      and FW skipped the DRAM initialization.
  58  *                                      Host can initialize the DRAM.
  59  *
  60  * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED       Waiting for BMC data will be skipped.
  61  *                                      Meaning the BMC data might not be
  62  *                                      available until reset.
  63  *
  64  * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY       NIC data from BMC is not ready.
  65  *                                      BMC has not provided the NIC data yet.
  66  *                                      Once provided this bit will be cleared.
  67  *
  68  * CPU_BOOT_ERR0_NIC_FW_FAIL            NIC FW loading failed.
  69  *                                      The NIC FW loading and initialization
  70  *                                      failed. This means NICs are not usable.
  71  *
  72  * CPU_BOOT_ERR0_SECURITY_NOT_RDY       Chip security initialization has been
  73  *                                      started, but is not ready yet - chip
  74  *                                      cannot be accessed.
  75  *
  76  * CPU_BOOT_ERR0_SECURITY_FAIL          Security related tasks have failed.
  77  *                                      The tasks are security init (root of
  78  *                                      trust), boot authentication (chain of
  79  *                                      trust), data packets authentication.
  80  *
  81  * CPU_BOOT_ERR0_EFUSE_FAIL             Reading from eFuse failed.
  82  *                                      The PCI device ID might be wrong.
  83  *
  84  * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL       Verification of primary image failed.
  85  *                                      It mean that ppboot checksum
  86  *                                      verification for the preboot primary
  87  *                                      image has failed to match expected
  88  *                                      checksum. Trying to program image again
  89  *                                      might solve this.
  90  *
  91  * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL       Verification of secondary image failed.
  92  *                                      It mean that ppboot checksum
  93  *                                      verification for the preboot secondary
  94  *                                      image has failed to match expected
  95  *                                      checksum. Trying to program image again
  96  *                                      might solve this.
  97  *
  98  * CPU_BOOT_ERR0_PLL_FAIL               PLL settings failed, meaning that one
  99  *                                      of the PLLs remains in REF_CLK
 100  *
 101  * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL   Device is unusable and customer support
 102  *                                      should be contacted.
 103  *
 104  * CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR       Critical error was detected during
 105  *                                      the execution of ppboot or preboot.
 106  *                                      for example: stack overflow.
 107  *
 108  * CPU_BOOT_ERR0_BINNING_FAIL           Binning settings failed, meaning
 109  *                                      malfunctioning components might still be
 110  *                                      in use.
 111  *
 112  * CPU_BOOT_ERR0_TPM_FAIL               TPM verification flow failed.
 113  *
 114  * CPU_BOOT_ERR0_ENABLED                Error registers enabled.
 115  *                                      This is a main indication that the
 116  *                                      running FW populates the error
 117  *                                      registers. Meaning the error bits are
 118  *                                      not garbage, but actual error statuses.
 119  */
 120 #define CPU_BOOT_ERR0_DRAM_INIT_FAIL            (1 << CPU_BOOT_ERR_DRAM_INIT_FAIL)
 121 #define CPU_BOOT_ERR0_FIT_CORRUPTED             (1 << CPU_BOOT_ERR_FIT_CORRUPTED)
 122 #define CPU_BOOT_ERR0_TS_INIT_FAIL              (1 << CPU_BOOT_ERR_TS_INIT_FAIL)
 123 #define CPU_BOOT_ERR0_DRAM_SKIPPED              (1 << CPU_BOOT_ERR_DRAM_SKIPPED)
 124 #define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED          (1 << CPU_BOOT_ERR_BMC_WAIT_SKIPPED)
 125 #define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY          (1 << CPU_BOOT_ERR_NIC_DATA_NOT_RDY)
 126 #define CPU_BOOT_ERR0_NIC_FW_FAIL               (1 << CPU_BOOT_ERR_NIC_FW_FAIL)
 127 #define CPU_BOOT_ERR0_SECURITY_NOT_RDY          (1 << CPU_BOOT_ERR_SECURITY_NOT_RDY)
 128 #define CPU_BOOT_ERR0_SECURITY_FAIL             (1 << CPU_BOOT_ERR_SECURITY_FAIL)
 129 #define CPU_BOOT_ERR0_EFUSE_FAIL                (1 << CPU_BOOT_ERR_EFUSE_FAIL)
 130 #define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL          (1 << CPU_BOOT_ERR_PRI_IMG_VER_FAIL)
 131 #define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL          (1 << CPU_BOOT_ERR_SEC_IMG_VER_FAIL)
 132 #define CPU_BOOT_ERR0_PLL_FAIL                  (1 << CPU_BOOT_ERR_PLL_FAIL)
 133 #define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL      (1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL)
 134 #define CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR          (1 << CPU_BOOT_ERR_BOOT_FW_CRIT_ERR)
 135 #define CPU_BOOT_ERR0_BINNING_FAIL              (1 << CPU_BOOT_ERR_BINNING_FAIL)
 136 #define CPU_BOOT_ERR0_TPM_FAIL                  (1 << CPU_BOOT_ERR_TPM_FAIL)
 137 #define CPU_BOOT_ERR0_ENABLED                   (1 << CPU_BOOT_ERR_ENABLED)
 138 #define CPU_BOOT_ERR1_ENABLED                   (1 << CPU_BOOT_ERR_ENABLED)
 139
 140 enum cpu_boot_dev_sts {
 141         CPU_BOOT_DEV_STS_SECURITY_EN = 0,
 142         CPU_BOOT_DEV_STS_DEBUG_EN = 1,
 143         CPU_BOOT_DEV_STS_WATCHDOG_EN = 2,
 144         CPU_BOOT_DEV_STS_DRAM_INIT_EN = 3,
 145         CPU_BOOT_DEV_STS_BMC_WAIT_EN = 4,
 146         CPU_BOOT_DEV_STS_E2E_CRED_EN = 5,
 147         CPU_BOOT_DEV_STS_HBM_CRED_EN = 6,
 148         CPU_BOOT_DEV_STS_RL_EN = 7,
 149         CPU_BOOT_DEV_STS_SRAM_SCR_EN = 8,
 150         CPU_BOOT_DEV_STS_DRAM_SCR_EN = 9,
 151         CPU_BOOT_DEV_STS_FW_HARD_RST_EN = 10,
 152         CPU_BOOT_DEV_STS_PLL_INFO_EN = 11,
 153         CPU_BOOT_DEV_STS_SP_SRAM_EN = 12,
 154         CPU_BOOT_DEV_STS_CLK_GATE_EN = 13,
 155         CPU_BOOT_DEV_STS_HBM_ECC_EN = 14,
 156         CPU_BOOT_DEV_STS_PKT_PI_ACK_EN = 15,
 157         CPU_BOOT_DEV_STS_FW_LD_COM_EN = 16,
 158         CPU_BOOT_DEV_STS_FW_IATU_CONF_EN = 17,
 159         CPU_BOOT_DEV_STS_FW_NIC_MAC_EN = 18,
 160         CPU_BOOT_DEV_STS_DYN_PLL_EN = 19,
 161         CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN = 20,
 162         CPU_BOOT_DEV_STS_EQ_INDEX_EN = 21,
 163         CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN = 22,
 164         CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN = 23,
 165         CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN = 24,
 166         CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN = 25,
 167         CPU_BOOT_DEV_STS_MAP_HWMON_EN = 26,
 168         CPU_BOOT_DEV_STS_ENABLED = 31,
 169         CPU_BOOT_DEV_STS_SCND_EN = 63,
 170         CPU_BOOT_DEV_STS_LAST = 64 /* we have 2 registers of 32 bits */
 171 };
 172
 173 /*
 174  * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers
 175  *
 176  * CPU_BOOT_DEV_STS0_SECURITY_EN        Security is Enabled.
 177  *                                      This is an indication for security
 178  *                                      enabled in FW, which means that
 179  *                                      all conditions for security are met:
 180  *                                      device is indicated as security enabled,
 181  *                                      registers are protected, and device
 182  *                                      uses keys for image verification.
 183  *                                      Initialized in: preboot
 184  *
 185  * CPU_BOOT_DEV_STS0_DEBUG_EN           Debug is enabled.
 186  *                                      Enabled when JTAG or DEBUG is enabled
 187  *                                      in FW.
 188  *                                      Initialized in: preboot
 189  *
 190  * CPU_BOOT_DEV_STS0_WATCHDOG_EN        Watchdog is enabled.
 191  *                                      Watchdog is enabled in FW.
 192  *                                      Initialized in: preboot
 193  *
 194  * CPU_BOOT_DEV_STS0_DRAM_INIT_EN       DRAM initialization is enabled.
 195  *                                      DRAM initialization has been done in FW.
 196  *                                      Initialized in: u-boot
 197  *
 198  * CPU_BOOT_DEV_STS0_BMC_WAIT_EN        Waiting for BMC data enabled.
 199  *                                      If set, it means that during boot,
 200  *                                      FW waited for BMC data.
 201  *                                      Initialized in: u-boot
 202  *
 203  * CPU_BOOT_DEV_STS0_E2E_CRED_EN        E2E credits initialized.
 204  *                                      FW initialized E2E credits.
 205  *                                      Initialized in: u-boot
 206  *
 207  * CPU_BOOT_DEV_STS0_HBM_CRED_EN        HBM credits initialized.
 208  *                                      FW initialized HBM credits.
 209  *                                      Initialized in: u-boot
 210  *
 211  * CPU_BOOT_DEV_STS0_RL_EN              Rate limiter initialized.
 212  *                                      FW initialized rate limiter.
 213  *                                      Initialized in: u-boot
 214  *
 215  * CPU_BOOT_DEV_STS0_SRAM_SCR_EN        SRAM scrambler enabled.
 216  *                                      FW initialized SRAM scrambler.
 217  *                                      Initialized in: linux
 218  *
 219  * CPU_BOOT_DEV_STS0_DRAM_SCR_EN        DRAM scrambler enabled.
 220  *                                      FW initialized DRAM scrambler.
 221  *                                      Initialized in: u-boot
 222  *
 223  * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN     FW hard reset procedure is enabled.
 224  *                                      FW has the hard reset procedure
 225  *                                      implemented. This means that FW will
 226  *                                      perform hard reset procedure on
 227  *                                      receiving the halt-machine event.
 228  *                                      Initialized in: preboot, u-boot, linux
 229  *
 230  * CPU_BOOT_DEV_STS0_PLL_INFO_EN        FW retrieval of PLL info is enabled.
 231  *                                      Initialized in: linux
 232  *
 233  * CPU_BOOT_DEV_STS0_SP_SRAM_EN         SP SRAM is initialized and available
 234  *                                      for use.
 235  *                                      Initialized in: preboot
 236  *
 237  * CPU_BOOT_DEV_STS0_CLK_GATE_EN        Clock Gating enabled.
 238  *                                      FW initialized Clock Gating.
 239  *                                      Initialized in: preboot
 240  *
 241  * CPU_BOOT_DEV_STS0_HBM_ECC_EN         HBM ECC handling Enabled.
 242  *                                      FW handles HBM ECC indications.
 243  *                                      Initialized in: linux
 244  *
 245  * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN      Packets ack value used in the armcpd
 246  *                                      is set to the PI counter.
 247  *                                      Initialized in: linux
 248  *
 249  * CPU_BOOT_DEV_STS0_FW_LD_COM_EN       Flexible FW loading communication
 250  *                                      protocol is enabled.
 251  *                                      Initialized in: preboot
 252  *
 253  * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN    FW iATU configuration is enabled.
 254  *                                      This bit if set, means the iATU has been
 255  *                                      configured and is ready for use.
 256  *                                      Initialized in: ppboot
 257  *
 258  * CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN      NIC MAC channels init is done by FW and
 259  *                                      any access to them is done via the FW.
 260  *                                      Initialized in: linux
 261  *
 262  * CPU_BOOT_DEV_STS0_DYN_PLL_EN         Dynamic PLL configuration is enabled.
 263  *                                      FW sends to host a bitmap of supported
 264  *                                      PLLs.
 265  *                                      Initialized in: linux
 266  *
 267  * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN  GIC access permission only from
 268  *                                      previleged entity. FW sets this status
 269  *                                      bit for host. If this bit is set then
 270  *                                      GIC can not be accessed from host.
 271  *                                      Initialized in: linux
 272  *
 273  * CPU_BOOT_DEV_STS0_EQ_INDEX_EN        Event Queue (EQ) index is a running
 274  *                                      index for each new event sent to host.
 275  *                                      This is used as a method in host to
 276  *                                      identify that the waiting event in
 277  *                                      queue is actually a new event which
 278  *                                      was not served before.
 279  *                                      Initialized in: linux
 280  *
 281  * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN  Use multiple scratchpad interfaces to
 282  *                                      prevent IRQs overriding each other.
 283  *                                      Initialized in: linux
 284  *
 285  * CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN
 286  *                                      NIC STAT and XPCS91 access is restricted
 287  *                                      and is done via FW only.
 288  *                                      Initialized in: linux
 289  *
 290  * CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN
 291  *                                      NIC STAT get all is supported.
 292  *                                      Initialized in: linux
 293  *
 294  * CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN
 295  *                                      F/W checks if the device is idle by reading defined set
 296  *                                      of registers. It returns a bitmask of all the engines,
 297  *                                      where a bit is set if the engine is not idle.
 298  *                                      Initialized in: linux
 299  *
 300  * CPU_BOOT_DEV_STS0_MAP_HWMON_EN
 301  *                                      If set, means f/w supports proprietary
 302  *                                      HWMON enum mapping to cpucp enums.
 303  *                                      Initialized in: linux
 304  *
 305  * CPU_BOOT_DEV_STS0_ENABLED            Device status register enabled.
 306  *                                      This is a main indication that the
 307  *                                      running FW populates the device status
 308  *                                      register. Meaning the device status
 309  *                                      bits are not garbage, but actual
 310  *                                      statuses.
 311  *                                      Initialized in: preboot
 312  *
 313  */
 314 #define CPU_BOOT_DEV_STS0_SECURITY_EN           (1 << CPU_BOOT_DEV_STS_SECURITY_EN)
 315 #define CPU_BOOT_DEV_STS0_DEBUG_EN              (1 << CPU_BOOT_DEV_STS_DEBUG_EN)
 316 #define CPU_BOOT_DEV_STS0_WATCHDOG_EN           (1 << CPU_BOOT_DEV_STS_WATCHDOG_EN)
 317 #define CPU_BOOT_DEV_STS0_DRAM_INIT_EN          (1 << CPU_BOOT_DEV_STS_DRAM_INIT_EN)
 318 #define CPU_BOOT_DEV_STS0_BMC_WAIT_EN           (1 << CPU_BOOT_DEV_STS_BMC_WAIT_EN)
 319 #define CPU_BOOT_DEV_STS0_E2E_CRED_EN           (1 << CPU_BOOT_DEV_STS_E2E_CRED_EN)
 320 #define CPU_BOOT_DEV_STS0_HBM_CRED_EN           (1 << CPU_BOOT_DEV_STS_HBM_CRED_EN)
 321 #define CPU_BOOT_DEV_STS0_RL_EN                 (1 << CPU_BOOT_DEV_STS_RL_EN)
 322 #define CPU_BOOT_DEV_STS0_SRAM_SCR_EN           (1 << CPU_BOOT_DEV_STS_SRAM_SCR_EN)
 323 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN           (1 << CPU_BOOT_DEV_STS_DRAM_SCR_EN)
 324 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN        (1 << CPU_BOOT_DEV_STS_FW_HARD_RST_EN)
 325 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN           (1 << CPU_BOOT_DEV_STS_PLL_INFO_EN)
 326 #define CPU_BOOT_DEV_STS0_SP_SRAM_EN            (1 << CPU_BOOT_DEV_STS_SP_SRAM_EN)
 327 #define CPU_BOOT_DEV_STS0_CLK_GATE_EN           (1 << CPU_BOOT_DEV_STS_CLK_GATE_EN)
 328 #define CPU_BOOT_DEV_STS0_HBM_ECC_EN            (1 << CPU_BOOT_DEV_STS_HBM_ECC_EN)
 329 #define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN         (1 << CPU_BOOT_DEV_STS_PKT_PI_ACK_EN)
 330 #define CPU_BOOT_DEV_STS0_FW_LD_COM_EN          (1 << CPU_BOOT_DEV_STS_FW_LD_COM_EN)
 331 #define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN       (1 << CPU_BOOT_DEV_STS_FW_IATU_CONF_EN)
 332 #define CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN         (1 << CPU_BOOT_DEV_STS_FW_NIC_MAC_EN)
 333 #define CPU_BOOT_DEV_STS0_DYN_PLL_EN            (1 << CPU_BOOT_DEV_STS_DYN_PLL_EN)
 334 #define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN     (1 << CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN)
 335 #define CPU_BOOT_DEV_STS0_EQ_INDEX_EN           (1 << CPU_BOOT_DEV_STS_EQ_INDEX_EN)
 336 #define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN     (1 << CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN)
 337 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN)
 338 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN    (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN)
 339 #define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN      (1 << CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN)
 340 #define CPU_BOOT_DEV_STS0_MAP_HWMON_EN          (1 << CPU_BOOT_DEV_STS_MAP_HWMON_EN)
 341 #define CPU_BOOT_DEV_STS0_ENABLED               (1 << CPU_BOOT_DEV_STS_ENABLED)
 342 #define CPU_BOOT_DEV_STS1_ENABLED               (1 << CPU_BOOT_DEV_STS_ENABLED)
 343
 344 enum cpu_boot_status {
 345         CPU_BOOT_STATUS_NA = 0,         /* Default value after reset of chip */
 346         CPU_BOOT_STATUS_IN_WFE = 1,
 347         CPU_BOOT_STATUS_DRAM_RDY = 2,
 348         CPU_BOOT_STATUS_SRAM_AVAIL = 3,
 349         CPU_BOOT_STATUS_IN_BTL = 4,     /* BTL is H/W FSM */
 350         CPU_BOOT_STATUS_IN_PREBOOT = 5,
 351         CPU_BOOT_STATUS_IN_SPL,         /* deprecated - not reported */
 352         CPU_BOOT_STATUS_IN_UBOOT = 7,
 353         CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */
 354         CPU_BOOT_STATUS_FIT_CORRUPTED,  /* deprecated - will be removed */
 355         /* U-Boot console prompt activated, commands are not processed */
 356         CPU_BOOT_STATUS_UBOOT_NOT_READY = 10,
 357         /* Finished NICs init, reported after DRAM and NICs */
 358         CPU_BOOT_STATUS_NIC_FW_RDY = 11,
 359         CPU_BOOT_STATUS_TS_INIT_FAIL,   /* deprecated - will be removed */
 360         CPU_BOOT_STATUS_DRAM_SKIPPED,   /* deprecated - will be removed */
 361         CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */
 362         /* Last boot loader progress status, ready to receive commands */
 363         CPU_BOOT_STATUS_READY_TO_BOOT = 15,
 364         /* Internal Boot finished, ready for boot-fit */
 365         CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16,
 366         /* Internal Security has been initialized, device can be accessed */
 367         CPU_BOOT_STATUS_SECURITY_READY = 17,
 368 };
 369
 370 enum kmd_msg {
 371         KMD_MSG_NA = 0,
 372         KMD_MSG_GOTO_WFE,
 373         KMD_MSG_FIT_RDY,
 374         KMD_MSG_SKIP_BMC,
 375         RESERVED,
 376         KMD_MSG_RST_DEV,
 377         KMD_MSG_LAST
 378 };
 379
 380 enum cpu_msg_status {
 381         CPU_MSG_CLR = 0,
 382         CPU_MSG_OK,
 383         CPU_MSG_ERR,
 384 };
 385
 386 /* communication registers mapping - consider ABI when changing */
 387 struct cpu_dyn_regs {
 388         __le32 cpu_pq_base_addr_low;
 389         __le32 cpu_pq_base_addr_high;
 390         __le32 cpu_pq_length;
 391         __le32 cpu_pq_init_status;
 392         __le32 cpu_eq_base_addr_low;
 393         __le32 cpu_eq_base_addr_high;
 394         __le32 cpu_eq_length;
 395         __le32 cpu_eq_ci;
 396         __le32 cpu_cq_base_addr_low;
 397         __le32 cpu_cq_base_addr_high;
 398         __le32 cpu_cq_length;
 399         __le32 cpu_pf_pq_pi;
 400         __le32 cpu_boot_dev_sts0;
 401         __le32 cpu_boot_dev_sts1;
 402         __le32 cpu_boot_err0;
 403         __le32 cpu_boot_err1;
 404         __le32 cpu_boot_status;
 405         __le32 fw_upd_sts;
 406         __le32 fw_upd_cmd;
 407         __le32 fw_upd_pending_sts;
 408         __le32 fuse_ver_offset;
 409         __le32 preboot_ver_offset;
 410         __le32 uboot_ver_offset;
 411         __le32 hw_state;
 412         __le32 kmd_msg_to_cpu;
 413         __le32 cpu_cmd_status_to_host;
 414         __le32 gic_host_pi_upd_irq;
 415         __le32 gic_tpc_qm_irq_ctrl;
 416         __le32 gic_mme_qm_irq_ctrl;
 417         __le32 gic_dma_qm_irq_ctrl;
 418         __le32 gic_nic_qm_irq_ctrl;
 419         __le32 gic_dma_core_irq_ctrl;
 420         __le32 gic_host_halt_irq;
 421         __le32 gic_host_ints_irq;
 422         __le32 gic_host_soft_rst_irq;
 423         __le32 gic_rot_qm_irq_ctrl;
 424         __le32 reserved1[22];           /* reserve for future use */
 425 };
 426
 427 /* TODO: remove the desc magic after the code is updated to use message */
 428 /* HCDM - Habana Communications Descriptor Magic */
 429 #define HL_COMMS_DESC_MAGIC     0x4843444D
 430 #define HL_COMMS_DESC_VER       1
 431
 432 /* HCMv - Habana Communications Message + header version */
 433 #define HL_COMMS_MSG_MAGIC_VALUE        0x48434D00
 434 #define HL_COMMS_MSG_MAGIC_MASK         0xFFFFFF00
 435 #define HL_COMMS_MSG_MAGIC_VER_MASK     0xFF
 436
 437 #define HL_COMMS_MSG_MAGIC_VER(ver)     (HL_COMMS_MSG_MAGIC_VALUE |     \
 438                                         ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK))
 439 #define HL_COMMS_MSG_MAGIC_V0           HL_COMMS_DESC_MAGIC
 440 #define HL_COMMS_MSG_MAGIC_V1           HL_COMMS_MSG_MAGIC_VER(1)
 441
 442 #define HL_COMMS_MSG_MAGIC              HL_COMMS_MSG_MAGIC_V1
 443
 444 #define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic)                        \
 445                 (((magic) & HL_COMMS_MSG_MAGIC_MASK) ==                 \
 446                 HL_COMMS_MSG_MAGIC_VALUE)
 447
 448 #define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver)                 \
 449                 (((magic) & HL_COMMS_MSG_MAGIC_VER_MASK) >=             \
 450                 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK))
 451
 452 #define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver)                         \
 453                 (HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC((magic)) &&          \
 454                 HL_COMMS_MSG_MAGIC_VALIDATE_VERSION((magic), (ver)))
 455
 456 enum comms_msg_type {
 457         HL_COMMS_DESC_TYPE = 0,
 458         HL_COMMS_RESET_CAUSE_TYPE = 1,
 459         HL_COMMS_FW_CFG_SKIP_TYPE = 2,
 460         HL_COMMS_BINNING_CONF_TYPE = 3,
 461 };
 462
 463 /* TODO: remove this struct after the code is updated to use message */
 464 /* this is the comms descriptor header - meta data */
 465 struct comms_desc_header {
 466         __le32 magic;           /* magic for validation */
 467         __le32 crc32;           /* CRC32 of the descriptor w/o header */
 468         __le16 size;            /* size of the descriptor w/o header */
 469         __u8 version;   /* descriptor version */
 470         __u8 reserved[5];       /* pad to 64 bit */
 471 };
 472
 473 /* this is the comms message header - meta data */
 474 struct comms_msg_header {
 475         __le32 magic;           /* magic for validation */
 476         __le32 crc32;           /* CRC32 of the message w/o header */
 477         __le16 size;            /* size of the message w/o header */
 478         __u8 version;   /* message payload version */
 479         __u8 type;              /* message type */
 480         __u8 reserved[4];       /* pad to 64 bit */
 481 };
 482
 483 /* this is the main FW descriptor - consider ABI when changing */
 484 struct lkd_fw_comms_desc {
 485         struct comms_desc_header header;
 486         struct cpu_dyn_regs cpu_dyn_regs;
 487         char fuse_ver[VERSION_MAX_LEN];
 488         char cur_fw_ver[VERSION_MAX_LEN];
 489         /* can be used for 1 more version w/o ABI change */
 490         char reserved0[VERSION_MAX_LEN];
 491         __le64 img_addr;        /* address for next FW component load */
 492 };
 493
 494 enum comms_reset_cause {
 495         HL_RESET_CAUSE_UNKNOWN = 0,
 496         HL_RESET_CAUSE_HEARTBEAT = 1,
 497         HL_RESET_CAUSE_TDR = 2,
 498 };
 499
 500 /* TODO: remove define after struct name is aligned on all projects */
 501 #define lkd_msg_comms lkd_fw_comms_msg
 502
 503 /* this is the comms message descriptor */
 504 struct lkd_fw_comms_msg {
 505         struct comms_msg_header header;
 506         /* union for future expantions of new messages */
 507         union {
 508                 struct {
 509                         struct cpu_dyn_regs cpu_dyn_regs;
 510                         char fuse_ver[VERSION_MAX_LEN];
 511                         char cur_fw_ver[VERSION_MAX_LEN];
 512                         /* can be used for 1 more version w/o ABI change */
 513                         char reserved0[VERSION_MAX_LEN];
 514                         /* address for next FW component load */
 515                         __le64 img_addr;
 516                 };
 517                 struct {
 518                         __u8 reset_cause;
 519                 };
 520                 struct {
 521                         __u8 fw_cfg_skip; /* 1 - skip, 0 - don't skip */
 522                 };
 523         };
 524 };
 525
 526 /*
 527  * LKD commands:
 528  *
 529  * COMMS_NOOP                   Used to clear the command register and no actual
 530  *                              command is send.
 531  *
 532  * COMMS_CLR_STS                Clear status command - FW should clear the
 533  *                              status register. Used for synchronization
 534  *                              between the commands as part of the race free
 535  *                              protocol.
 536  *
 537  * COMMS_RST_STATE              Reset the current communication state which is
 538  *                              kept by FW for proper responses.
 539  *                              Should be used in the beginning of the
 540  *                              communication cycle to clean any leftovers from
 541  *                              previous communication attempts.
 542  *
 543  * COMMS_PREP_DESC              Prepare descriptor for setting up the
 544  *                              communication and other dynamic data:
 545  *                              struct lkd_fw_comms_desc.
 546  *                              This command has a parameter stating the next FW
 547  *                              component size, so the FW can actually prepare a
 548  *                              space for it and in the status response provide
 549  *                              the descriptor offset. The Offset of the next FW
 550  *                              data component is a part of the descriptor
 551  *                              structure.
 552  *
 553  * COMMS_DATA_RDY               The FW data has been uploaded and is ready for
 554  *                              validation.
 555  *
 556  * COMMS_EXEC                   Execute the next FW component.
 557  *
 558  * COMMS_RST_DEV                Reset the device.
 559  *
 560  * COMMS_GOTO_WFE               Execute WFE command. Allowed only on non-secure
 561  *                              devices.
 562  *
 563  * COMMS_SKIP_BMC               Perform actions required for BMC-less servers.
 564  *                              Do not wait for BMC response.
 565  *
 566  * COMMS_PREP_DESC_ELBI         Same as COMMS_PREP_DESC only that the memory
 567  *                              space is allocated in a ELBI access only
 568  *                              address range.
 569  *
 570  */
 571 enum comms_cmd {
 572         COMMS_NOOP = 0,
 573         COMMS_CLR_STS = 1,
 574         COMMS_RST_STATE = 2,
 575         COMMS_PREP_DESC = 3,
 576         COMMS_DATA_RDY = 4,
 577         COMMS_EXEC = 5,
 578         COMMS_RST_DEV = 6,
 579         COMMS_GOTO_WFE = 7,
 580         COMMS_SKIP_BMC = 8,
 581         COMMS_PREP_DESC_ELBI = 10,
 582         COMMS_INVLD_LAST
 583 };
 584
 585 #define COMMS_COMMAND_SIZE_SHIFT        0
 586 #define COMMS_COMMAND_SIZE_MASK         0x1FFFFFF
 587 #define COMMS_COMMAND_CMD_SHIFT         27
 588 #define COMMS_COMMAND_CMD_MASK          0xF8000000
 589
 590 /*
 591  * LKD command to FW register structure
 592  * @size        - FW component size
 593  * @cmd         - command from enum comms_cmd
 594  */
 595 struct comms_command {
 596         union {         /* bit fields are only for FW use */
 597                 struct {
 598                         u32 size :25;           /* 32MB max. */
 599                         u32 reserved :2;
 600                         enum comms_cmd cmd :5;          /* 32 commands */
 601                 };
 602                 __le32 val;
 603         };
 604 };
 605
 606 /*
 607  * FW status
 608  *
 609  * COMMS_STS_NOOP               Used to clear the status register and no actual
 610  *                              status is provided.
 611  *
 612  * COMMS_STS_ACK                Command has been received and recognized.
 613  *
 614  * COMMS_STS_OK                 Command execution has finished successfully.
 615  *
 616  * COMMS_STS_ERR                Command execution was unsuccessful and resulted
 617  *                              in error.
 618  *
 619  * COMMS_STS_VALID_ERR          FW validation has failed.
 620  *
 621  * COMMS_STS_TIMEOUT_ERR        Command execution has timed out.
 622  */
 623 enum comms_sts {
 624         COMMS_STS_NOOP = 0,
 625         COMMS_STS_ACK = 1,
 626         COMMS_STS_OK = 2,
 627         COMMS_STS_ERR = 3,
 628         COMMS_STS_VALID_ERR = 4,
 629         COMMS_STS_TIMEOUT_ERR = 5,
 630         COMMS_STS_INVLD_LAST
 631 };
 632
 633 /* RAM types for FW components loading - defines the base address */
 634 enum comms_ram_types {
 635         COMMS_SRAM = 0,
 636         COMMS_DRAM = 1,
 637 };
 638
 639 #define COMMS_STATUS_OFFSET_SHIFT       0
 640 #define COMMS_STATUS_OFFSET_MASK        0x03FFFFFF
 641 #define COMMS_STATUS_OFFSET_ALIGN_SHIFT 2
 642 #define COMMS_STATUS_RAM_TYPE_SHIFT     26
 643 #define COMMS_STATUS_RAM_TYPE_MASK      0x0C000000
 644 #define COMMS_STATUS_STATUS_SHIFT       28
 645 #define COMMS_STATUS_STATUS_MASK        0xF0000000
 646
 647 /*
 648  * FW status to LKD register structure
 649  * @offset      - an offset from the base of the ram_type shifted right by
 650  *                2 bits (always aligned to 32 bits).
 651  *                Allows a maximum addressable offset of 256MB from RAM base.
 652  *                Example: for real offset in RAM of 0x800000 (8MB), the value
 653  *                in offset field is (0x800000 >> 2) = 0x200000.
 654  * @ram_type    - the RAM type that should be used for offset from
 655  *                enum comms_ram_types
 656  * @status      - status from enum comms_sts
 657  */
 658 struct comms_status {
 659         union {         /* bit fields are only for FW use */
 660                 struct {
 661                         u32 offset :26;
 662                         enum comms_ram_types ram_type :2;
 663                         enum comms_sts status :4;       /* 16 statuses */
 664                 };
 665                 __le32 val;
 666         };
 667 };
 668
 669 #endif /* HL_BOOT_IF_H */