drivers/misc/habanalabs/include/common/hl_boot_if.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2018-2020 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef HL_BOOT_IF_H
   9 #define HL_BOOT_IF_H
  10
  11 #define LKD_HARD_RESET_MAGIC            0xED7BD694
  12 #define HL_POWER9_HOST_MAGIC            0x1DA30009
  13
  14 #define BOOT_FIT_SRAM_OFFSET            0x200000
  15
  16 /*
  17  * CPU error bits in BOOT_ERROR registers
  18  *
  19  * CPU_BOOT_ERR0_DRAM_INIT_FAIL         DRAM initialization failed.
  20  *                                      DRAM is not reliable to use.
  21  *
  22  * CPU_BOOT_ERR0_FIT_CORRUPTED          FIT data integrity verification of the
  23  *                                      image provided by the host has failed.
  24  *
  25  * CPU_BOOT_ERR0_TS_INIT_FAIL           Thermal Sensor initialization failed.
  26  *                                      Boot continues as usual, but keep in
  27  *                                      mind this is a warning.
  28  *
  29  * CPU_BOOT_ERR0_DRAM_SKIPPED           DRAM initialization has been skipped.
  30  *                                      Skipping DRAM initialization has been
  31  *                                      requested (e.g. strap, command, etc.)
  32  *                                      and FW skipped the DRAM initialization.
  33  *                                      Host can initialize the DRAM.
  34  *
  35  * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED       Waiting for BMC data will be skipped.
  36  *                                      Meaning the BMC data might not be
  37  *                                      available until reset.
  38  *
  39  * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY       NIC data from BMC is not ready.
  40  *                                      BMC has not provided the NIC data yet.
  41  *                                      Once provided this bit will be cleared.
  42  *
  43  * CPU_BOOT_ERR0_NIC_FW_FAIL            NIC FW loading failed.
  44  *                                      The NIC FW loading and initialization
  45  *                                      failed. This means NICs are not usable.
  46  *
  47  * CPU_BOOT_ERR0_SECURITY_NOT_RDY       Chip security initialization has been
  48  *                                      started, but is not ready yet - chip
  49  *                                      cannot be accessed.
  50  *
  51  * CPU_BOOT_ERR0_SECURITY_FAIL          Security related tasks have failed.
  52  *                                      The tasks are security init (root of
  53  *                                      trust), boot authentication (chain of
  54  *                                      trust), data packets authentication.
  55  *
  56  * CPU_BOOT_ERR0_EFUSE_FAIL             Reading from eFuse failed.
  57  *                                      The PCI device ID might be wrong.
  58  *
  59  * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL       Verification of primary image failed.
  60  *                                      It mean that ppboot checksum
  61  *                                      verification for the preboot primary
  62  *                                      image has failed to match expected
  63  *                                      checksum. Trying to program image again
  64  *                                      might solve this.
  65  *
  66  * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL       Verification of secondary image failed.
  67  *                                      It mean that ppboot checksum
  68  *                                      verification for the preboot secondary
  69  *                                      image has failed to match expected
  70  *                                      checksum. Trying to program image again
  71  *                                      might solve this.
  72  *
  73  * CPU_BOOT_ERR0_ENABLED                Error registers enabled.
  74  *                                      This is a main indication that the
  75  *                                      running FW populates the error
  76  *                                      registers. Meaning the error bits are
  77  *                                      not garbage, but actual error statuses.
  78  */
  79 #define CPU_BOOT_ERR0_DRAM_INIT_FAIL            (1 << 0)
  80 #define CPU_BOOT_ERR0_FIT_CORRUPTED             (1 << 1)
  81 #define CPU_BOOT_ERR0_TS_INIT_FAIL              (1 << 2)
  82 #define CPU_BOOT_ERR0_DRAM_SKIPPED              (1 << 3)
  83 #define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED          (1 << 4)
  84 #define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY          (1 << 5)
  85 #define CPU_BOOT_ERR0_NIC_FW_FAIL               (1 << 6)
  86 #define CPU_BOOT_ERR0_SECURITY_NOT_RDY          (1 << 7)
  87 #define CPU_BOOT_ERR0_SECURITY_FAIL             (1 << 8)
  88 #define CPU_BOOT_ERR0_EFUSE_FAIL                (1 << 9)
  89 #define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL          (1 << 10)
  90 #define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL          (1 << 11)
  91 #define CPU_BOOT_ERR0_ENABLED                   (1 << 31)
  92
  93 /*
  94  * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers
  95  *
  96  * CPU_BOOT_DEV_STS0_SECURITY_EN        Security is Enabled.
  97  *                                      This is an indication for security
  98  *                                      enabled in FW, which means that
  99  *                                      all conditions for security are met:
 100  *                                      device is indicated as security enabled,
 101  *                                      registers are protected, and device
 102  *                                      uses keys for image verification.
 103  *                                      Initialized in: preboot
 104  *
 105  * CPU_BOOT_DEV_STS0_DEBUG_EN           Debug is enabled.
 106  *                                      Enabled when JTAG or DEBUG is enabled
 107  *                                      in FW.
 108  *                                      Initialized in: preboot
 109  *
 110  * CPU_BOOT_DEV_STS0_WATCHDOG_EN        Watchdog is enabled.
 111  *                                      Watchdog is enabled in FW.
 112  *                                      Initialized in: preboot
 113  *
 114  * CPU_BOOT_DEV_STS0_DRAM_INIT_EN       DRAM initialization is enabled.
 115  *                                      DRAM initialization has been done in FW.
 116  *                                      Initialized in: u-boot
 117  *
 118  * CPU_BOOT_DEV_STS0_BMC_WAIT_EN        Waiting for BMC data enabled.
 119  *                                      If set, it means that during boot,
 120  *                                      FW waited for BMC data.
 121  *                                      Initialized in: u-boot
 122  *
 123  * CPU_BOOT_DEV_STS0_E2E_CRED_EN        E2E credits initialized.
 124  *                                      FW initialized E2E credits.
 125  *                                      Initialized in: u-boot
 126  *
 127  * CPU_BOOT_DEV_STS0_HBM_CRED_EN        HBM credits initialized.
 128  *                                      FW initialized HBM credits.
 129  *                                      Initialized in: u-boot
 130  *
 131  * CPU_BOOT_DEV_STS0_RL_EN              Rate limiter initialized.
 132  *                                      FW initialized rate limiter.
 133  *                                      Initialized in: u-boot
 134  *
 135  * CPU_BOOT_DEV_STS0_SRAM_SCR_EN        SRAM scrambler enabled.
 136  *                                      FW initialized SRAM scrambler.
 137  *                                      Initialized in: linux
 138  *
 139  * CPU_BOOT_DEV_STS0_DRAM_SCR_EN        DRAM scrambler enabled.
 140  *                                      FW initialized DRAM scrambler.
 141  *                                      Initialized in: u-boot
 142  *
 143  * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN     FW hard reset procedure is enabled.
 144  *                                      FW has the hard reset procedure
 145  *                                      implemented. This means that FW will
 146  *                                      perform hard reset procedure on
 147  *                                      receiving the halt-machine event.
 148  *                                      Initialized in: linux
 149  *
 150  * CPU_BOOT_DEV_STS0_PLL_INFO_EN        FW retrieval of PLL info is enabled.
 151  *                                      Initialized in: linux
 152  *
 153  * CPU_BOOT_DEV_STS0_ENABLED            Device status register enabled.
 154  *                                      This is a main indication that the
 155  *                                      running FW populates the device status
 156  *                                      register. Meaning the device status
 157  *                                      bits are not garbage, but actual
 158  *                                      statuses.
 159  *                                      Initialized in: preboot
 160  *
 161  */
 162 #define CPU_BOOT_DEV_STS0_SECURITY_EN                   (1 << 0)
 163 #define CPU_BOOT_DEV_STS0_DEBUG_EN                      (1 << 1)
 164 #define CPU_BOOT_DEV_STS0_WATCHDOG_EN                   (1 << 2)
 165 #define CPU_BOOT_DEV_STS0_DRAM_INIT_EN                  (1 << 3)
 166 #define CPU_BOOT_DEV_STS0_BMC_WAIT_EN                   (1 << 4)
 167 #define CPU_BOOT_DEV_STS0_E2E_CRED_EN                   (1 << 5)
 168 #define CPU_BOOT_DEV_STS0_HBM_CRED_EN                   (1 << 6)
 169 #define CPU_BOOT_DEV_STS0_RL_EN                         (1 << 7)
 170 #define CPU_BOOT_DEV_STS0_SRAM_SCR_EN                   (1 << 8)
 171 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN                   (1 << 9)
 172 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN                (1 << 10)
 173 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN                   (1 << 11)
 174 #define CPU_BOOT_DEV_STS0_ENABLED                       (1 << 31)
 175
 176 enum cpu_boot_status {
 177         CPU_BOOT_STATUS_NA = 0,         /* Default value after reset of chip */
 178         CPU_BOOT_STATUS_IN_WFE = 1,
 179         CPU_BOOT_STATUS_DRAM_RDY = 2,
 180         CPU_BOOT_STATUS_SRAM_AVAIL = 3,
 181         CPU_BOOT_STATUS_IN_BTL = 4,     /* BTL is H/W FSM */
 182         CPU_BOOT_STATUS_IN_PREBOOT = 5,
 183         CPU_BOOT_STATUS_IN_SPL,         /* deprecated - not reported */
 184         CPU_BOOT_STATUS_IN_UBOOT = 7,
 185         CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */
 186         CPU_BOOT_STATUS_FIT_CORRUPTED,  /* deprecated - will be removed */
 187         /* U-Boot console prompt activated, commands are not processed */
 188         CPU_BOOT_STATUS_UBOOT_NOT_READY = 10,
 189         /* Finished NICs init, reported after DRAM and NICs */
 190         CPU_BOOT_STATUS_NIC_FW_RDY = 11,
 191         CPU_BOOT_STATUS_TS_INIT_FAIL,   /* deprecated - will be removed */
 192         CPU_BOOT_STATUS_DRAM_SKIPPED,   /* deprecated - will be removed */
 193         CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */
 194         /* Last boot loader progress status, ready to receive commands */
 195         CPU_BOOT_STATUS_READY_TO_BOOT = 15,
 196         /* Internal Boot finished, ready for boot-fit */
 197         CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16,
 198         /* Internal Security has been initialized, device can be accessed */
 199         CPU_BOOT_STATUS_SECURITY_READY = 17,
 200 };
 201
 202 enum kmd_msg {
 203         KMD_MSG_NA = 0,
 204         KMD_MSG_GOTO_WFE,
 205         KMD_MSG_FIT_RDY,
 206         KMD_MSG_SKIP_BMC,
 207 };
 208
 209 enum cpu_msg_status {
 210         CPU_MSG_CLR = 0,
 211         CPU_MSG_OK,
 212         CPU_MSG_ERR,
 213 };
 214
 215 #endif /* HL_BOOT_IF_H */