1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2021 HabanaLabs, Ltd.
9 #include "../include/hw_ip/mmu/mmu_general.h"
10 #include "../include/hw_ip/mmu/mmu_v1_0.h"
11 #include "../include/goya/asic_reg/goya_masks.h"
12 #include "../include/goya/goya_reg_map.h"
14 #include <linux/pci.h>
15 #include <linux/hwmon.h>
16 #include <linux/iommu.h>
17 #include <linux/seq_file.h>
20 * GOYA security scheme:
22 * 1. Host is protected by:
23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
26 * 2. DRAM is protected by:
27 * - Range registers (protect the first 512MB)
28 * - MMU (isolation between users)
30 * 3. Configuration is protected by:
34 * When MMU is disabled:
36 * QMAN DMA: PQ, CQ, CP, DMA are secured.
37 * PQ, CB and the data are on the host.
40 * PQ, CQ and CP are not secured.
41 * PQ, CB and the data are on the SRAM/DRAM.
43 * Since QMAN DMA is secured, the driver is parsing the DMA CB:
44 * - checks DMA pointer
45 * - WREG, MSG_PROT are not allowed.
46 * - MSG_LONG/SHORT are allowed.
48 * A read/write transaction by the QMAN to a protected area will succeed if
49 * and only if the QMAN's CP is secured and MSG_PROT is used
52 * When MMU is enabled:
54 * QMAN DMA: PQ, CQ and CP are secured.
55 * MMU is set to bypass on the Secure props register of the QMAN.
56 * The reasons we don't enable MMU for PQ, CQ and CP are:
57 * - PQ entry is in kernel address space and the driver doesn't map it.
58 * - CP writes to MSIX register and to kernel address space (completion
61 * DMA is not secured but because CP is secured, the driver still needs to parse
62 * the CB, but doesn't need to check the DMA addresses.
64 * For QMAN DMA 0, DMA is also secured because only the driver uses this DMA and
65 * the driver doesn't map memory in MMU.
67 * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
69 * DMA RR does NOT protect host because DMA is not secured
73 #define GOYA_BOOT_FIT_FILE "habanalabs/goya/goya-boot-fit.itb"
74 #define GOYA_LINUX_FW_FILE "habanalabs/goya/goya-fit.itb"
76 #define GOYA_MMU_REGS_NUM 63
78 #define GOYA_DMA_POOL_BLK_SIZE 0x100 /* 256 bytes */
80 #define GOYA_RESET_TIMEOUT_MSEC 500 /* 500ms */
81 #define GOYA_PLDM_RESET_TIMEOUT_MSEC 20000 /* 20s */
82 #define GOYA_RESET_WAIT_MSEC 1 /* 1ms */
83 #define GOYA_CPU_RESET_WAIT_MSEC 100 /* 100ms */
84 #define GOYA_PLDM_RESET_WAIT_MSEC 1000 /* 1s */
85 #define GOYA_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */
86 #define GOYA_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 100)
87 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC (HL_DEVICE_TIMEOUT_USEC * 30)
88 #define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC 1000000 /* 1s */
89 #define GOYA_MSG_TO_CPU_TIMEOUT_USEC 4000000 /* 4s */
90 #define GOYA_WAIT_FOR_BL_TIMEOUT_USEC 15000000 /* 15s */
92 #define GOYA_QMAN0_FENCE_VAL 0xD169B243
94 #define GOYA_MAX_STRING_LEN 20
96 #define GOYA_CB_POOL_CB_CNT 512
97 #define GOYA_CB_POOL_CB_SIZE 0x20000 /* 128KB */
99 #define IS_QM_IDLE(engine, qm_glbl_sts0) \
100 (((qm_glbl_sts0) & engine##_QM_IDLE_MASK) == engine##_QM_IDLE_MASK)
101 #define IS_DMA_QM_IDLE(qm_glbl_sts0) IS_QM_IDLE(DMA, qm_glbl_sts0)
102 #define IS_TPC_QM_IDLE(qm_glbl_sts0) IS_QM_IDLE(TPC, qm_glbl_sts0)
103 #define IS_MME_QM_IDLE(qm_glbl_sts0) IS_QM_IDLE(MME, qm_glbl_sts0)
105 #define IS_CMDQ_IDLE(engine, cmdq_glbl_sts0) \
106 (((cmdq_glbl_sts0) & engine##_CMDQ_IDLE_MASK) == \
107 engine##_CMDQ_IDLE_MASK)
108 #define IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) \
109 IS_CMDQ_IDLE(TPC, cmdq_glbl_sts0)
110 #define IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) \
111 IS_CMDQ_IDLE(MME, cmdq_glbl_sts0)
113 #define IS_DMA_IDLE(dma_core_sts0) \
114 !((dma_core_sts0) & DMA_CH_0_STS0_DMA_BUSY_MASK)
116 #define IS_TPC_IDLE(tpc_cfg_sts) \
117 (((tpc_cfg_sts) & TPC_CFG_IDLE_MASK) == TPC_CFG_IDLE_MASK)
119 #define IS_MME_IDLE(mme_arch_sts) \
120 (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
122 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
123 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
124 "goya cq 4", "goya cpu eq"
127 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
128 [PACKET_WREG_32] = sizeof(struct packet_wreg32),
129 [PACKET_WREG_BULK] = sizeof(struct packet_wreg_bulk),
130 [PACKET_MSG_LONG] = sizeof(struct packet_msg_long),
131 [PACKET_MSG_SHORT] = sizeof(struct packet_msg_short),
132 [PACKET_CP_DMA] = sizeof(struct packet_cp_dma),
133 [PACKET_MSG_PROT] = sizeof(struct packet_msg_prot),
134 [PACKET_FENCE] = sizeof(struct packet_fence),
135 [PACKET_LIN_DMA] = sizeof(struct packet_lin_dma),
136 [PACKET_NOP] = sizeof(struct packet_nop),
137 [PACKET_STOP] = sizeof(struct packet_stop)
140 static inline bool validate_packet_id(enum packet_id id)
144 case PACKET_WREG_BULK:
145 case PACKET_MSG_LONG:
146 case PACKET_MSG_SHORT:
148 case PACKET_MSG_PROT:
159 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
160 mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
161 mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
162 mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
163 mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
164 mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
165 mmTPC0_QM_GLBL_SECURE_PROPS,
166 mmTPC0_QM_GLBL_NON_SECURE_PROPS,
167 mmTPC0_CMDQ_GLBL_SECURE_PROPS,
168 mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
171 mmTPC1_QM_GLBL_SECURE_PROPS,
172 mmTPC1_QM_GLBL_NON_SECURE_PROPS,
173 mmTPC1_CMDQ_GLBL_SECURE_PROPS,
174 mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
177 mmTPC2_QM_GLBL_SECURE_PROPS,
178 mmTPC2_QM_GLBL_NON_SECURE_PROPS,
179 mmTPC2_CMDQ_GLBL_SECURE_PROPS,
180 mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
183 mmTPC3_QM_GLBL_SECURE_PROPS,
184 mmTPC3_QM_GLBL_NON_SECURE_PROPS,
185 mmTPC3_CMDQ_GLBL_SECURE_PROPS,
186 mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
189 mmTPC4_QM_GLBL_SECURE_PROPS,
190 mmTPC4_QM_GLBL_NON_SECURE_PROPS,
191 mmTPC4_CMDQ_GLBL_SECURE_PROPS,
192 mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
195 mmTPC5_QM_GLBL_SECURE_PROPS,
196 mmTPC5_QM_GLBL_NON_SECURE_PROPS,
197 mmTPC5_CMDQ_GLBL_SECURE_PROPS,
198 mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
201 mmTPC6_QM_GLBL_SECURE_PROPS,
202 mmTPC6_QM_GLBL_NON_SECURE_PROPS,
203 mmTPC6_CMDQ_GLBL_SECURE_PROPS,
204 mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
207 mmTPC7_QM_GLBL_SECURE_PROPS,
208 mmTPC7_QM_GLBL_NON_SECURE_PROPS,
209 mmTPC7_CMDQ_GLBL_SECURE_PROPS,
210 mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
213 mmMME_QM_GLBL_SECURE_PROPS,
214 mmMME_QM_GLBL_NON_SECURE_PROPS,
215 mmMME_CMDQ_GLBL_SECURE_PROPS,
216 mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
217 mmMME_SBA_CONTROL_DATA,
218 mmMME_SBB_CONTROL_DATA,
219 mmMME_SBC_CONTROL_DATA,
220 mmMME_WBC_CONTROL_DATA,
221 mmPCIE_WRAP_PSOC_ARUSER,
222 mmPCIE_WRAP_PSOC_AWUSER
225 static u32 goya_all_events[] = {
226 GOYA_ASYNC_EVENT_ID_PCIE_IF,
227 GOYA_ASYNC_EVENT_ID_TPC0_ECC,
228 GOYA_ASYNC_EVENT_ID_TPC1_ECC,
229 GOYA_ASYNC_EVENT_ID_TPC2_ECC,
230 GOYA_ASYNC_EVENT_ID_TPC3_ECC,
231 GOYA_ASYNC_EVENT_ID_TPC4_ECC,
232 GOYA_ASYNC_EVENT_ID_TPC5_ECC,
233 GOYA_ASYNC_EVENT_ID_TPC6_ECC,
234 GOYA_ASYNC_EVENT_ID_TPC7_ECC,
235 GOYA_ASYNC_EVENT_ID_MME_ECC,
236 GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
237 GOYA_ASYNC_EVENT_ID_MMU_ECC,
238 GOYA_ASYNC_EVENT_ID_DMA_MACRO,
239 GOYA_ASYNC_EVENT_ID_DMA_ECC,
240 GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
241 GOYA_ASYNC_EVENT_ID_PSOC_MEM,
242 GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
243 GOYA_ASYNC_EVENT_ID_SRAM0,
244 GOYA_ASYNC_EVENT_ID_SRAM1,
245 GOYA_ASYNC_EVENT_ID_SRAM2,
246 GOYA_ASYNC_EVENT_ID_SRAM3,
247 GOYA_ASYNC_EVENT_ID_SRAM4,
248 GOYA_ASYNC_EVENT_ID_SRAM5,
249 GOYA_ASYNC_EVENT_ID_SRAM6,
250 GOYA_ASYNC_EVENT_ID_SRAM7,
251 GOYA_ASYNC_EVENT_ID_SRAM8,
252 GOYA_ASYNC_EVENT_ID_SRAM9,
253 GOYA_ASYNC_EVENT_ID_SRAM10,
254 GOYA_ASYNC_EVENT_ID_SRAM11,
255 GOYA_ASYNC_EVENT_ID_SRAM12,
256 GOYA_ASYNC_EVENT_ID_SRAM13,
257 GOYA_ASYNC_EVENT_ID_SRAM14,
258 GOYA_ASYNC_EVENT_ID_SRAM15,
259 GOYA_ASYNC_EVENT_ID_SRAM16,
260 GOYA_ASYNC_EVENT_ID_SRAM17,
261 GOYA_ASYNC_EVENT_ID_SRAM18,
262 GOYA_ASYNC_EVENT_ID_SRAM19,
263 GOYA_ASYNC_EVENT_ID_SRAM20,
264 GOYA_ASYNC_EVENT_ID_SRAM21,
265 GOYA_ASYNC_EVENT_ID_SRAM22,
266 GOYA_ASYNC_EVENT_ID_SRAM23,
267 GOYA_ASYNC_EVENT_ID_SRAM24,
268 GOYA_ASYNC_EVENT_ID_SRAM25,
269 GOYA_ASYNC_EVENT_ID_SRAM26,
270 GOYA_ASYNC_EVENT_ID_SRAM27,
271 GOYA_ASYNC_EVENT_ID_SRAM28,
272 GOYA_ASYNC_EVENT_ID_SRAM29,
273 GOYA_ASYNC_EVENT_ID_GIC500,
274 GOYA_ASYNC_EVENT_ID_PLL0,
275 GOYA_ASYNC_EVENT_ID_PLL1,
276 GOYA_ASYNC_EVENT_ID_PLL3,
277 GOYA_ASYNC_EVENT_ID_PLL4,
278 GOYA_ASYNC_EVENT_ID_PLL5,
279 GOYA_ASYNC_EVENT_ID_PLL6,
280 GOYA_ASYNC_EVENT_ID_AXI_ECC,
281 GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
282 GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
283 GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
284 GOYA_ASYNC_EVENT_ID_PCIE_DEC,
285 GOYA_ASYNC_EVENT_ID_TPC0_DEC,
286 GOYA_ASYNC_EVENT_ID_TPC1_DEC,
287 GOYA_ASYNC_EVENT_ID_TPC2_DEC,
288 GOYA_ASYNC_EVENT_ID_TPC3_DEC,
289 GOYA_ASYNC_EVENT_ID_TPC4_DEC,
290 GOYA_ASYNC_EVENT_ID_TPC5_DEC,
291 GOYA_ASYNC_EVENT_ID_TPC6_DEC,
292 GOYA_ASYNC_EVENT_ID_TPC7_DEC,
293 GOYA_ASYNC_EVENT_ID_MME_WACS,
294 GOYA_ASYNC_EVENT_ID_MME_WACSD,
295 GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
296 GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
297 GOYA_ASYNC_EVENT_ID_PSOC,
298 GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
299 GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
300 GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
301 GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
302 GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
303 GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
304 GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
305 GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
306 GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
307 GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
308 GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
309 GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
310 GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
311 GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
312 GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
313 GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
314 GOYA_ASYNC_EVENT_ID_TPC0_QM,
315 GOYA_ASYNC_EVENT_ID_TPC1_QM,
316 GOYA_ASYNC_EVENT_ID_TPC2_QM,
317 GOYA_ASYNC_EVENT_ID_TPC3_QM,
318 GOYA_ASYNC_EVENT_ID_TPC4_QM,
319 GOYA_ASYNC_EVENT_ID_TPC5_QM,
320 GOYA_ASYNC_EVENT_ID_TPC6_QM,
321 GOYA_ASYNC_EVENT_ID_TPC7_QM,
322 GOYA_ASYNC_EVENT_ID_MME_QM,
323 GOYA_ASYNC_EVENT_ID_MME_CMDQ,
324 GOYA_ASYNC_EVENT_ID_DMA0_QM,
325 GOYA_ASYNC_EVENT_ID_DMA1_QM,
326 GOYA_ASYNC_EVENT_ID_DMA2_QM,
327 GOYA_ASYNC_EVENT_ID_DMA3_QM,
328 GOYA_ASYNC_EVENT_ID_DMA4_QM,
329 GOYA_ASYNC_EVENT_ID_DMA0_CH,
330 GOYA_ASYNC_EVENT_ID_DMA1_CH,
331 GOYA_ASYNC_EVENT_ID_DMA2_CH,
332 GOYA_ASYNC_EVENT_ID_DMA3_CH,
333 GOYA_ASYNC_EVENT_ID_DMA4_CH,
334 GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
335 GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
336 GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
337 GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
338 GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
339 GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
340 GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
341 GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
342 GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
343 GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
344 GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
345 GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
346 GOYA_ASYNC_EVENT_ID_DMA_BM_CH4,
347 GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S,
348 GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E,
349 GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S,
350 GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E
353 static s64 goya_state_dump_specs_props[SP_MAX] = {0};
355 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
356 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
357 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
358 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
360 int goya_set_fixed_properties(struct hl_device *hdev)
362 struct asic_fixed_properties *prop = &hdev->asic_prop;
365 prop->max_queues = GOYA_QUEUE_ID_SIZE;
366 prop->hw_queues_props = kcalloc(prop->max_queues,
367 sizeof(struct hw_queue_properties),
370 if (!prop->hw_queues_props)
373 for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
374 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
375 prop->hw_queues_props[i].driver_only = 0;
376 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
379 for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
380 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
381 prop->hw_queues_props[i].driver_only = 1;
382 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
385 for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
386 NUMBER_OF_INT_HW_QUEUES; i++) {
387 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
388 prop->hw_queues_props[i].driver_only = 0;
389 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER;
392 prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;
393 prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
395 prop->dram_base_address = DRAM_PHYS_BASE;
396 prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
397 prop->dram_end_address = prop->dram_base_address + prop->dram_size;
398 prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
400 prop->sram_base_address = SRAM_BASE_ADDR;
401 prop->sram_size = SRAM_SIZE;
402 prop->sram_end_address = prop->sram_base_address + prop->sram_size;
403 prop->sram_user_base_address = prop->sram_base_address +
404 SRAM_USER_BASE_OFFSET;
406 prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
407 prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
409 prop->mmu_pgt_size = 0x800000; /* 8MB */
411 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
412 prop->mmu_pte_size = HL_PTE_SIZE;
413 prop->mmu_hop_table_size = HOP_TABLE_SIZE_512_PTE;
414 prop->mmu_hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE;
415 prop->dram_page_size = PAGE_SIZE_2MB;
416 prop->dram_supports_virtual_memory = true;
418 prop->dmmu.hop0_shift = MMU_V1_0_HOP0_SHIFT;
419 prop->dmmu.hop1_shift = MMU_V1_0_HOP1_SHIFT;
420 prop->dmmu.hop2_shift = MMU_V1_0_HOP2_SHIFT;
421 prop->dmmu.hop3_shift = MMU_V1_0_HOP3_SHIFT;
422 prop->dmmu.hop4_shift = MMU_V1_0_HOP4_SHIFT;
423 prop->dmmu.hop0_mask = MMU_V1_0_HOP0_MASK;
424 prop->dmmu.hop1_mask = MMU_V1_0_HOP1_MASK;
425 prop->dmmu.hop2_mask = MMU_V1_0_HOP2_MASK;
426 prop->dmmu.hop3_mask = MMU_V1_0_HOP3_MASK;
427 prop->dmmu.hop4_mask = MMU_V1_0_HOP4_MASK;
428 prop->dmmu.start_addr = VA_DDR_SPACE_START;
429 prop->dmmu.end_addr = VA_DDR_SPACE_END;
430 prop->dmmu.page_size = PAGE_SIZE_2MB;
431 prop->dmmu.num_hops = MMU_ARCH_5_HOPS;
432 prop->dmmu.last_mask = LAST_MASK;
434 /* shifts and masks are the same in PMMU and DMMU */
435 memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu));
436 prop->pmmu.start_addr = VA_HOST_SPACE_START;
437 prop->pmmu.end_addr = VA_HOST_SPACE_END;
438 prop->pmmu.page_size = PAGE_SIZE_4KB;
439 prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
440 prop->pmmu.last_mask = LAST_MASK;
442 /* PMMU and HPMMU are the same except of page size */
443 memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
444 prop->pmmu_huge.page_size = PAGE_SIZE_2MB;
446 prop->dram_size_for_default_page_mapping = VA_DDR_SPACE_END;
447 prop->cfg_size = CFG_SIZE;
448 prop->max_asid = MAX_ASID;
449 prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
450 prop->high_pll = PLL_HIGH_DEFAULT;
451 prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
452 prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
453 prop->max_power_default = MAX_POWER_DEFAULT;
454 prop->dc_power_default = DC_POWER_DEFAULT;
455 prop->tpc_enabled_mask = TPC_ENABLED_MASK;
456 prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
457 prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
459 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
462 prop->max_pending_cs = GOYA_MAX_PENDING_CS;
464 prop->first_available_user_msix_interrupt = USHRT_MAX;
466 for (i = 0 ; i < HL_MAX_DCORES ; i++)
467 prop->first_available_cq[i] = USHRT_MAX;
469 prop->fw_cpu_boot_dev_sts0_valid = false;
470 prop->fw_cpu_boot_dev_sts1_valid = false;
471 prop->hard_reset_done_by_fw = false;
472 prop->gic_interrupts_enable = true;
474 prop->server_type = HL_SERVER_TYPE_UNKNOWN;
476 prop->clk_pll_index = HL_GOYA_MME_PLL;
478 prop->use_get_power_for_reset_history = true;
484 * goya_pci_bars_map - Map PCI BARS of Goya device
486 * @hdev: pointer to hl_device structure
488 * Request PCI regions and map them to kernel virtual addresses.
489 * Returns 0 on success
492 static int goya_pci_bars_map(struct hl_device *hdev)
494 static const char * const name[] = {"SRAM_CFG", "MSIX", "DDR"};
495 bool is_wc[3] = {false, false, true};
498 rc = hl_pci_bars_map(hdev, name, is_wc);
502 hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
503 (CFG_BASE - SRAM_BASE_ADDR);
508 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
510 struct goya_device *goya = hdev->asic_specific;
511 struct hl_inbound_pci_region pci_region;
515 if ((goya) && (goya->ddr_bar_cur_addr == addr))
518 /* Inbound Region 1 - Bar 4 - Point to DDR */
519 pci_region.mode = PCI_BAR_MATCH_MODE;
520 pci_region.bar = DDR_BAR_ID;
521 pci_region.addr = addr;
522 rc = hl_pci_set_inbound_region(hdev, 1, &pci_region);
527 old_addr = goya->ddr_bar_cur_addr;
528 goya->ddr_bar_cur_addr = addr;
535 * goya_init_iatu - Initialize the iATU unit inside the PCI controller
537 * @hdev: pointer to hl_device structure
539 * This is needed in case the firmware doesn't initialize the iATU
542 static int goya_init_iatu(struct hl_device *hdev)
544 struct hl_inbound_pci_region inbound_region;
545 struct hl_outbound_pci_region outbound_region;
548 if (hdev->asic_prop.iatu_done_by_fw)
551 /* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */
552 inbound_region.mode = PCI_BAR_MATCH_MODE;
553 inbound_region.bar = SRAM_CFG_BAR_ID;
554 inbound_region.addr = SRAM_BASE_ADDR;
555 rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
559 /* Inbound Region 1 - Bar 4 - Point to DDR */
560 inbound_region.mode = PCI_BAR_MATCH_MODE;
561 inbound_region.bar = DDR_BAR_ID;
562 inbound_region.addr = DRAM_PHYS_BASE;
563 rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
567 hdev->asic_funcs->set_dma_mask_from_fw(hdev);
569 /* Outbound Region 0 - Point to Host */
570 outbound_region.addr = HOST_PHYS_BASE;
571 outbound_region.size = HOST_PHYS_SIZE;
572 rc = hl_pci_set_outbound_region(hdev, &outbound_region);
578 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
580 return RREG32(mmHW_STATE);
584 * goya_early_init - GOYA early initialization code
586 * @hdev: pointer to hl_device structure
590 * PCI controller initialization
594 static int goya_early_init(struct hl_device *hdev)
596 struct asic_fixed_properties *prop = &hdev->asic_prop;
597 struct pci_dev *pdev = hdev->pdev;
598 u32 fw_boot_status, val;
601 rc = goya_set_fixed_properties(hdev);
603 dev_err(hdev->dev, "Failed to get fixed properties\n");
607 /* Check BAR sizes */
608 if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
610 "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
612 (unsigned long long) pci_resource_len(pdev,
616 goto free_queue_props;
619 if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
621 "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
623 (unsigned long long) pci_resource_len(pdev,
627 goto free_queue_props;
630 prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
631 hdev->dram_pci_bar_start = pci_resource_start(pdev, DDR_BAR_ID);
633 /* If FW security is enabled at this point it means no access to ELBI */
634 if (hdev->asic_prop.fw_security_enabled) {
635 hdev->asic_prop.iatu_done_by_fw = true;
639 rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
642 goto free_queue_props;
644 /* Check whether FW is configuring iATU */
645 if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) &&
646 (fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN))
647 hdev->asic_prop.iatu_done_by_fw = true;
650 rc = hl_pci_init(hdev);
652 goto free_queue_props;
654 /* Before continuing in the initialization, we need to read the preboot
655 * version to determine whether we run with a security-enabled firmware
657 rc = hl_fw_read_preboot_status(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS,
659 mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
661 GOYA_BOOT_FIT_REQ_TIMEOUT_USEC);
663 if (hdev->reset_on_preboot_fail)
664 hdev->asic_funcs->hw_fini(hdev, true, false);
668 if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
670 "H/W state is dirty, must reset before initializing\n");
671 hdev->asic_funcs->hw_fini(hdev, true, false);
675 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
676 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
678 "PCI strap is not configured correctly, PCI bus errors may occur\n");
686 kfree(hdev->asic_prop.hw_queues_props);
691 * goya_early_fini - GOYA early finalization code
693 * @hdev: pointer to hl_device structure
698 static int goya_early_fini(struct hl_device *hdev)
700 kfree(hdev->asic_prop.hw_queues_props);
706 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
708 /* mask to zero the MMBP and ASID bits */
709 WREG32_AND(reg, ~0x7FF);
710 WREG32_OR(reg, asid);
713 static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
715 struct goya_device *goya = hdev->asic_specific;
717 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
721 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
723 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
725 RREG32(mmDMA_QM_0_GLBL_PROT);
729 * goya_fetch_psoc_frequency - Fetch PSOC frequency values
731 * @hdev: pointer to hl_device structure
734 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
736 struct asic_fixed_properties *prop = &hdev->asic_prop;
737 u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
738 u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
741 if (hdev->asic_prop.fw_security_enabled) {
742 struct goya_device *goya = hdev->asic_specific;
744 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
747 rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL,
753 freq = pll_freq_arr[1];
755 div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
756 div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
757 nr = RREG32(mmPSOC_PCI_PLL_NR);
758 nf = RREG32(mmPSOC_PCI_PLL_NF);
759 od = RREG32(mmPSOC_PCI_PLL_OD);
761 if (div_sel == DIV_SEL_REF_CLK ||
762 div_sel == DIV_SEL_DIVIDED_REF) {
763 if (div_sel == DIV_SEL_REF_CLK)
766 freq = PLL_REF_CLK / (div_fctr + 1);
767 } else if (div_sel == DIV_SEL_PLL_CLK ||
768 div_sel == DIV_SEL_DIVIDED_PLL) {
769 pll_clk = PLL_REF_CLK * (nf + 1) /
770 ((nr + 1) * (od + 1));
771 if (div_sel == DIV_SEL_PLL_CLK)
774 freq = pll_clk / (div_fctr + 1);
777 "Received invalid div select value: %d",
783 prop->psoc_timestamp_frequency = freq;
784 prop->psoc_pci_pll_nr = nr;
785 prop->psoc_pci_pll_nf = nf;
786 prop->psoc_pci_pll_od = od;
787 prop->psoc_pci_pll_div_factor = div_fctr;
791 * goya_set_frequency - set the frequency of the device
793 * @hdev: pointer to habanalabs device structure
794 * @freq: the new frequency value
796 * Change the frequency if needed. This function has no protection against
797 * concurrency, therefore it is assumed that the calling function has protected
798 * itself against the case of calling this function from multiple threads with
801 * Returns 0 if no change was done, otherwise returns 1
803 int goya_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq)
805 struct goya_device *goya = hdev->asic_specific;
807 if ((goya->pm_mng_profile == PM_MANUAL) ||
808 (goya->curr_pll_profile == freq))
811 dev_dbg(hdev->dev, "Changing device frequency to %s\n",
812 freq == PLL_HIGH ? "high" : "low");
814 goya_set_pll_profile(hdev, freq);
816 goya->curr_pll_profile = freq;
821 static void goya_set_freq_to_low_job(struct work_struct *work)
823 struct goya_work_freq *goya_work = container_of(work,
824 struct goya_work_freq,
826 struct hl_device *hdev = goya_work->hdev;
828 mutex_lock(&hdev->fpriv_list_lock);
830 if (!hdev->is_compute_ctx_active)
831 goya_set_frequency(hdev, PLL_LOW);
833 mutex_unlock(&hdev->fpriv_list_lock);
835 schedule_delayed_work(&goya_work->work_freq,
836 usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));
839 int goya_late_init(struct hl_device *hdev)
841 struct asic_fixed_properties *prop = &hdev->asic_prop;
842 struct goya_device *goya = hdev->asic_specific;
845 goya_fetch_psoc_frequency(hdev);
847 rc = goya_mmu_clear_pgt_range(hdev);
850 "Failed to clear MMU page tables range %d\n", rc);
854 rc = goya_mmu_set_dram_default_page(hdev);
856 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc);
860 rc = goya_mmu_add_mappings_for_device_cpu(hdev);
864 rc = goya_init_cpu_queues(hdev);
868 rc = goya_test_cpu_queue(hdev);
872 rc = goya_cpucp_info_get(hdev);
874 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc);
878 /* Now that we have the DRAM size in ASIC prop, we need to check
879 * its size and configure the DMA_IF DDR wrap protection (which is in
880 * the MMU block) accordingly. The value is the log2 of the DRAM size
882 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
884 rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS);
887 "Failed to enable PCI access from CPU %d\n", rc);
891 /* force setting to low frequency */
892 goya->curr_pll_profile = PLL_LOW;
894 goya->pm_mng_profile = PM_AUTO;
896 hdev->asic_funcs->set_pll_profile(hdev, PLL_LOW);
898 schedule_delayed_work(&goya->goya_work->work_freq,
899 usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));
905 * goya_late_fini - GOYA late tear-down code
907 * @hdev: pointer to hl_device structure
909 * Free sensors allocated structures
911 void goya_late_fini(struct hl_device *hdev)
913 const struct hwmon_channel_info **channel_info_arr;
914 struct goya_device *goya = hdev->asic_specific;
917 cancel_delayed_work_sync(&goya->goya_work->work_freq);
919 if (!hdev->hl_chip_info->info)
922 channel_info_arr = hdev->hl_chip_info->info;
924 while (channel_info_arr[i]) {
925 kfree(channel_info_arr[i]->config);
926 kfree(channel_info_arr[i]);
930 kfree(channel_info_arr);
932 hdev->hl_chip_info->info = NULL;
935 static void goya_set_pci_memory_regions(struct hl_device *hdev)
937 struct asic_fixed_properties *prop = &hdev->asic_prop;
938 struct pci_mem_region *region;
941 region = &hdev->pci_mem_region[PCI_REGION_CFG];
942 region->region_base = CFG_BASE;
943 region->region_size = CFG_SIZE;
944 region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR;
945 region->bar_size = CFG_BAR_SIZE;
946 region->bar_id = SRAM_CFG_BAR_ID;
950 region = &hdev->pci_mem_region[PCI_REGION_SRAM];
951 region->region_base = SRAM_BASE_ADDR;
952 region->region_size = SRAM_SIZE;
953 region->offset_in_bar = 0;
954 region->bar_size = CFG_BAR_SIZE;
955 region->bar_id = SRAM_CFG_BAR_ID;
959 region = &hdev->pci_mem_region[PCI_REGION_DRAM];
960 region->region_base = DRAM_PHYS_BASE;
961 region->region_size = hdev->asic_prop.dram_size;
962 region->offset_in_bar = 0;
963 region->bar_size = prop->dram_pci_bar_size;
964 region->bar_id = DDR_BAR_ID;
969 * goya_sw_init - Goya software initialization code
971 * @hdev: pointer to hl_device structure
974 static int goya_sw_init(struct hl_device *hdev)
976 struct goya_device *goya;
979 /* Allocate device structure */
980 goya = kzalloc(sizeof(*goya), GFP_KERNEL);
984 /* according to goya_init_iatu */
985 goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
987 goya->mme_clk = GOYA_PLL_FREQ_LOW;
988 goya->tpc_clk = GOYA_PLL_FREQ_LOW;
989 goya->ic_clk = GOYA_PLL_FREQ_LOW;
991 hdev->asic_specific = goya;
993 /* Create DMA pool for small allocations */
994 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
995 &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
996 if (!hdev->dma_pool) {
997 dev_err(hdev->dev, "failed to create DMA pool\n");
999 goto free_goya_device;
1002 hdev->cpu_accessible_dma_mem =
1003 hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
1004 HL_CPU_ACCESSIBLE_MEM_SIZE,
1005 &hdev->cpu_accessible_dma_address,
1006 GFP_KERNEL | __GFP_ZERO);
1008 if (!hdev->cpu_accessible_dma_mem) {
1013 dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n",
1014 &hdev->cpu_accessible_dma_address);
1016 hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
1017 if (!hdev->cpu_accessible_dma_pool) {
1019 "Failed to create CPU accessible DMA pool\n");
1021 goto free_cpu_dma_mem;
1024 rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
1025 (uintptr_t) hdev->cpu_accessible_dma_mem,
1026 HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
1029 "Failed to add memory to CPU accessible DMA pool\n");
1031 goto free_cpu_accessible_dma_pool;
1034 spin_lock_init(&goya->hw_queues_lock);
1035 hdev->supports_coresight = true;
1036 hdev->asic_prop.supports_soft_reset = true;
1037 hdev->asic_prop.allow_inference_soft_reset = true;
1038 hdev->supports_wait_for_multi_cs = false;
1040 hdev->asic_funcs->set_pci_memory_regions(hdev);
1042 goya->goya_work = kmalloc(sizeof(struct goya_work_freq), GFP_KERNEL);
1043 if (!goya->goya_work) {
1045 goto free_cpu_accessible_dma_pool;
1048 goya->goya_work->hdev = hdev;
1049 INIT_DELAYED_WORK(&goya->goya_work->work_freq, goya_set_freq_to_low_job);
1053 free_cpu_accessible_dma_pool:
1054 gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1056 hdev->asic_funcs->asic_dma_free_coherent(hdev,
1057 HL_CPU_ACCESSIBLE_MEM_SIZE,
1058 hdev->cpu_accessible_dma_mem,
1059 hdev->cpu_accessible_dma_address);
1061 dma_pool_destroy(hdev->dma_pool);
1069 * goya_sw_fini - Goya software tear-down code
1071 * @hdev: pointer to hl_device structure
1074 static int goya_sw_fini(struct hl_device *hdev)
1076 struct goya_device *goya = hdev->asic_specific;
1078 gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1080 hdev->asic_funcs->asic_dma_free_coherent(hdev,
1081 HL_CPU_ACCESSIBLE_MEM_SIZE,
1082 hdev->cpu_accessible_dma_mem,
1083 hdev->cpu_accessible_dma_address);
1085 dma_pool_destroy(hdev->dma_pool);
1087 kfree(goya->goya_work);
1093 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
1094 dma_addr_t bus_address)
1096 struct goya_device *goya = hdev->asic_specific;
1097 u32 mtr_base_lo, mtr_base_hi;
1098 u32 so_base_lo, so_base_hi;
1099 u32 gic_base_lo, gic_base_hi;
1100 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
1101 u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN;
1103 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1104 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1105 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1106 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1109 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1111 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1113 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
1114 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
1116 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
1117 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1118 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1120 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1121 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1122 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1123 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1124 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1125 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1126 WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
1127 GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
1129 /* PQ has buffer of 2 cache lines, while CQ has 8 lines */
1130 WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
1131 WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
1133 if (goya->hw_cap_initialized & HW_CAP_MMU)
1134 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
1136 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
1138 if (hdev->stop_on_err)
1139 dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT;
1141 WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
1142 WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
1145 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
1147 u32 gic_base_lo, gic_base_hi;
1149 u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
1152 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1154 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1156 WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
1157 WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
1158 WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
1159 GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
1162 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
1165 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
1167 WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1168 WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1172 * goya_init_dma_qmans - Initialize QMAN DMA registers
1174 * @hdev: pointer to hl_device structure
1176 * Initialize the H/W registers of the QMAN DMA channels
1179 void goya_init_dma_qmans(struct hl_device *hdev)
1181 struct goya_device *goya = hdev->asic_specific;
1182 struct hl_hw_queue *q;
1185 if (goya->hw_cap_initialized & HW_CAP_DMA)
1188 q = &hdev->kernel_queues[0];
1190 for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
1191 q->cq_id = q->msi_vec = i;
1192 goya_init_dma_qman(hdev, i, q->bus_address);
1193 goya_init_dma_ch(hdev, i);
1196 goya->hw_cap_initialized |= HW_CAP_DMA;
1200 * goya_disable_external_queues - Disable external queues
1202 * @hdev: pointer to hl_device structure
1205 static void goya_disable_external_queues(struct hl_device *hdev)
1207 struct goya_device *goya = hdev->asic_specific;
1209 if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1212 WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1213 WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1214 WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1215 WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1216 WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1219 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
1220 u32 cp_sts_reg, u32 glbl_sts0_reg)
1225 /* use the values of TPC0 as they are all the same*/
1227 WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1229 status = RREG32(cp_sts_reg);
1230 if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
1231 rc = hl_poll_timeout(
1235 !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
1237 QMAN_FENCE_TIMEOUT_USEC);
1239 /* if QMAN is stuck in fence no need to check for stop */
1244 rc = hl_poll_timeout(
1248 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
1250 QMAN_STOP_TIMEOUT_USEC);
1254 "Timeout while waiting for QMAN to stop\n");
1262 * goya_stop_external_queues - Stop external queues
1264 * @hdev: pointer to hl_device structure
1266 * Returns 0 on success
1269 static int goya_stop_external_queues(struct hl_device *hdev)
1273 struct goya_device *goya = hdev->asic_specific;
1275 if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1278 rc = goya_stop_queue(hdev,
1279 mmDMA_QM_0_GLBL_CFG1,
1281 mmDMA_QM_0_GLBL_STS0);
1284 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
1288 rc = goya_stop_queue(hdev,
1289 mmDMA_QM_1_GLBL_CFG1,
1291 mmDMA_QM_1_GLBL_STS0);
1294 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
1298 rc = goya_stop_queue(hdev,
1299 mmDMA_QM_2_GLBL_CFG1,
1301 mmDMA_QM_2_GLBL_STS0);
1304 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
1308 rc = goya_stop_queue(hdev,
1309 mmDMA_QM_3_GLBL_CFG1,
1311 mmDMA_QM_3_GLBL_STS0);
1314 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
1318 rc = goya_stop_queue(hdev,
1319 mmDMA_QM_4_GLBL_CFG1,
1321 mmDMA_QM_4_GLBL_STS0);
1324 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
1332 * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1334 * @hdev: pointer to hl_device structure
1336 * Returns 0 on success
1339 int goya_init_cpu_queues(struct hl_device *hdev)
1341 struct goya_device *goya = hdev->asic_specific;
1342 struct asic_fixed_properties *prop = &hdev->asic_prop;
1345 struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1348 if (!hdev->cpu_queues_enable)
1351 if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
1354 eq = &hdev->event_queue;
1356 WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1357 WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1359 WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1360 WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1362 WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1363 lower_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1364 WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1365 upper_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1367 WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1368 WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1369 WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1371 /* Used for EQ CI */
1372 WREG32(mmCPU_EQ_CI, 0);
1374 WREG32(mmCPU_IF_PF_PQ_PI, 0);
1376 WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1378 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1379 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1381 err = hl_poll_timeout(
1383 mmCPU_PQ_INIT_STATUS,
1385 (status == PQ_INIT_STATUS_READY_FOR_HOST),
1387 GOYA_CPU_TIMEOUT_USEC);
1391 "Failed to setup communication with device CPU\n");
1395 /* update FW application security bits */
1396 if (prop->fw_cpu_boot_dev_sts0_valid)
1397 prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);
1399 if (prop->fw_cpu_boot_dev_sts1_valid)
1400 prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);
1402 goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1406 static void goya_set_pll_refclk(struct hl_device *hdev)
1408 WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1409 WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1410 WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1411 WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1413 WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1414 WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1415 WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1416 WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1418 WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1419 WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1420 WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1421 WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1423 WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1424 WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1425 WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1426 WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1428 WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1429 WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1430 WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1431 WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1433 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1434 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1435 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1436 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1438 WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1439 WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1440 WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1441 WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1444 static void goya_disable_clk_rlx(struct hl_device *hdev)
1446 WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1447 WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1450 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1452 u64 tpc_eml_address;
1453 u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1456 tpc_offset = tpc_id * 0x40000;
1457 tpc_eml_offset = tpc_id * 0x200000;
1458 tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1459 tpc_slm_offset = tpc_eml_address + 0x100000;
1462 * Workaround for Bug H2 #2443 :
1463 * "TPC SB is not initialized on chip reset"
1466 val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1467 if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1468 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1471 WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1473 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1474 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1475 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1476 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1477 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1478 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1479 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1480 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1481 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1482 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1484 WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1485 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1487 err = hl_poll_timeout(
1489 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1491 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1493 HL_DEVICE_TIMEOUT_USEC);
1497 "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1499 WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1500 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1502 msleep(GOYA_RESET_WAIT_MSEC);
1504 WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1505 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1507 msleep(GOYA_RESET_WAIT_MSEC);
1509 for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1510 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1512 val = RREG32(tpc_slm_offset);
1515 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1517 struct goya_device *goya = hdev->asic_specific;
1523 if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1526 /* Workaround for H2 #2443 */
1528 for (i = 0 ; i < TPC_MAX_NUM ; i++)
1529 _goya_tpc_mbist_workaround(hdev, i);
1531 goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1535 * goya_init_golden_registers - Initialize golden registers
1537 * @hdev: pointer to hl_device structure
1539 * Initialize the H/W registers of the device
1542 static void goya_init_golden_registers(struct hl_device *hdev)
1544 struct goya_device *goya = hdev->asic_specific;
1545 u32 polynom[10], tpc_intr_mask, offset;
1548 if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1551 polynom[0] = 0x00020080;
1552 polynom[1] = 0x00401000;
1553 polynom[2] = 0x00200800;
1554 polynom[3] = 0x00002000;
1555 polynom[4] = 0x00080200;
1556 polynom[5] = 0x00040100;
1557 polynom[6] = 0x00100400;
1558 polynom[7] = 0x00004000;
1559 polynom[8] = 0x00010000;
1560 polynom[9] = 0x00008000;
1562 /* Mask all arithmetic interrupts from TPC */
1563 tpc_intr_mask = 0x7FFF;
1565 for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1566 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1567 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1568 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1569 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1570 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1572 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1573 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1574 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1575 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1576 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1579 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1580 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1581 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1582 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1583 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1585 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1586 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1587 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1588 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1589 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1591 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1592 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1593 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1594 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1595 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1597 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1598 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1599 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1600 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1601 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1604 WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1605 WREG32(mmMME_AGU, 0x0f0f0f10);
1606 WREG32(mmMME_SEI_MASK, ~0x0);
1608 WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1609 WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1610 WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1611 WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1612 WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1613 WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1614 WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1615 WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1616 WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1617 WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1618 WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1619 WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1620 WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1621 WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1622 WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1623 WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1624 WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1625 WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1626 WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1627 WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1628 WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1629 WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1630 WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1631 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1632 WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1633 WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1634 WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1635 WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1636 WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1637 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1638 WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1639 WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1640 WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1641 WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1642 WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1643 WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1644 WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1645 WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1646 WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1647 WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1648 WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1649 WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1650 WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1651 WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1652 WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1653 WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1654 WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1655 WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1656 WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1657 WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1658 WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1659 WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1660 WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1661 WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1662 WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1663 WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1664 WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1665 WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1666 WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1667 WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1668 WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1669 WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1670 WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1671 WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1672 WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1673 WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1674 WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1675 WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1676 WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1677 WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1678 WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1679 WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1680 WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1681 WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1682 WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1683 WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1684 WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1685 WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1686 WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1687 WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1688 WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1689 WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1690 WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1691 WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1693 WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1694 WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1695 WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1696 WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1697 WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1698 WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1699 WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1700 WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1701 WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1702 WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1703 WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1704 WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1706 WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1707 WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1708 WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1709 WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1710 WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1711 WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1712 WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1713 WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1714 WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1715 WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1716 WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1717 WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1719 WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1720 WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1721 WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1722 WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1723 WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1724 WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1725 WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1726 WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1727 WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1728 WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1729 WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1730 WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1732 WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1733 WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1734 WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1735 WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1736 WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1737 WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1738 WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1739 WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1740 WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1741 WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1742 WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1743 WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1745 WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1746 WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1747 WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1748 WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1749 WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1750 WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1751 WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1752 WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1753 WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1754 WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1755 WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1756 WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1758 WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1759 WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1760 WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1761 WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1762 WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1763 WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1764 WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1765 WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1766 WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1767 WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1768 WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1769 WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1771 for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1772 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1773 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1774 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1775 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1776 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1777 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1779 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1780 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1781 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1782 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1783 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1784 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1785 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1786 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1788 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1789 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1792 for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1793 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1794 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1795 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1796 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1799 for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1801 * Workaround for Bug H2 #2441 :
1802 * "ST.NOP set trace event illegal opcode"
1804 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1806 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1807 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1808 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1809 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1811 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset,
1812 ICACHE_FETCH_LINE_NUM, 2);
1815 WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1816 WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1817 1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1819 WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1820 WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1821 1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1824 * Workaround for H2 #HW-23 bug
1825 * Set DMA max outstanding read requests to 240 on DMA CH 1.
1826 * This limitation is still large enough to not affect Gen4 bandwidth.
1827 * We need to only limit that DMA channel because the user can only read
1828 * from Host using DMA CH 1
1830 WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1832 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1834 goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1837 static void goya_init_mme_qman(struct hl_device *hdev)
1839 u32 mtr_base_lo, mtr_base_hi;
1840 u32 so_base_lo, so_base_hi;
1841 u32 gic_base_lo, gic_base_hi;
1844 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1845 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1846 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1847 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1850 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1852 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1854 qman_base_addr = hdev->asic_prop.sram_base_address +
1855 MME_QMAN_BASE_OFFSET;
1857 WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1858 WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1859 WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1860 WREG32(mmMME_QM_PQ_PI, 0);
1861 WREG32(mmMME_QM_PQ_CI, 0);
1862 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1863 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1864 WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1865 WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1867 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1868 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1869 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1870 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1872 /* QMAN CQ has 8 cache lines */
1873 WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1875 WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1876 WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1878 WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1880 WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1882 WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1884 WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1887 static void goya_init_mme_cmdq(struct hl_device *hdev)
1889 u32 mtr_base_lo, mtr_base_hi;
1890 u32 so_base_lo, so_base_hi;
1891 u32 gic_base_lo, gic_base_hi;
1893 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1894 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1895 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1896 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1899 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1901 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1903 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1904 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1905 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1906 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1908 /* CMDQ CQ has 20 cache lines */
1909 WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1911 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1912 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1914 WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1916 WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1918 WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1920 WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1923 void goya_init_mme_qmans(struct hl_device *hdev)
1925 struct goya_device *goya = hdev->asic_specific;
1926 u32 so_base_lo, so_base_hi;
1928 if (goya->hw_cap_initialized & HW_CAP_MME)
1931 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1932 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1934 WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1935 WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1937 goya_init_mme_qman(hdev);
1938 goya_init_mme_cmdq(hdev);
1940 goya->hw_cap_initialized |= HW_CAP_MME;
1943 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1945 u32 mtr_base_lo, mtr_base_hi;
1946 u32 so_base_lo, so_base_hi;
1947 u32 gic_base_lo, gic_base_hi;
1949 u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1951 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1952 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1953 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1954 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1957 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1959 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1961 qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1963 WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1964 WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1965 WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1966 WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1967 WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1968 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1969 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1970 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1971 WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1973 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1974 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1975 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1976 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1978 WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1980 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1981 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1983 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1984 GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1986 WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1988 WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1990 WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1993 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1995 u32 mtr_base_lo, mtr_base_hi;
1996 u32 so_base_lo, so_base_hi;
1997 u32 gic_base_lo, gic_base_hi;
1998 u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
2000 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
2001 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
2002 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
2003 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
2006 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
2008 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
2010 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
2011 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
2012 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
2013 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
2015 WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
2017 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
2018 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
2020 WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
2021 GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
2023 WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
2025 WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
2027 WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
2030 void goya_init_tpc_qmans(struct hl_device *hdev)
2032 struct goya_device *goya = hdev->asic_specific;
2033 u32 so_base_lo, so_base_hi;
2034 u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
2035 mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
2038 if (goya->hw_cap_initialized & HW_CAP_TPC)
2041 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
2042 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
2044 for (i = 0 ; i < TPC_MAX_NUM ; i++) {
2045 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
2047 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
2051 goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
2052 goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
2053 goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
2054 goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
2055 goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
2056 goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
2057 goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
2058 goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
2060 for (i = 0 ; i < TPC_MAX_NUM ; i++)
2061 goya_init_tpc_cmdq(hdev, i);
2063 goya->hw_cap_initialized |= HW_CAP_TPC;
2067 * goya_disable_internal_queues - Disable internal queues
2069 * @hdev: pointer to hl_device structure
2072 static void goya_disable_internal_queues(struct hl_device *hdev)
2074 struct goya_device *goya = hdev->asic_specific;
2076 if (!(goya->hw_cap_initialized & HW_CAP_MME))
2079 WREG32(mmMME_QM_GLBL_CFG0, 0);
2080 WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
2083 if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2086 WREG32(mmTPC0_QM_GLBL_CFG0, 0);
2087 WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
2089 WREG32(mmTPC1_QM_GLBL_CFG0, 0);
2090 WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
2092 WREG32(mmTPC2_QM_GLBL_CFG0, 0);
2093 WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
2095 WREG32(mmTPC3_QM_GLBL_CFG0, 0);
2096 WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
2098 WREG32(mmTPC4_QM_GLBL_CFG0, 0);
2099 WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
2101 WREG32(mmTPC5_QM_GLBL_CFG0, 0);
2102 WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
2104 WREG32(mmTPC6_QM_GLBL_CFG0, 0);
2105 WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
2107 WREG32(mmTPC7_QM_GLBL_CFG0, 0);
2108 WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
2112 * goya_stop_internal_queues - Stop internal queues
2114 * @hdev: pointer to hl_device structure
2116 * Returns 0 on success
2119 static int goya_stop_internal_queues(struct hl_device *hdev)
2121 struct goya_device *goya = hdev->asic_specific;
2124 if (!(goya->hw_cap_initialized & HW_CAP_MME))
2128 * Each queue (QMAN) is a separate H/W logic. That means that each
2129 * QMAN can be stopped independently and failure to stop one does NOT
2130 * mandate we should not try to stop other QMANs
2133 rc = goya_stop_queue(hdev,
2136 mmMME_QM_GLBL_STS0);
2139 dev_err(hdev->dev, "failed to stop MME QMAN\n");
2143 rc = goya_stop_queue(hdev,
2144 mmMME_CMDQ_GLBL_CFG1,
2146 mmMME_CMDQ_GLBL_STS0);
2149 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
2154 if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2157 rc = goya_stop_queue(hdev,
2158 mmTPC0_QM_GLBL_CFG1,
2160 mmTPC0_QM_GLBL_STS0);
2163 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
2167 rc = goya_stop_queue(hdev,
2168 mmTPC0_CMDQ_GLBL_CFG1,
2170 mmTPC0_CMDQ_GLBL_STS0);
2173 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
2177 rc = goya_stop_queue(hdev,
2178 mmTPC1_QM_GLBL_CFG1,
2180 mmTPC1_QM_GLBL_STS0);
2183 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
2187 rc = goya_stop_queue(hdev,
2188 mmTPC1_CMDQ_GLBL_CFG1,
2190 mmTPC1_CMDQ_GLBL_STS0);
2193 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
2197 rc = goya_stop_queue(hdev,
2198 mmTPC2_QM_GLBL_CFG1,
2200 mmTPC2_QM_GLBL_STS0);
2203 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
2207 rc = goya_stop_queue(hdev,
2208 mmTPC2_CMDQ_GLBL_CFG1,
2210 mmTPC2_CMDQ_GLBL_STS0);
2213 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
2217 rc = goya_stop_queue(hdev,
2218 mmTPC3_QM_GLBL_CFG1,
2220 mmTPC3_QM_GLBL_STS0);
2223 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
2227 rc = goya_stop_queue(hdev,
2228 mmTPC3_CMDQ_GLBL_CFG1,
2230 mmTPC3_CMDQ_GLBL_STS0);
2233 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
2237 rc = goya_stop_queue(hdev,
2238 mmTPC4_QM_GLBL_CFG1,
2240 mmTPC4_QM_GLBL_STS0);
2243 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
2247 rc = goya_stop_queue(hdev,
2248 mmTPC4_CMDQ_GLBL_CFG1,
2250 mmTPC4_CMDQ_GLBL_STS0);
2253 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
2257 rc = goya_stop_queue(hdev,
2258 mmTPC5_QM_GLBL_CFG1,
2260 mmTPC5_QM_GLBL_STS0);
2263 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
2267 rc = goya_stop_queue(hdev,
2268 mmTPC5_CMDQ_GLBL_CFG1,
2270 mmTPC5_CMDQ_GLBL_STS0);
2273 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
2277 rc = goya_stop_queue(hdev,
2278 mmTPC6_QM_GLBL_CFG1,
2280 mmTPC6_QM_GLBL_STS0);
2283 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
2287 rc = goya_stop_queue(hdev,
2288 mmTPC6_CMDQ_GLBL_CFG1,
2290 mmTPC6_CMDQ_GLBL_STS0);
2293 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
2297 rc = goya_stop_queue(hdev,
2298 mmTPC7_QM_GLBL_CFG1,
2300 mmTPC7_QM_GLBL_STS0);
2303 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
2307 rc = goya_stop_queue(hdev,
2308 mmTPC7_CMDQ_GLBL_CFG1,
2310 mmTPC7_CMDQ_GLBL_STS0);
2313 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
2320 static void goya_dma_stall(struct hl_device *hdev)
2322 struct goya_device *goya = hdev->asic_specific;
2324 if (!(goya->hw_cap_initialized & HW_CAP_DMA))
2327 WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2328 WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2329 WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2330 WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2331 WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2334 static void goya_tpc_stall(struct hl_device *hdev)
2336 struct goya_device *goya = hdev->asic_specific;
2338 if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2341 WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2342 WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2343 WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2344 WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2345 WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2346 WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2347 WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2348 WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2351 static void goya_mme_stall(struct hl_device *hdev)
2353 struct goya_device *goya = hdev->asic_specific;
2355 if (!(goya->hw_cap_initialized & HW_CAP_MME))
2358 WREG32(mmMME_STALL, 0xFFFFFFFF);
2361 static int goya_enable_msix(struct hl_device *hdev)
2363 struct goya_device *goya = hdev->asic_specific;
2364 int cq_cnt = hdev->asic_prop.completion_queues_count;
2365 int rc, i, irq_cnt_init, irq;
2367 if (goya->hw_cap_initialized & HW_CAP_MSIX)
2370 rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
2371 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
2374 "MSI-X: Failed to enable support -- %d/%d\n",
2375 GOYA_MSIX_ENTRIES, rc);
2379 for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
2380 irq = pci_irq_vector(hdev->pdev, i);
2381 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
2382 &hdev->completion_queue[i]);
2384 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2389 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2391 rc = request_irq(irq, hl_irq_handler_eq, 0,
2392 goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
2393 &hdev->event_queue);
2395 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2399 goya->hw_cap_initialized |= HW_CAP_MSIX;
2403 for (i = 0 ; i < irq_cnt_init ; i++)
2404 free_irq(pci_irq_vector(hdev->pdev, i),
2405 &hdev->completion_queue[i]);
2407 pci_free_irq_vectors(hdev->pdev);
2411 static void goya_sync_irqs(struct hl_device *hdev)
2413 struct goya_device *goya = hdev->asic_specific;
2416 if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2419 /* Wait for all pending IRQs to be finished */
2420 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2421 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2423 synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
2426 static void goya_disable_msix(struct hl_device *hdev)
2428 struct goya_device *goya = hdev->asic_specific;
2431 if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2434 goya_sync_irqs(hdev);
2436 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2437 free_irq(irq, &hdev->event_queue);
2439 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2440 irq = pci_irq_vector(hdev->pdev, i);
2441 free_irq(irq, &hdev->completion_queue[i]);
2444 pci_free_irq_vectors(hdev->pdev);
2446 goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2449 static void goya_enable_timestamp(struct hl_device *hdev)
2451 /* Disable the timestamp counter */
2452 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2454 /* Zero the lower/upper parts of the 64-bit counter */
2455 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2456 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2458 /* Enable the counter */
2459 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2462 static void goya_disable_timestamp(struct hl_device *hdev)
2464 /* Disable the timestamp counter */
2465 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2468 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2470 u32 wait_timeout_ms;
2473 "Halting compute engines and disabling interrupts\n");
2476 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2478 wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2480 goya_stop_external_queues(hdev);
2481 goya_stop_internal_queues(hdev);
2483 msleep(wait_timeout_ms);
2485 goya_dma_stall(hdev);
2486 goya_tpc_stall(hdev);
2487 goya_mme_stall(hdev);
2489 msleep(wait_timeout_ms);
2491 goya_disable_external_queues(hdev);
2492 goya_disable_internal_queues(hdev);
2494 goya_disable_timestamp(hdev);
2497 goya_disable_msix(hdev);
2498 goya_mmu_remove_device_cpu_mappings(hdev);
2500 goya_sync_irqs(hdev);
2505 * goya_load_firmware_to_device() - Load LINUX FW code to device.
2506 * @hdev: Pointer to hl_device structure.
2508 * Copy LINUX fw code from firmware file to HBM BAR.
2510 * Return: 0 on success, non-zero for failure.
2512 static int goya_load_firmware_to_device(struct hl_device *hdev)
2516 dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2518 return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst, 0, 0);
2522 * goya_load_boot_fit_to_device() - Load boot fit to device.
2523 * @hdev: Pointer to hl_device structure.
2525 * Copy boot fit file to SRAM BAR.
2527 * Return: 0 on success, non-zero for failure.
2529 static int goya_load_boot_fit_to_device(struct hl_device *hdev)
2533 dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
2535 return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0);
2538 static void goya_init_dynamic_firmware_loader(struct hl_device *hdev)
2540 struct dynamic_fw_load_mgr *dynamic_loader;
2541 struct cpu_dyn_regs *dyn_regs;
2543 dynamic_loader = &hdev->fw_loader.dynamic_loader;
2546 * here we update initial values for few specific dynamic regs (as
2547 * before reading the first descriptor from FW those value has to be
2548 * hard-coded) in later stages of the protocol those values will be
2549 * updated automatically by reading the FW descriptor so data there
2550 * will always be up-to-date
2552 dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs;
2553 dyn_regs->kmd_msg_to_cpu =
2554 cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
2555 dyn_regs->cpu_cmd_status_to_host =
2556 cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
2558 dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC;
2561 static void goya_init_static_firmware_loader(struct hl_device *hdev)
2563 struct static_fw_load_mgr *static_loader;
2565 static_loader = &hdev->fw_loader.static_loader;
2567 static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2568 static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2569 static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
2570 static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
2571 static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
2572 static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0;
2573 static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1;
2574 static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
2575 static_loader->boot_err1_reg = mmCPU_BOOT_ERR1;
2576 static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
2577 static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
2578 static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR));
2581 static void goya_init_firmware_loader(struct hl_device *hdev)
2583 struct asic_fixed_properties *prop = &hdev->asic_prop;
2584 struct fw_load_mgr *fw_loader = &hdev->fw_loader;
2586 /* fill common fields */
2587 fw_loader->fw_comp_loaded = FW_TYPE_NONE;
2588 fw_loader->boot_fit_img.image_name = GOYA_BOOT_FIT_FILE;
2589 fw_loader->linux_img.image_name = GOYA_LINUX_FW_FILE;
2590 fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC;
2591 fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
2592 fw_loader->skip_bmc = false;
2593 fw_loader->sram_bar_id = SRAM_CFG_BAR_ID;
2594 fw_loader->dram_bar_id = DDR_BAR_ID;
2596 if (prop->dynamic_fw_load)
2597 goya_init_dynamic_firmware_loader(hdev);
2599 goya_init_static_firmware_loader(hdev);
2602 static int goya_init_cpu(struct hl_device *hdev)
2604 struct goya_device *goya = hdev->asic_specific;
2607 if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
2610 if (goya->hw_cap_initialized & HW_CAP_CPU)
2614 * Before pushing u-boot/linux to device, need to set the ddr bar to
2615 * base address of dram
2617 if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
2619 "failed to map DDR bar to DRAM base address\n");
2623 rc = hl_fw_init_cpu(hdev);
2628 goya->hw_cap_initialized |= HW_CAP_CPU;
2633 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
2636 u32 status, timeout_usec;
2640 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
2642 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
2644 WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2645 WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2646 WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2648 rc = hl_poll_timeout(
2652 !(status & 0x80000000),
2658 "Timeout during MMU hop0 config of asid %d\n", asid);
2665 int goya_mmu_init(struct hl_device *hdev)
2667 struct asic_fixed_properties *prop = &hdev->asic_prop;
2668 struct goya_device *goya = hdev->asic_specific;
2672 if (!hdev->mmu_enable)
2675 if (goya->hw_cap_initialized & HW_CAP_MMU)
2678 hdev->dram_default_page_mapping = true;
2680 for (i = 0 ; i < prop->max_asid ; i++) {
2681 hop0_addr = prop->mmu_pgt_addr +
2682 (i * prop->mmu_hop_table_size);
2684 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2687 "failed to set hop0 addr for asid %d\n", i);
2692 goya->hw_cap_initialized |= HW_CAP_MMU;
2694 /* init MMU cache manage page */
2695 WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2696 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2697 WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2699 /* Remove follower feature due to performance bug */
2700 WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2701 (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2703 hdev->asic_funcs->mmu_invalidate_cache(hdev, true,
2704 MMU_OP_USERPTR | MMU_OP_PHYS_PACK);
2706 WREG32(mmMMU_MMU_ENABLE, 1);
2707 WREG32(mmMMU_SPI_MASK, 0xF);
2716 * goya_hw_init - Goya hardware initialization code
2718 * @hdev: pointer to hl_device structure
2720 * Returns 0 on success
2723 static int goya_hw_init(struct hl_device *hdev)
2725 struct asic_fixed_properties *prop = &hdev->asic_prop;
2728 /* Perform read from the device to make sure device is up */
2729 RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2732 * Let's mark in the H/W that we have reached this point. We check
2733 * this value in the reset_before_init function to understand whether
2734 * we need to reset the chip before doing H/W init. This register is
2735 * cleared by the H/W upon H/W reset
2737 WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2739 rc = goya_init_cpu(hdev);
2741 dev_err(hdev->dev, "failed to initialize CPU\n");
2745 goya_tpc_mbist_workaround(hdev);
2747 goya_init_golden_registers(hdev);
2750 * After CPU initialization is finished, change DDR bar mapping inside
2751 * iATU to point to the start address of the MMU page tables
2753 if (goya_set_ddr_bar_base(hdev, (MMU_PAGE_TABLES_ADDR &
2754 ~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) {
2756 "failed to map DDR bar to MMU page tables\n");
2760 rc = goya_mmu_init(hdev);
2764 goya_init_security(hdev);
2766 goya_init_dma_qmans(hdev);
2768 goya_init_mme_qmans(hdev);
2770 goya_init_tpc_qmans(hdev);
2772 goya_enable_timestamp(hdev);
2774 /* MSI-X must be enabled before CPU queues are initialized */
2775 rc = goya_enable_msix(hdev);
2777 goto disable_queues;
2779 /* Perform read from the device to flush all MSI-X configuration */
2780 RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2785 goya_disable_internal_queues(hdev);
2786 goya_disable_external_queues(hdev);
2791 static void goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2793 struct goya_device *goya = hdev->asic_specific;
2794 u32 reset_timeout_ms, cpu_timeout_ms, status;
2797 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2798 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2800 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2801 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2805 /* I don't know what is the state of the CPU so make sure it is
2806 * stopped in any means necessary
2808 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2809 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2810 GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2812 msleep(cpu_timeout_ms);
2814 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2815 goya_disable_clk_rlx(hdev);
2816 goya_set_pll_refclk(hdev);
2818 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2820 "Issued HARD reset command, going to wait %dms\n",
2823 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2825 "Issued SOFT reset command, going to wait %dms\n",
2830 * After hard reset, we can't poll the BTM_FSM register because the PSOC
2831 * itself is in reset. In either reset we need to wait until the reset
2834 msleep(reset_timeout_ms);
2836 status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2837 if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
2839 "Timeout while waiting for device to reset 0x%x\n",
2842 if (!hard_reset && goya) {
2843 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2844 HW_CAP_GOLDEN | HW_CAP_TPC);
2845 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2846 GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2850 /* Chicken bit to re-initiate boot sequencer flow */
2851 WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2852 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2853 /* Move boot manager FSM to pre boot sequencer init state */
2854 WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2855 0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2858 goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2859 HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2860 HW_CAP_DMA | HW_CAP_MME |
2861 HW_CAP_MMU | HW_CAP_TPC_MBIST |
2862 HW_CAP_GOLDEN | HW_CAP_TPC);
2864 memset(goya->events_stat, 0, sizeof(goya->events_stat));
2868 int goya_suspend(struct hl_device *hdev)
2872 rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS);
2874 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2879 int goya_resume(struct hl_device *hdev)
2881 return goya_init_iatu(hdev);
2884 static int goya_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2885 void *cpu_addr, dma_addr_t dma_addr, size_t size)
2889 vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2890 VM_DONTCOPY | VM_NORESERVE;
2892 rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr,
2893 (dma_addr - HOST_PHYS_BASE), size);
2895 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
2900 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2902 u32 db_reg_offset, db_value;
2904 switch (hw_queue_id) {
2905 case GOYA_QUEUE_ID_DMA_0:
2906 db_reg_offset = mmDMA_QM_0_PQ_PI;
2909 case GOYA_QUEUE_ID_DMA_1:
2910 db_reg_offset = mmDMA_QM_1_PQ_PI;
2913 case GOYA_QUEUE_ID_DMA_2:
2914 db_reg_offset = mmDMA_QM_2_PQ_PI;
2917 case GOYA_QUEUE_ID_DMA_3:
2918 db_reg_offset = mmDMA_QM_3_PQ_PI;
2921 case GOYA_QUEUE_ID_DMA_4:
2922 db_reg_offset = mmDMA_QM_4_PQ_PI;
2925 case GOYA_QUEUE_ID_CPU_PQ:
2926 db_reg_offset = mmCPU_IF_PF_PQ_PI;
2929 case GOYA_QUEUE_ID_MME:
2930 db_reg_offset = mmMME_QM_PQ_PI;
2933 case GOYA_QUEUE_ID_TPC0:
2934 db_reg_offset = mmTPC0_QM_PQ_PI;
2937 case GOYA_QUEUE_ID_TPC1:
2938 db_reg_offset = mmTPC1_QM_PQ_PI;
2941 case GOYA_QUEUE_ID_TPC2:
2942 db_reg_offset = mmTPC2_QM_PQ_PI;
2945 case GOYA_QUEUE_ID_TPC3:
2946 db_reg_offset = mmTPC3_QM_PQ_PI;
2949 case GOYA_QUEUE_ID_TPC4:
2950 db_reg_offset = mmTPC4_QM_PQ_PI;
2953 case GOYA_QUEUE_ID_TPC5:
2954 db_reg_offset = mmTPC5_QM_PQ_PI;
2957 case GOYA_QUEUE_ID_TPC6:
2958 db_reg_offset = mmTPC6_QM_PQ_PI;
2961 case GOYA_QUEUE_ID_TPC7:
2962 db_reg_offset = mmTPC7_QM_PQ_PI;
2966 /* Should never get here */
2967 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n",
2974 /* ring the doorbell */
2975 WREG32(db_reg_offset, db_value);
2977 if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ) {
2978 /* make sure device CPU will read latest data from host */
2980 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2981 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2985 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
2987 /* The QMANs are on the SRAM so need to copy to IO space */
2988 memcpy_toio((void __iomem *) pqe, bd, sizeof(struct hl_bd));
2991 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2992 dma_addr_t *dma_handle, gfp_t flags)
2994 void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
2997 /* Shift to the device's base physical address of host memory */
2999 *dma_handle += HOST_PHYS_BASE;
3004 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
3005 void *cpu_addr, dma_addr_t dma_handle)
3007 /* Cancel the device's base physical address of host memory */
3008 dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
3010 dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
3013 int goya_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size)
3018 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
3019 dma_addr_t *dma_handle, u16 *queue_len)
3024 *dma_handle = hdev->asic_prop.sram_base_address;
3026 base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
3029 case GOYA_QUEUE_ID_MME:
3030 offset = MME_QMAN_BASE_OFFSET;
3031 *queue_len = MME_QMAN_LENGTH;
3033 case GOYA_QUEUE_ID_TPC0:
3034 offset = TPC0_QMAN_BASE_OFFSET;
3035 *queue_len = TPC_QMAN_LENGTH;
3037 case GOYA_QUEUE_ID_TPC1:
3038 offset = TPC1_QMAN_BASE_OFFSET;
3039 *queue_len = TPC_QMAN_LENGTH;
3041 case GOYA_QUEUE_ID_TPC2:
3042 offset = TPC2_QMAN_BASE_OFFSET;
3043 *queue_len = TPC_QMAN_LENGTH;
3045 case GOYA_QUEUE_ID_TPC3:
3046 offset = TPC3_QMAN_BASE_OFFSET;
3047 *queue_len = TPC_QMAN_LENGTH;
3049 case GOYA_QUEUE_ID_TPC4:
3050 offset = TPC4_QMAN_BASE_OFFSET;
3051 *queue_len = TPC_QMAN_LENGTH;
3053 case GOYA_QUEUE_ID_TPC5:
3054 offset = TPC5_QMAN_BASE_OFFSET;
3055 *queue_len = TPC_QMAN_LENGTH;
3057 case GOYA_QUEUE_ID_TPC6:
3058 offset = TPC6_QMAN_BASE_OFFSET;
3059 *queue_len = TPC_QMAN_LENGTH;
3061 case GOYA_QUEUE_ID_TPC7:
3062 offset = TPC7_QMAN_BASE_OFFSET;
3063 *queue_len = TPC_QMAN_LENGTH;
3066 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
3071 *dma_handle += offset;
3076 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
3078 struct packet_msg_prot *fence_pkt;
3080 dma_addr_t fence_dma_addr;
3086 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
3088 timeout = HL_DEVICE_TIMEOUT_USEC;
3090 if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) {
3091 dev_err_ratelimited(hdev->dev,
3092 "Can't send driver job on QMAN0 because the device is not idle\n");
3096 fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3100 "Failed to allocate fence memory for QMAN0\n");
3104 goya_qman0_set_security(hdev, true);
3106 cb = job->patched_cb;
3108 fence_pkt = cb->kernel_address +
3109 job->job_cb_size - sizeof(struct packet_msg_prot);
3111 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3112 (1 << GOYA_PKT_CTL_EB_SHIFT) |
3113 (1 << GOYA_PKT_CTL_MB_SHIFT);
3114 fence_pkt->ctl = cpu_to_le32(tmp);
3115 fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
3116 fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3118 rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
3119 job->job_cb_size, cb->bus_address);
3121 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
3122 goto free_fence_ptr;
3125 rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
3126 (tmp == GOYA_QMAN0_FENCE_VAL), 1000,
3129 hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
3131 if (rc == -ETIMEDOUT) {
3132 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
3133 goto free_fence_ptr;
3137 hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
3140 goya_qman0_set_security(hdev, false);
3145 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
3146 u32 timeout, u64 *result)
3148 struct goya_device *goya = hdev->asic_specific;
3150 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
3157 timeout = GOYA_MSG_TO_CPU_TIMEOUT_USEC;
3159 return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
3163 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
3165 struct packet_msg_prot *fence_pkt;
3166 dma_addr_t pkt_dma_addr;
3168 dma_addr_t fence_dma_addr;
3172 fence_val = GOYA_QMAN0_FENCE_VAL;
3174 fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3178 "Failed to allocate memory for H/W queue %d testing\n",
3185 fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev,
3186 sizeof(struct packet_msg_prot),
3187 GFP_KERNEL, &pkt_dma_addr);
3190 "Failed to allocate packet for H/W queue %d testing\n",
3193 goto free_fence_ptr;
3196 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3197 (1 << GOYA_PKT_CTL_EB_SHIFT) |
3198 (1 << GOYA_PKT_CTL_MB_SHIFT);
3199 fence_pkt->ctl = cpu_to_le32(tmp);
3200 fence_pkt->value = cpu_to_le32(fence_val);
3201 fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3203 rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
3204 sizeof(struct packet_msg_prot),
3208 "Failed to send fence packet to H/W queue %d\n",
3213 rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
3214 1000, GOYA_TEST_QUEUE_WAIT_USEC, true);
3216 hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
3218 if (rc == -ETIMEDOUT) {
3220 "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
3221 hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
3226 hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt,
3229 hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
3234 int goya_test_cpu_queue(struct hl_device *hdev)
3236 struct goya_device *goya = hdev->asic_specific;
3239 * check capability here as send_cpu_message() won't update the result
3240 * value if no capability
3242 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
3245 return hl_fw_test_cpu_queue(hdev);
3248 int goya_test_queues(struct hl_device *hdev)
3250 int i, rc, ret_val = 0;
3252 for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
3253 rc = goya_test_queue(hdev, i);
3261 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3262 gfp_t mem_flags, dma_addr_t *dma_handle)
3266 if (size > GOYA_DMA_POOL_BLK_SIZE)
3269 kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3271 /* Shift to the device's base physical address of host memory */
3273 *dma_handle += HOST_PHYS_BASE;
3278 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3279 dma_addr_t dma_addr)
3281 /* Cancel the device's base physical address of host memory */
3282 dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
3284 dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
3287 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
3288 dma_addr_t *dma_handle)
3292 vaddr = hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
3293 *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address +
3294 VA_CPU_ACCESSIBLE_MEM_ADDR;
3299 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
3302 hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
3305 static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl,
3306 int nents, enum dma_data_direction dir)
3308 struct scatterlist *sg;
3311 if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir))
3314 /* Shift to the device's base physical address of host memory */
3315 for_each_sg(sgl, sg, nents, i)
3316 sg->dma_address += HOST_PHYS_BASE;
3321 static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl,
3322 int nents, enum dma_data_direction dir)
3324 struct scatterlist *sg;
3327 /* Cancel the device's base physical address of host memory */
3328 for_each_sg(sgl, sg, nents, i)
3329 sg->dma_address -= HOST_PHYS_BASE;
3331 dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir);
3334 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3336 struct scatterlist *sg, *sg_next_iter;
3337 u32 count, dma_desc_cnt;
3339 dma_addr_t addr, addr_next;
3343 for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3345 len = sg_dma_len(sg);
3346 addr = sg_dma_address(sg);
3351 while ((count + 1) < sgt->nents) {
3352 sg_next_iter = sg_next(sg);
3353 len_next = sg_dma_len(sg_next_iter);
3354 addr_next = sg_dma_address(sg_next_iter);
3359 if ((addr + len == addr_next) &&
3360 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3372 return dma_desc_cnt * sizeof(struct packet_lin_dma);
3375 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3376 struct hl_cs_parser *parser,
3377 struct packet_lin_dma *user_dma_pkt,
3378 u64 addr, enum dma_data_direction dir)
3380 struct hl_userptr *userptr;
3383 if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3384 parser->job_userptr_list, &userptr))
3385 goto already_pinned;
3387 userptr = kzalloc(sizeof(*userptr), GFP_KERNEL);
3391 rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3396 list_add_tail(&userptr->job_node, parser->job_userptr_list);
3398 rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
3399 userptr->sgt->nents, dir);
3401 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3405 userptr->dma_mapped = true;
3409 parser->patched_cb_size +=
3410 goya_get_dma_desc_list_size(hdev, userptr->sgt);
3415 list_del(&userptr->job_node);
3416 hl_unpin_host_memory(hdev, userptr);
3422 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3423 struct hl_cs_parser *parser,
3424 struct packet_lin_dma *user_dma_pkt)
3426 u64 device_memory_addr, addr;
3427 enum dma_data_direction dir;
3428 enum goya_dma_direction user_dir;
3429 bool sram_addr = true;
3430 bool skip_host_mem_pin = false;
3435 ctl = le32_to_cpu(user_dma_pkt->ctl);
3437 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3438 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3440 user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3441 GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3444 case DMA_HOST_TO_DRAM:
3445 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3446 dir = DMA_TO_DEVICE;
3448 addr = le64_to_cpu(user_dma_pkt->src_addr);
3449 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3451 skip_host_mem_pin = true;
3454 case DMA_DRAM_TO_HOST:
3455 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3456 dir = DMA_FROM_DEVICE;
3458 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3459 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3462 case DMA_HOST_TO_SRAM:
3463 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3464 dir = DMA_TO_DEVICE;
3465 addr = le64_to_cpu(user_dma_pkt->src_addr);
3466 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3468 skip_host_mem_pin = true;
3471 case DMA_SRAM_TO_HOST:
3472 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3473 dir = DMA_FROM_DEVICE;
3474 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3475 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3478 dev_err(hdev->dev, "DMA direction is undefined\n");
3483 if (!hl_mem_area_inside_range(device_memory_addr,
3484 le32_to_cpu(user_dma_pkt->tsize),
3485 hdev->asic_prop.sram_user_base_address,
3486 hdev->asic_prop.sram_end_address)) {
3489 "SRAM address 0x%llx + 0x%x is invalid\n",
3491 user_dma_pkt->tsize);
3495 if (!hl_mem_area_inside_range(device_memory_addr,
3496 le32_to_cpu(user_dma_pkt->tsize),
3497 hdev->asic_prop.dram_user_base_address,
3498 hdev->asic_prop.dram_end_address)) {
3501 "DRAM address 0x%llx + 0x%x is invalid\n",
3503 user_dma_pkt->tsize);
3508 if (skip_host_mem_pin)
3509 parser->patched_cb_size += sizeof(*user_dma_pkt);
3511 if ((dir == DMA_TO_DEVICE) &&
3512 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3514 "Can't DMA from host on queue other then 1\n");
3518 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3525 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3526 struct hl_cs_parser *parser,
3527 struct packet_lin_dma *user_dma_pkt)
3529 u64 sram_memory_addr, dram_memory_addr;
3530 enum goya_dma_direction user_dir;
3533 ctl = le32_to_cpu(user_dma_pkt->ctl);
3534 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3535 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3537 if (user_dir == DMA_DRAM_TO_SRAM) {
3538 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3539 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3540 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3542 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3543 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3544 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3547 if (!hl_mem_area_inside_range(sram_memory_addr,
3548 le32_to_cpu(user_dma_pkt->tsize),
3549 hdev->asic_prop.sram_user_base_address,
3550 hdev->asic_prop.sram_end_address)) {
3551 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3552 sram_memory_addr, user_dma_pkt->tsize);
3556 if (!hl_mem_area_inside_range(dram_memory_addr,
3557 le32_to_cpu(user_dma_pkt->tsize),
3558 hdev->asic_prop.dram_user_base_address,
3559 hdev->asic_prop.dram_end_address)) {
3560 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3561 dram_memory_addr, user_dma_pkt->tsize);
3565 parser->patched_cb_size += sizeof(*user_dma_pkt);
3570 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3571 struct hl_cs_parser *parser,
3572 struct packet_lin_dma *user_dma_pkt)
3574 enum goya_dma_direction user_dir;
3578 dev_dbg(hdev->dev, "DMA packet details:\n");
3579 dev_dbg(hdev->dev, "source == 0x%llx\n",
3580 le64_to_cpu(user_dma_pkt->src_addr));
3581 dev_dbg(hdev->dev, "destination == 0x%llx\n",
3582 le64_to_cpu(user_dma_pkt->dst_addr));
3583 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3585 ctl = le32_to_cpu(user_dma_pkt->ctl);
3586 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3587 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3590 * Special handling for DMA with size 0. The H/W has a bug where
3591 * this can cause the QMAN DMA to get stuck, so block it here.
3593 if (user_dma_pkt->tsize == 0) {
3595 "Got DMA with size 0, might reset the device\n");
3599 if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM))
3600 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3602 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3607 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3608 struct hl_cs_parser *parser,
3609 struct packet_lin_dma *user_dma_pkt)
3611 dev_dbg(hdev->dev, "DMA packet details:\n");
3612 dev_dbg(hdev->dev, "source == 0x%llx\n",
3613 le64_to_cpu(user_dma_pkt->src_addr));
3614 dev_dbg(hdev->dev, "destination == 0x%llx\n",
3615 le64_to_cpu(user_dma_pkt->dst_addr));
3616 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3620 * We can't allow user to read from Host using QMANs other than 1.
3621 * PMMU and HPMMU addresses are equal, check only one of them.
3623 if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 &&
3624 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3625 le32_to_cpu(user_dma_pkt->tsize),
3626 hdev->asic_prop.pmmu.start_addr,
3627 hdev->asic_prop.pmmu.end_addr)) {
3629 "Can't DMA from host on queue other then 1\n");
3633 if (user_dma_pkt->tsize == 0) {
3635 "Got DMA with size 0, might reset the device\n");
3639 parser->patched_cb_size += sizeof(*user_dma_pkt);
3644 static int goya_validate_wreg32(struct hl_device *hdev,
3645 struct hl_cs_parser *parser,
3646 struct packet_wreg32 *wreg_pkt)
3648 struct goya_device *goya = hdev->asic_specific;
3649 u32 sob_start_addr, sob_end_addr;
3652 reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3653 GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3655 dev_dbg(hdev->dev, "WREG32 packet details:\n");
3656 dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3657 dev_dbg(hdev->dev, "value == 0x%x\n",
3658 le32_to_cpu(wreg_pkt->value));
3660 if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3661 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3667 * With MMU, DMA channels are not secured, so it doesn't matter where
3668 * the WR COMP will be written to because it will go out with
3669 * non-secured property
3671 if (goya->hw_cap_initialized & HW_CAP_MMU)
3674 sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3675 sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3677 if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3678 (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3680 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3688 static int goya_validate_cb(struct hl_device *hdev,
3689 struct hl_cs_parser *parser, bool is_mmu)
3691 u32 cb_parsed_length = 0;
3694 parser->patched_cb_size = 0;
3696 /* cb_user_size is more than 0 so loop will always be executed */
3697 while (cb_parsed_length < parser->user_cb_size) {
3698 enum packet_id pkt_id;
3700 struct goya_packet *user_pkt;
3702 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3704 pkt_id = (enum packet_id) (
3705 (le64_to_cpu(user_pkt->header) &
3706 PACKET_HEADER_PACKET_ID_MASK) >>
3707 PACKET_HEADER_PACKET_ID_SHIFT);
3709 if (!validate_packet_id(pkt_id)) {
3710 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3715 pkt_size = goya_packet_sizes[pkt_id];
3716 cb_parsed_length += pkt_size;
3717 if (cb_parsed_length > parser->user_cb_size) {
3719 "packet 0x%x is out of CB boundary\n", pkt_id);
3725 case PACKET_WREG_32:
3727 * Although it is validated after copy in patch_cb(),
3728 * need to validate here as well because patch_cb() is
3729 * not called in MMU path while this function is called
3731 rc = goya_validate_wreg32(hdev,
3732 parser, (struct packet_wreg32 *) user_pkt);
3733 parser->patched_cb_size += pkt_size;
3736 case PACKET_WREG_BULK:
3738 "User not allowed to use WREG_BULK\n");
3742 case PACKET_MSG_PROT:
3744 "User not allowed to use MSG_PROT\n");
3749 dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3754 dev_err(hdev->dev, "User not allowed to use STOP\n");
3758 case PACKET_LIN_DMA:
3760 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3761 (struct packet_lin_dma *) user_pkt);
3763 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3764 (struct packet_lin_dma *) user_pkt);
3767 case PACKET_MSG_LONG:
3768 case PACKET_MSG_SHORT:
3771 parser->patched_cb_size += pkt_size;
3775 dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3786 * The new CB should have space at the end for two MSG_PROT packets:
3787 * 1. A packet that will act as a completion packet
3788 * 2. A packet that will generate MSI-X interrupt
3790 parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3795 static int goya_patch_dma_packet(struct hl_device *hdev,
3796 struct hl_cs_parser *parser,
3797 struct packet_lin_dma *user_dma_pkt,
3798 struct packet_lin_dma *new_dma_pkt,
3799 u32 *new_dma_pkt_size)
3801 struct hl_userptr *userptr;
3802 struct scatterlist *sg, *sg_next_iter;
3803 u32 count, dma_desc_cnt;
3805 dma_addr_t dma_addr, dma_addr_next;
3806 enum goya_dma_direction user_dir;
3807 u64 device_memory_addr, addr;
3808 enum dma_data_direction dir;
3809 struct sg_table *sgt;
3810 bool skip_host_mem_pin = false;
3812 u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3814 ctl = le32_to_cpu(user_dma_pkt->ctl);
3816 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3817 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3819 user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3820 GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3822 if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) ||
3823 (user_dma_pkt->tsize == 0)) {
3824 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3825 *new_dma_pkt_size = sizeof(*new_dma_pkt);
3829 if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) {
3830 addr = le64_to_cpu(user_dma_pkt->src_addr);
3831 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3832 dir = DMA_TO_DEVICE;
3834 skip_host_mem_pin = true;
3836 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3837 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3838 dir = DMA_FROM_DEVICE;
3841 if ((!skip_host_mem_pin) &&
3842 (hl_userptr_is_pinned(hdev, addr,
3843 le32_to_cpu(user_dma_pkt->tsize),
3844 parser->job_userptr_list, &userptr) == false)) {
3845 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3846 addr, user_dma_pkt->tsize);
3850 if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3851 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3852 *new_dma_pkt_size = sizeof(*user_dma_pkt);
3856 user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3858 user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3863 for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3864 len = sg_dma_len(sg);
3865 dma_addr = sg_dma_address(sg);
3870 while ((count + 1) < sgt->nents) {
3871 sg_next_iter = sg_next(sg);
3872 len_next = sg_dma_len(sg_next_iter);
3873 dma_addr_next = sg_dma_address(sg_next_iter);
3878 if ((dma_addr + len == dma_addr_next) &&
3879 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3888 ctl = le32_to_cpu(user_dma_pkt->ctl);
3889 if (likely(dma_desc_cnt))
3890 ctl &= ~GOYA_PKT_CTL_EB_MASK;
3891 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3892 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3893 new_dma_pkt->ctl = cpu_to_le32(ctl);
3894 new_dma_pkt->tsize = cpu_to_le32((u32) len);
3896 if (dir == DMA_TO_DEVICE) {
3897 new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3898 new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3900 new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3901 new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3905 device_memory_addr += len;
3910 if (!dma_desc_cnt) {
3912 "Error of 0 SG entries when patching DMA packet\n");
3916 /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3918 new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3920 *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3925 static int goya_patch_cb(struct hl_device *hdev,
3926 struct hl_cs_parser *parser)
3928 u32 cb_parsed_length = 0;
3929 u32 cb_patched_cur_length = 0;
3932 /* cb_user_size is more than 0 so loop will always be executed */
3933 while (cb_parsed_length < parser->user_cb_size) {
3934 enum packet_id pkt_id;
3936 u32 new_pkt_size = 0;
3937 struct goya_packet *user_pkt, *kernel_pkt;
3939 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3940 kernel_pkt = parser->patched_cb->kernel_address +
3941 cb_patched_cur_length;
3943 pkt_id = (enum packet_id) (
3944 (le64_to_cpu(user_pkt->header) &
3945 PACKET_HEADER_PACKET_ID_MASK) >>
3946 PACKET_HEADER_PACKET_ID_SHIFT);
3948 if (!validate_packet_id(pkt_id)) {
3949 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3954 pkt_size = goya_packet_sizes[pkt_id];
3955 cb_parsed_length += pkt_size;
3956 if (cb_parsed_length > parser->user_cb_size) {
3958 "packet 0x%x is out of CB boundary\n", pkt_id);
3964 case PACKET_LIN_DMA:
3965 rc = goya_patch_dma_packet(hdev, parser,
3966 (struct packet_lin_dma *) user_pkt,
3967 (struct packet_lin_dma *) kernel_pkt,
3969 cb_patched_cur_length += new_pkt_size;
3972 case PACKET_WREG_32:
3973 memcpy(kernel_pkt, user_pkt, pkt_size);
3974 cb_patched_cur_length += pkt_size;
3975 rc = goya_validate_wreg32(hdev, parser,
3976 (struct packet_wreg32 *) kernel_pkt);
3979 case PACKET_WREG_BULK:
3981 "User not allowed to use WREG_BULK\n");
3985 case PACKET_MSG_PROT:
3987 "User not allowed to use MSG_PROT\n");
3992 dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3997 dev_err(hdev->dev, "User not allowed to use STOP\n");
4001 case PACKET_MSG_LONG:
4002 case PACKET_MSG_SHORT:
4005 memcpy(kernel_pkt, user_pkt, pkt_size);
4006 cb_patched_cur_length += pkt_size;
4010 dev_err(hdev->dev, "Invalid packet header 0x%x\n",
4023 static int goya_parse_cb_mmu(struct hl_device *hdev,
4024 struct hl_cs_parser *parser)
4026 u64 patched_cb_handle;
4027 u32 patched_cb_size;
4028 struct hl_cb *user_cb;
4032 * The new CB should have space at the end for two MSG_PROT pkt:
4033 * 1. A packet that will act as a completion packet
4034 * 2. A packet that will generate MSI-X interrupt
4036 parser->patched_cb_size = parser->user_cb_size +
4037 sizeof(struct packet_msg_prot) * 2;
4039 rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
4040 parser->patched_cb_size, false, false,
4041 &patched_cb_handle);
4045 "Failed to allocate patched CB for DMA CS %d\n",
4050 patched_cb_handle >>= PAGE_SHIFT;
4051 parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
4052 (u32) patched_cb_handle);
4053 /* hl_cb_get should never fail here */
4054 if (!parser->patched_cb) {
4055 dev_crit(hdev->dev, "DMA CB handle invalid 0x%x\n",
4056 (u32) patched_cb_handle);
4062 * The check that parser->user_cb_size <= parser->user_cb->size was done
4063 * in validate_queue_index().
4065 memcpy(parser->patched_cb->kernel_address,
4066 parser->user_cb->kernel_address,
4067 parser->user_cb_size);
4069 patched_cb_size = parser->patched_cb_size;
4071 /* validate patched CB instead of user CB */
4072 user_cb = parser->user_cb;
4073 parser->user_cb = parser->patched_cb;
4074 rc = goya_validate_cb(hdev, parser, true);
4075 parser->user_cb = user_cb;
4078 hl_cb_put(parser->patched_cb);
4082 if (patched_cb_size != parser->patched_cb_size) {
4083 dev_err(hdev->dev, "user CB size mismatch\n");
4084 hl_cb_put(parser->patched_cb);
4091 * Always call cb destroy here because we still have 1 reference
4092 * to it by calling cb_get earlier. After the job will be completed,
4093 * cb_put will release it, but here we want to remove it from the
4096 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4097 patched_cb_handle << PAGE_SHIFT);
4102 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
4103 struct hl_cs_parser *parser)
4105 u64 patched_cb_handle;
4108 rc = goya_validate_cb(hdev, parser, false);
4113 rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
4114 parser->patched_cb_size, false, false,
4115 &patched_cb_handle);
4118 "Failed to allocate patched CB for DMA CS %d\n", rc);
4122 patched_cb_handle >>= PAGE_SHIFT;
4123 parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
4124 (u32) patched_cb_handle);
4125 /* hl_cb_get should never fail here */
4126 if (!parser->patched_cb) {
4127 dev_crit(hdev->dev, "DMA CB handle invalid 0x%x\n",
4128 (u32) patched_cb_handle);
4133 rc = goya_patch_cb(hdev, parser);
4136 hl_cb_put(parser->patched_cb);
4140 * Always call cb destroy here because we still have 1 reference
4141 * to it by calling cb_get earlier. After the job will be completed,
4142 * cb_put will release it, but here we want to remove it from the
4145 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4146 patched_cb_handle << PAGE_SHIFT);
4150 hl_userptr_delete_list(hdev, parser->job_userptr_list);
4154 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev,
4155 struct hl_cs_parser *parser)
4157 struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
4158 struct goya_device *goya = hdev->asic_specific;
4160 if (goya->hw_cap_initialized & HW_CAP_MMU)
4163 /* For internal queue jobs, just check if CB address is valid */
4164 if (hl_mem_area_inside_range(
4165 (u64) (uintptr_t) parser->user_cb,
4166 parser->user_cb_size,
4167 asic_prop->sram_user_base_address,
4168 asic_prop->sram_end_address))
4171 if (hl_mem_area_inside_range(
4172 (u64) (uintptr_t) parser->user_cb,
4173 parser->user_cb_size,
4174 asic_prop->dram_user_base_address,
4175 asic_prop->dram_end_address))
4179 "Internal CB address 0x%px + 0x%x is not in SRAM nor in DRAM\n",
4180 parser->user_cb, parser->user_cb_size);
4185 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
4187 struct goya_device *goya = hdev->asic_specific;
4189 if (parser->queue_type == QUEUE_TYPE_INT)
4190 return goya_parse_cb_no_ext_queue(hdev, parser);
4192 if (goya->hw_cap_initialized & HW_CAP_MMU)
4193 return goya_parse_cb_mmu(hdev, parser);
4195 return goya_parse_cb_no_mmu(hdev, parser);
4198 void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
4199 u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec,
4202 struct packet_msg_prot *cq_pkt;
4205 cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
4207 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4208 (1 << GOYA_PKT_CTL_EB_SHIFT) |
4209 (1 << GOYA_PKT_CTL_MB_SHIFT);
4210 cq_pkt->ctl = cpu_to_le32(tmp);
4211 cq_pkt->value = cpu_to_le32(cq_val);
4212 cq_pkt->addr = cpu_to_le64(cq_addr);
4216 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4217 (1 << GOYA_PKT_CTL_MB_SHIFT);
4218 cq_pkt->ctl = cpu_to_le32(tmp);
4219 cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
4220 cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
4223 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4225 WREG32(mmCPU_EQ_CI, val);
4228 void goya_restore_phase_topology(struct hl_device *hdev)
4233 static void goya_clear_sm_regs(struct hl_device *hdev)
4235 int i, num_of_sob_in_longs, num_of_mon_in_longs;
4237 num_of_sob_in_longs =
4238 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
4240 num_of_mon_in_longs =
4241 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
4243 for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
4244 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4246 for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
4247 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4249 /* Flush all WREG to prevent race */
4250 i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
4254 * goya_debugfs_read32 - read a 32bit value from a given device or a host mapped
4257 * @hdev: pointer to hl_device structure
4258 * @addr: device or host mapped address
4259 * @val: returned value
4261 * In case of DDR address that is not mapped into the default aperture that
4262 * the DDR bar exposes, the function will configure the iATU so that the DDR
4263 * bar will be positioned at a base address that allows reading from the
4264 * required address. Configuring the iATU during normal operation can
4265 * lead to undefined behavior and therefore, should be done with extreme care
4268 static int goya_debugfs_read32(struct hl_device *hdev, u64 addr,
4269 bool user_address, u32 *val)
4271 struct asic_fixed_properties *prop = &hdev->asic_prop;
4272 u64 ddr_bar_addr, host_phys_end;
4275 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4277 if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4278 *val = RREG32(addr - CFG_BASE);
4280 } else if ((addr >= SRAM_BASE_ADDR) &&
4281 (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4283 *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4284 (addr - SRAM_BASE_ADDR));
4286 } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
4288 u64 bar_base_addr = DRAM_PHYS_BASE +
4289 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4291 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4292 if (ddr_bar_addr != U64_MAX) {
4293 *val = readl(hdev->pcie_bar[DDR_BAR_ID] +
4294 (addr - bar_base_addr));
4296 ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4299 if (ddr_bar_addr == U64_MAX)
4302 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4303 user_address && !iommu_present(&pci_bus_type)) {
4304 *val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
4314 * goya_debugfs_write32 - write a 32bit value to a given device or a host mapped
4317 * @hdev: pointer to hl_device structure
4318 * @addr: device or host mapped address
4319 * @val: returned value
4321 * In case of DDR address that is not mapped into the default aperture that
4322 * the DDR bar exposes, the function will configure the iATU so that the DDR
4323 * bar will be positioned at a base address that allows writing to the
4324 * required address. Configuring the iATU during normal operation can
4325 * lead to undefined behavior and therefore, should be done with extreme care
4328 static int goya_debugfs_write32(struct hl_device *hdev, u64 addr,
4329 bool user_address, u32 val)
4331 struct asic_fixed_properties *prop = &hdev->asic_prop;
4332 u64 ddr_bar_addr, host_phys_end;
4335 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4337 if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4338 WREG32(addr - CFG_BASE, val);
4340 } else if ((addr >= SRAM_BASE_ADDR) &&
4341 (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4343 writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4344 (addr - SRAM_BASE_ADDR));
4346 } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
4348 u64 bar_base_addr = DRAM_PHYS_BASE +
4349 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4351 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4352 if (ddr_bar_addr != U64_MAX) {
4353 writel(val, hdev->pcie_bar[DDR_BAR_ID] +
4354 (addr - bar_base_addr));
4356 ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4359 if (ddr_bar_addr == U64_MAX)
4362 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4363 user_address && !iommu_present(&pci_bus_type)) {
4364 *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4373 static int goya_debugfs_read64(struct hl_device *hdev, u64 addr,
4374 bool user_address, u64 *val)
4376 struct asic_fixed_properties *prop = &hdev->asic_prop;
4377 u64 ddr_bar_addr, host_phys_end;
4380 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4382 if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
4383 u32 val_l = RREG32(addr - CFG_BASE);
4384 u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);
4386 *val = (((u64) val_h) << 32) | val_l;
4388 } else if ((addr >= SRAM_BASE_ADDR) &&
4389 (addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
4391 *val = readq(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4392 (addr - SRAM_BASE_ADDR));
4395 DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
4397 u64 bar_base_addr = DRAM_PHYS_BASE +
4398 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4400 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4401 if (ddr_bar_addr != U64_MAX) {
4402 *val = readq(hdev->pcie_bar[DDR_BAR_ID] +
4403 (addr - bar_base_addr));
4405 ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4408 if (ddr_bar_addr == U64_MAX)
4411 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4412 user_address && !iommu_present(&pci_bus_type)) {
4413 *val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);
4422 static int goya_debugfs_write64(struct hl_device *hdev, u64 addr,
4423 bool user_address, u64 val)
4425 struct asic_fixed_properties *prop = &hdev->asic_prop;
4426 u64 ddr_bar_addr, host_phys_end;
4429 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4431 if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
4432 WREG32(addr - CFG_BASE, lower_32_bits(val));
4433 WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));
4435 } else if ((addr >= SRAM_BASE_ADDR) &&
4436 (addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
4438 writeq(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4439 (addr - SRAM_BASE_ADDR));
4442 DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
4444 u64 bar_base_addr = DRAM_PHYS_BASE +
4445 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4447 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4448 if (ddr_bar_addr != U64_MAX) {
4449 writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4450 (addr - bar_base_addr));
4452 ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4455 if (ddr_bar_addr == U64_MAX)
4458 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4459 user_address && !iommu_present(&pci_bus_type)) {
4460 *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4469 static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,
4472 dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n");
4476 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4478 struct goya_device *goya = hdev->asic_specific;
4480 if (hdev->reset_info.hard_reset_pending)
4483 return readq(hdev->pcie_bar[DDR_BAR_ID] +
4484 (addr - goya->ddr_bar_cur_addr));
4487 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4489 struct goya_device *goya = hdev->asic_specific;
4491 if (hdev->reset_info.hard_reset_pending)
4494 writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4495 (addr - goya->ddr_bar_cur_addr));
4498 static const char *_goya_get_event_desc(u16 event_type)
4500 switch (event_type) {
4501 case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4503 case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4504 case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4505 case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4506 case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4507 case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4508 case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4509 case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4510 case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4512 case GOYA_ASYNC_EVENT_ID_MME_ECC:
4514 case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4515 return "MME_ecc_ext";
4516 case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4518 case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4520 case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4522 case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4523 return "CPU_if_ecc";
4524 case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4526 case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4527 return "PSOC_coresight";
4528 case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4530 case GOYA_ASYNC_EVENT_ID_GIC500:
4532 case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4534 case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4536 case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4537 return "L2_ram_ecc";
4538 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4539 return "PSOC_gpio_05_sw_reset";
4540 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4541 return "PSOC_gpio_10_vrhot_icrit";
4542 case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4544 case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4545 case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4546 case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4547 case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4548 case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4549 case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4550 case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4551 case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4553 case GOYA_ASYNC_EVENT_ID_MME_WACS:
4555 case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4557 case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4558 return "CPU_axi_splitter";
4559 case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4560 return "PSOC_axi_dec";
4561 case GOYA_ASYNC_EVENT_ID_PSOC:
4563 case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4564 case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4565 case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4566 case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4567 case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4568 case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4569 case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4570 case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4571 return "TPC%d_krn_err";
4572 case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4574 case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4576 case GOYA_ASYNC_EVENT_ID_MME_QM:
4578 case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4580 case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4582 case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4584 case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4585 case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4586 case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4587 case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4588 case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4589 case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4590 case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4591 case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4592 return "TPC%d_bmon_spmu";
4593 case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4594 return "DMA_bm_ch%d";
4595 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4596 return "POWER_ENV_S";
4597 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4598 return "POWER_ENV_E";
4599 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4600 return "THERMAL_ENV_S";
4601 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4602 return "THERMAL_ENV_E";
4603 case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4604 return "QUEUE_OUT_OF_SYNC";
4610 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4614 switch (event_type) {
4615 case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4616 case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4617 case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4618 case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4619 case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4620 case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4621 case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4622 case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4623 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3;
4624 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4626 case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4627 index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0;
4628 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4630 case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4631 index = event_type - GOYA_ASYNC_EVENT_ID_PLL0;
4632 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4634 case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4635 case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4636 case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4637 case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4638 case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4639 case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4640 case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4641 case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4642 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4643 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4645 case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4646 case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4647 case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4648 case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4649 case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4650 case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4651 case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4652 case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4653 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4654 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4656 case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4657 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4658 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4660 case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4661 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4662 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4664 case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4665 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4666 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4668 case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4669 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4670 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4672 case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4673 case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4674 case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4675 case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4676 case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4677 case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4678 case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4679 case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4680 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10;
4681 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4683 case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4684 index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0;
4685 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4687 case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4688 snprintf(desc, size, _goya_get_event_desc(event_type));
4691 snprintf(desc, size, _goya_get_event_desc(event_type));
4696 static void goya_print_razwi_info(struct hl_device *hdev)
4698 if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4699 dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n");
4700 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4703 if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4704 dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n");
4705 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4708 if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4709 dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n");
4710 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4713 if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4714 dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n");
4715 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4719 static void goya_print_mmu_error_info(struct hl_device *hdev)
4721 struct goya_device *goya = hdev->asic_specific;
4725 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4728 val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4729 if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4730 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4732 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4734 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n",
4737 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4741 static void goya_print_out_of_sync_info(struct hl_device *hdev,
4742 struct cpucp_pkt_sync_err *sync_err)
4744 struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
4746 dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%u\n",
4747 sync_err->pi, sync_err->ci, q->pi, atomic_read(&q->ci));
4750 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
4755 goya_get_event_desc(event_type, desc, sizeof(desc));
4756 dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4760 goya_print_razwi_info(hdev);
4761 goya_print_mmu_error_info(hdev);
4765 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4766 size_t irq_arr_size)
4768 struct cpucp_unmask_irq_arr_packet *pkt;
4769 size_t total_pkt_size;
4772 int irq_num_entries, irq_arr_index;
4773 __le32 *goya_irq_arr;
4775 total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) +
4778 /* data should be aligned to 8 bytes in order to CPU-CP to copy it */
4779 total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4781 /* total_pkt_size is casted to u16 later on */
4782 if (total_pkt_size > USHRT_MAX) {
4783 dev_err(hdev->dev, "too many elements in IRQ array\n");
4787 pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4791 irq_num_entries = irq_arr_size / sizeof(irq_arr[0]);
4792 pkt->length = cpu_to_le32(irq_num_entries);
4794 /* We must perform any necessary endianness conversation on the irq
4795 * array being passed to the goya hardware
4797 for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs;
4798 irq_arr_index < irq_num_entries ; irq_arr_index++)
4799 goya_irq_arr[irq_arr_index] =
4800 cpu_to_le32(irq_arr[irq_arr_index]);
4802 pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4803 CPUCP_PKT_CTL_OPCODE_SHIFT);
4805 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
4806 total_pkt_size, 0, &result);
4809 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4816 static int goya_non_hard_reset_late_init(struct hl_device *hdev)
4819 * Unmask all IRQs since some could have been received
4820 * during the soft reset
4822 return goya_unmask_irq_arr(hdev, goya_all_events,
4823 sizeof(goya_all_events));
4826 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4828 struct cpucp_packet pkt;
4832 memset(&pkt, 0, sizeof(pkt));
4834 pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ <<
4835 CPUCP_PKT_CTL_OPCODE_SHIFT);
4836 pkt.value = cpu_to_le64(event_type);
4838 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4842 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4847 static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type)
4849 ktime_t zero_time = ktime_set(0, 0);
4851 mutex_lock(&hdev->clk_throttling.lock);
4853 switch (event_type) {
4854 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4855 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER;
4856 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER;
4857 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get();
4858 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time;
4859 dev_info_ratelimited(hdev->dev,
4860 "Clock throttling due to power consumption\n");
4863 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4864 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER;
4865 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get();
4866 dev_info_ratelimited(hdev->dev,
4867 "Power envelop is safe, back to optimal clock\n");
4870 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4871 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL;
4872 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL;
4873 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get();
4874 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time;
4875 dev_info_ratelimited(hdev->dev,
4876 "Clock throttling due to overheating\n");
4879 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4880 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL;
4881 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get();
4882 dev_info_ratelimited(hdev->dev,
4883 "Thermal envelop is safe, back to optimal clock\n");
4887 dev_err(hdev->dev, "Received invalid clock change event %d\n",
4892 mutex_unlock(&hdev->clk_throttling.lock);
4895 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4897 u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4898 u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4899 >> EQ_CTL_EVENT_TYPE_SHIFT);
4900 struct goya_device *goya = hdev->asic_specific;
4902 if (event_type >= GOYA_ASYNC_EVENT_ID_SIZE) {
4903 dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
4904 event_type, GOYA_ASYNC_EVENT_ID_SIZE - 1);
4908 goya->events_stat[event_type]++;
4909 goya->events_stat_aggregate[event_type]++;
4911 switch (event_type) {
4912 case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4913 case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4914 case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4915 case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4916 case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4917 case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4918 case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4919 case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4920 case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4921 case GOYA_ASYNC_EVENT_ID_MME_ECC:
4922 case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4923 case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4924 case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4925 case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4926 case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4927 case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4928 case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4929 case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4930 case GOYA_ASYNC_EVENT_ID_GIC500:
4931 case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4932 case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4933 case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4934 goya_print_irq_info(hdev, event_type, false);
4935 if (hdev->hard_reset_on_fw_events)
4936 hl_device_reset(hdev, (HL_DRV_RESET_HARD |
4937 HL_DRV_RESET_FW_FATAL_ERR));
4940 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4941 goya_print_irq_info(hdev, event_type, false);
4942 if (hdev->hard_reset_on_fw_events)
4943 hl_device_reset(hdev, HL_DRV_RESET_HARD);
4946 case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4947 case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4948 case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4949 case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4950 case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4951 case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4952 case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4953 case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4954 case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4955 case GOYA_ASYNC_EVENT_ID_MME_WACS:
4956 case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4957 case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4958 case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4959 case GOYA_ASYNC_EVENT_ID_PSOC:
4960 case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4961 case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4962 case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4963 case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4964 case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4965 case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4966 case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4967 case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4968 case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4969 case GOYA_ASYNC_EVENT_ID_MME_QM:
4970 case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4971 case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4972 case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4973 goya_print_irq_info(hdev, event_type, true);
4974 goya_unmask_irq(hdev, event_type);
4977 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4978 case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4979 case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4980 case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4981 case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4982 case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4983 case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4984 case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4985 case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4986 case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4987 goya_print_irq_info(hdev, event_type, false);
4988 goya_unmask_irq(hdev, event_type);
4991 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4992 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4993 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4994 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4995 goya_print_clk_change_info(hdev, event_type);
4996 goya_unmask_irq(hdev, event_type);
4999 case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
5000 goya_print_irq_info(hdev, event_type, false);
5001 goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err);
5002 if (hdev->hard_reset_on_fw_events)
5003 hl_device_reset(hdev, HL_DRV_RESET_HARD);
5005 hl_fw_unmask_irq(hdev, event_type);
5009 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
5015 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size)
5017 struct goya_device *goya = hdev->asic_specific;
5020 *size = (u32) sizeof(goya->events_stat_aggregate);
5021 return goya->events_stat_aggregate;
5024 *size = (u32) sizeof(goya->events_stat);
5025 return goya->events_stat;
5028 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
5029 u64 val, bool is_dram)
5031 struct packet_lin_dma *lin_dma_pkt;
5032 struct hl_cs_job *job;
5035 int rc, lin_dma_pkts_cnt;
5037 lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G);
5038 cb_size = lin_dma_pkts_cnt * sizeof(struct packet_lin_dma) +
5039 sizeof(struct packet_msg_prot);
5040 cb = hl_cb_kernel_create(hdev, cb_size, false);
5044 lin_dma_pkt = cb->kernel_address;
5047 memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
5049 ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
5050 (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
5051 (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
5052 (1 << GOYA_PKT_CTL_RB_SHIFT) |
5053 (1 << GOYA_PKT_CTL_MB_SHIFT));
5054 ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) <<
5055 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
5056 lin_dma_pkt->ctl = cpu_to_le32(ctl);
5058 lin_dma_pkt->src_addr = cpu_to_le64(val);
5059 lin_dma_pkt->dst_addr = cpu_to_le64(addr);
5060 if (lin_dma_pkts_cnt > 1)
5061 lin_dma_pkt->tsize = cpu_to_le32(SZ_2G);
5063 lin_dma_pkt->tsize = cpu_to_le32(size);
5068 } while (--lin_dma_pkts_cnt);
5070 job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
5072 dev_err(hdev->dev, "Failed to allocate a new job\n");
5079 atomic_inc(&job->user_cb->cs_cnt);
5080 job->user_cb_size = cb_size;
5081 job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
5082 job->patched_cb = job->user_cb;
5083 job->job_cb_size = job->user_cb_size;
5085 hl_debugfs_add_job(hdev, job);
5087 rc = goya_send_job_on_qman0(hdev, job);
5089 hl_debugfs_remove_job(hdev, job);
5091 atomic_dec(&cb->cs_cnt);
5095 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
5100 int goya_context_switch(struct hl_device *hdev, u32 asid)
5102 struct asic_fixed_properties *prop = &hdev->asic_prop;
5103 u64 addr = prop->sram_base_address, sob_addr;
5104 u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
5105 u64 val = 0x7777777777777777ull;
5107 u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO -
5108 mmDMA_CH_0_WR_COMP_ADDR_LO;
5110 rc = goya_memset_device_memory(hdev, addr, size, val, false);
5112 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
5116 /* we need to reset registers that the user is allowed to change */
5117 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
5118 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
5120 for (dma_id = 1 ; dma_id < NUMBER_OF_EXT_HW_QUEUES ; dma_id++) {
5121 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
5123 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
5124 lower_32_bits(sob_addr));
5127 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
5129 goya_clear_sm_regs(hdev);
5134 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
5136 struct asic_fixed_properties *prop = &hdev->asic_prop;
5137 struct goya_device *goya = hdev->asic_specific;
5138 u64 addr = prop->mmu_pgt_addr;
5139 u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
5142 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5145 return goya_memset_device_memory(hdev, addr, size, 0, true);
5148 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
5150 struct goya_device *goya = hdev->asic_specific;
5151 u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
5152 u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
5153 u64 val = 0x9999999999999999ull;
5155 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5158 return goya_memset_device_memory(hdev, addr, size, val, true);
5161 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
5163 struct asic_fixed_properties *prop = &hdev->asic_prop;
5164 struct goya_device *goya = hdev->asic_specific;
5168 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5171 for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) {
5172 rc = hl_mmu_map_page(hdev->kernel_ctx,
5173 prop->dram_base_address + off,
5174 prop->dram_base_address + off, PAGE_SIZE_2MB,
5175 (off + PAGE_SIZE_2MB) == CPU_FW_IMAGE_SIZE);
5177 dev_err(hdev->dev, "Map failed for address 0x%llx\n",
5178 prop->dram_base_address + off);
5183 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
5184 rc = hl_mmu_map_page(hdev->kernel_ctx,
5185 VA_CPU_ACCESSIBLE_MEM_ADDR,
5186 hdev->cpu_accessible_dma_address,
5187 PAGE_SIZE_2MB, true);
5191 "Map failed for CPU accessible memory\n");
5192 off -= PAGE_SIZE_2MB;
5196 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) {
5197 rc = hl_mmu_map_page(hdev->kernel_ctx,
5198 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5199 hdev->cpu_accessible_dma_address + cpu_off,
5200 PAGE_SIZE_4KB, true);
5203 "Map failed for CPU accessible memory\n");
5204 cpu_off -= PAGE_SIZE_4KB;
5210 goya_mmu_prepare_reg(hdev, mmCPU_IF_ARUSER_OVR, HL_KERNEL_ASID_ID);
5211 goya_mmu_prepare_reg(hdev, mmCPU_IF_AWUSER_OVR, HL_KERNEL_ASID_ID);
5212 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
5213 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
5215 /* Make sure configuration is flushed to device */
5216 RREG32(mmCPU_IF_AWUSER_OVR_EN);
5218 goya->device_cpu_mmu_mappings_done = true;
5223 for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB)
5224 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5225 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5226 PAGE_SIZE_4KB, true))
5227 dev_warn_ratelimited(hdev->dev,
5228 "failed to unmap address 0x%llx\n",
5229 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5231 for (; off >= 0 ; off -= PAGE_SIZE_2MB)
5232 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5233 prop->dram_base_address + off, PAGE_SIZE_2MB,
5235 dev_warn_ratelimited(hdev->dev,
5236 "failed to unmap address 0x%llx\n",
5237 prop->dram_base_address + off);
5242 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
5244 struct asic_fixed_properties *prop = &hdev->asic_prop;
5245 struct goya_device *goya = hdev->asic_specific;
5248 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5251 if (!goya->device_cpu_mmu_mappings_done)
5254 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
5255 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
5257 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
5258 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5259 VA_CPU_ACCESSIBLE_MEM_ADDR,
5260 PAGE_SIZE_2MB, true))
5262 "Failed to unmap CPU accessible memory\n");
5264 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB)
5265 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5266 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5268 (cpu_off + PAGE_SIZE_4KB) >= SZ_2M))
5269 dev_warn_ratelimited(hdev->dev,
5270 "failed to unmap address 0x%llx\n",
5271 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5274 for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB)
5275 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5276 prop->dram_base_address + off, PAGE_SIZE_2MB,
5277 (off + PAGE_SIZE_2MB) >= CPU_FW_IMAGE_SIZE))
5278 dev_warn_ratelimited(hdev->dev,
5279 "Failed to unmap address 0x%llx\n",
5280 prop->dram_base_address + off);
5282 goya->device_cpu_mmu_mappings_done = false;
5285 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
5287 struct goya_device *goya = hdev->asic_specific;
5290 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5293 if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
5294 dev_crit(hdev->dev, "asid %u is too big\n", asid);
5298 /* zero the MMBP and ASID bits and then set the ASID */
5299 for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++)
5300 goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
5303 static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
5306 struct goya_device *goya = hdev->asic_specific;
5307 u32 status, timeout_usec;
5310 if (!(goya->hw_cap_initialized & HW_CAP_MMU) ||
5311 hdev->reset_info.hard_reset_pending)
5314 /* no need in L1 only invalidation in Goya */
5319 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
5321 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
5323 /* L0 & L1 invalidation */
5324 WREG32(mmSTLB_INV_ALL_START, 1);
5326 rc = hl_poll_timeout(
5328 mmSTLB_INV_ALL_START,
5337 static int goya_mmu_invalidate_cache_range(struct hl_device *hdev,
5338 bool is_hard, u32 flags,
5339 u32 asid, u64 va, u64 size)
5341 /* Treat as invalidate all because there is no range invalidation
5344 return hdev->asic_funcs->mmu_invalidate_cache(hdev, is_hard, flags);
5347 int goya_send_heartbeat(struct hl_device *hdev)
5349 struct goya_device *goya = hdev->asic_specific;
5351 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5354 return hl_fw_send_heartbeat(hdev);
5357 int goya_cpucp_info_get(struct hl_device *hdev)
5359 struct goya_device *goya = hdev->asic_specific;
5360 struct asic_fixed_properties *prop = &hdev->asic_prop;
5364 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5367 rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0,
5368 mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
5373 dram_size = le64_to_cpu(prop->cpucp_info.dram_size);
5375 if ((!is_power_of_2(dram_size)) ||
5376 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
5378 "F/W reported invalid DRAM size %llu. Trying to use default size\n",
5380 dram_size = DRAM_PHYS_DEFAULT_SIZE;
5383 prop->dram_size = dram_size;
5384 prop->dram_end_address = prop->dram_base_address + dram_size;
5387 if (!strlen(prop->cpucp_info.card_name))
5388 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
5394 static void goya_set_clock_gating(struct hl_device *hdev)
5396 /* clock gating not supported in Goya */
5399 static void goya_disable_clock_gating(struct hl_device *hdev)
5401 /* clock gating not supported in Goya */
5404 static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask_arr,
5405 u8 mask_len, struct seq_file *s)
5407 const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n";
5408 const char *dma_fmt = "%-5d%-9s%#-14x%#x\n";
5409 unsigned long *mask = (unsigned long *)mask_arr;
5410 u32 qm_glbl_sts0, cmdq_glbl_sts0, dma_core_sts0, tpc_cfg_sts,
5412 bool is_idle = true, is_eng_idle;
5417 seq_puts(s, "\nDMA is_idle QM_GLBL_STS0 DMA_CORE_STS0\n"
5418 "--- ------- ------------ -------------\n");
5420 offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
5422 for (i = 0 ; i < DMA_MAX_NUM ; i++) {
5423 qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset);
5424 dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset);
5425 is_eng_idle = IS_DMA_QM_IDLE(qm_glbl_sts0) &&
5426 IS_DMA_IDLE(dma_core_sts0);
5427 is_idle &= is_eng_idle;
5429 if (mask && !is_eng_idle)
5430 set_bit(GOYA_ENGINE_ID_DMA_0 + i, mask);
5432 seq_printf(s, dma_fmt, i, is_eng_idle ? "Y" : "N",
5433 qm_glbl_sts0, dma_core_sts0);
5438 "\nTPC is_idle QM_GLBL_STS0 CMDQ_GLBL_STS0 CFG_STATUS\n"
5439 "--- ------- ------------ -------------- ----------\n");
5441 offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
5443 for (i = 0 ; i < TPC_MAX_NUM ; i++) {
5444 qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset);
5445 cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset);
5446 tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset);
5447 is_eng_idle = IS_TPC_QM_IDLE(qm_glbl_sts0) &&
5448 IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) &&
5449 IS_TPC_IDLE(tpc_cfg_sts);
5450 is_idle &= is_eng_idle;
5452 if (mask && !is_eng_idle)
5453 set_bit(GOYA_ENGINE_ID_TPC_0 + i, mask);
5455 seq_printf(s, fmt, i, is_eng_idle ? "Y" : "N",
5456 qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts);
5461 "\nMME is_idle QM_GLBL_STS0 CMDQ_GLBL_STS0 ARCH_STATUS\n"
5462 "--- ------- ------------ -------------- -----------\n");
5464 qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0);
5465 cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0);
5466 mme_arch_sts = RREG32(mmMME_ARCH_STATUS);
5467 is_eng_idle = IS_MME_QM_IDLE(qm_glbl_sts0) &&
5468 IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) &&
5469 IS_MME_IDLE(mme_arch_sts);
5470 is_idle &= is_eng_idle;
5472 if (mask && !is_eng_idle)
5473 set_bit(GOYA_ENGINE_ID_MME_0, mask);
5475 seq_printf(s, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0,
5476 cmdq_glbl_sts0, mme_arch_sts);
5483 static void goya_hw_queues_lock(struct hl_device *hdev)
5484 __acquires(&goya->hw_queues_lock)
5486 struct goya_device *goya = hdev->asic_specific;
5488 spin_lock(&goya->hw_queues_lock);
5491 static void goya_hw_queues_unlock(struct hl_device *hdev)
5492 __releases(&goya->hw_queues_lock)
5494 struct goya_device *goya = hdev->asic_specific;
5496 spin_unlock(&goya->hw_queues_lock);
5499 static u32 goya_get_pci_id(struct hl_device *hdev)
5501 return hdev->pdev->device;
5504 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5507 struct goya_device *goya = hdev->asic_specific;
5509 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5512 return hl_fw_get_eeprom_data(hdev, data, max_size);
5515 static void goya_cpu_init_scrambler_dram(struct hl_device *hdev)
5520 static int goya_ctx_init(struct hl_ctx *ctx)
5522 if (ctx->asid != HL_KERNEL_ASID_ID)
5523 goya_mmu_prepare(ctx->hdev, ctx->asid);
5528 u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
5533 static u32 goya_get_signal_cb_size(struct hl_device *hdev)
5538 static u32 goya_get_wait_cb_size(struct hl_device *hdev)
5543 static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
5549 static u32 goya_gen_wait_cb(struct hl_device *hdev,
5550 struct hl_gen_wait_properties *prop)
5555 static void goya_reset_sob(struct hl_device *hdev, void *data)
5560 static void goya_reset_sob_group(struct hl_device *hdev, u16 sob_group)
5565 static void goya_set_dma_mask_from_fw(struct hl_device *hdev)
5567 if (RREG32(mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0) ==
5568 HL_POWER9_HOST_MAGIC) {
5569 dev_dbg(hdev->dev, "Working in 64-bit DMA mode\n");
5570 hdev->power9_64bit_dma_enable = 1;
5571 hdev->dma_mask = 64;
5573 dev_dbg(hdev->dev, "Working in 48-bit DMA mode\n");
5574 hdev->power9_64bit_dma_enable = 0;
5575 hdev->dma_mask = 48;
5579 u64 goya_get_device_time(struct hl_device *hdev)
5581 u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
5583 return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
5586 static int goya_collective_wait_init_cs(struct hl_cs *cs)
5591 static int goya_collective_wait_create_jobs(struct hl_device *hdev,
5592 struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id,
5593 u32 collective_engine_id, u32 encaps_signal_offset)
5598 static void goya_ctx_fini(struct hl_ctx *ctx)
5603 static int goya_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
5604 u32 *block_size, u32 *block_id)
5609 static int goya_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
5610 u32 block_id, u32 block_size)
5615 static void goya_enable_events_from_fw(struct hl_device *hdev)
5617 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
5618 GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
5621 static int goya_map_pll_idx_to_fw_idx(u32 pll_idx)
5624 case HL_GOYA_CPU_PLL: return CPU_PLL;
5625 case HL_GOYA_PCI_PLL: return PCI_PLL;
5626 case HL_GOYA_MME_PLL: return MME_PLL;
5627 case HL_GOYA_TPC_PLL: return TPC_PLL;
5628 case HL_GOYA_IC_PLL: return IC_PLL;
5629 case HL_GOYA_MC_PLL: return MC_PLL;
5630 case HL_GOYA_EMMC_PLL: return EMMC_PLL;
5631 default: return -EINVAL;
5635 static int goya_gen_sync_to_engine_map(struct hl_device *hdev,
5636 struct hl_sync_to_engine_map *map)
5638 /* Not implemented */
5642 static int goya_monitor_valid(struct hl_mon_state_dump *mon)
5644 /* Not implemented */
5648 static int goya_print_single_monitor(char **buf, size_t *size, size_t *offset,
5649 struct hl_device *hdev,
5650 struct hl_mon_state_dump *mon)
5652 /* Not implemented */
5657 static int goya_print_fences_single_engine(
5658 struct hl_device *hdev, u64 base_offset, u64 status_base_offset,
5659 enum hl_sync_engine_type engine_type, u32 engine_id, char **buf,
5660 size_t *size, size_t *offset)
5662 /* Not implemented */
5667 static struct hl_state_dump_specs_funcs goya_state_dump_funcs = {
5668 .monitor_valid = goya_monitor_valid,
5669 .print_single_monitor = goya_print_single_monitor,
5670 .gen_sync_to_engine_map = goya_gen_sync_to_engine_map,
5671 .print_fences_single_engine = goya_print_fences_single_engine,
5674 static void goya_state_dump_init(struct hl_device *hdev)
5676 /* Not implemented */
5677 hdev->state_dump_specs.props = goya_state_dump_specs_props;
5678 hdev->state_dump_specs.funcs = goya_state_dump_funcs;
5681 static u32 goya_get_sob_addr(struct hl_device *hdev, u32 sob_id)
5686 static u32 *goya_get_stream_master_qid_arr(void)
5691 static const struct hl_asic_funcs goya_funcs = {
5692 .early_init = goya_early_init,
5693 .early_fini = goya_early_fini,
5694 .late_init = goya_late_init,
5695 .late_fini = goya_late_fini,
5696 .sw_init = goya_sw_init,
5697 .sw_fini = goya_sw_fini,
5698 .hw_init = goya_hw_init,
5699 .hw_fini = goya_hw_fini,
5700 .halt_engines = goya_halt_engines,
5701 .suspend = goya_suspend,
5702 .resume = goya_resume,
5704 .ring_doorbell = goya_ring_doorbell,
5705 .pqe_write = goya_pqe_write,
5706 .asic_dma_alloc_coherent = goya_dma_alloc_coherent,
5707 .asic_dma_free_coherent = goya_dma_free_coherent,
5708 .scrub_device_mem = goya_scrub_device_mem,
5709 .get_int_queue_base = goya_get_int_queue_base,
5710 .test_queues = goya_test_queues,
5711 .asic_dma_pool_zalloc = goya_dma_pool_zalloc,
5712 .asic_dma_pool_free = goya_dma_pool_free,
5713 .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
5714 .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
5715 .hl_dma_unmap_sg = goya_dma_unmap_sg,
5716 .cs_parser = goya_cs_parser,
5717 .asic_dma_map_sg = goya_dma_map_sg,
5718 .get_dma_desc_list_size = goya_get_dma_desc_list_size,
5719 .add_end_of_cb_packets = goya_add_end_of_cb_packets,
5720 .update_eq_ci = goya_update_eq_ci,
5721 .context_switch = goya_context_switch,
5722 .restore_phase_topology = goya_restore_phase_topology,
5723 .debugfs_read32 = goya_debugfs_read32,
5724 .debugfs_write32 = goya_debugfs_write32,
5725 .debugfs_read64 = goya_debugfs_read64,
5726 .debugfs_write64 = goya_debugfs_write64,
5727 .debugfs_read_dma = goya_debugfs_read_dma,
5728 .add_device_attr = goya_add_device_attr,
5729 .handle_eqe = goya_handle_eqe,
5730 .set_pll_profile = goya_set_pll_profile,
5731 .get_events_stat = goya_get_events_stat,
5732 .read_pte = goya_read_pte,
5733 .write_pte = goya_write_pte,
5734 .mmu_invalidate_cache = goya_mmu_invalidate_cache,
5735 .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
5736 .send_heartbeat = goya_send_heartbeat,
5737 .set_clock_gating = goya_set_clock_gating,
5738 .disable_clock_gating = goya_disable_clock_gating,
5739 .debug_coresight = goya_debug_coresight,
5740 .is_device_idle = goya_is_device_idle,
5741 .non_hard_reset_late_init = goya_non_hard_reset_late_init,
5742 .hw_queues_lock = goya_hw_queues_lock,
5743 .hw_queues_unlock = goya_hw_queues_unlock,
5744 .get_pci_id = goya_get_pci_id,
5745 .get_eeprom_data = goya_get_eeprom_data,
5746 .send_cpu_message = goya_send_cpu_message,
5747 .pci_bars_map = goya_pci_bars_map,
5748 .init_iatu = goya_init_iatu,
5751 .halt_coresight = goya_halt_coresight,
5752 .ctx_init = goya_ctx_init,
5753 .ctx_fini = goya_ctx_fini,
5754 .get_clk_rate = hl_get_clk_rate,
5755 .get_queue_id_for_cq = goya_get_queue_id_for_cq,
5756 .load_firmware_to_device = goya_load_firmware_to_device,
5757 .load_boot_fit_to_device = goya_load_boot_fit_to_device,
5758 .get_signal_cb_size = goya_get_signal_cb_size,
5759 .get_wait_cb_size = goya_get_wait_cb_size,
5760 .gen_signal_cb = goya_gen_signal_cb,
5761 .gen_wait_cb = goya_gen_wait_cb,
5762 .reset_sob = goya_reset_sob,
5763 .reset_sob_group = goya_reset_sob_group,
5764 .set_dma_mask_from_fw = goya_set_dma_mask_from_fw,
5765 .get_device_time = goya_get_device_time,
5766 .collective_wait_init_cs = goya_collective_wait_init_cs,
5767 .collective_wait_create_jobs = goya_collective_wait_create_jobs,
5768 .scramble_addr = hl_mmu_scramble_addr,
5769 .descramble_addr = hl_mmu_descramble_addr,
5770 .ack_protection_bits_errors = goya_ack_protection_bits_errors,
5771 .get_hw_block_id = goya_get_hw_block_id,
5772 .hw_block_mmap = goya_block_mmap,
5773 .enable_events_from_fw = goya_enable_events_from_fw,
5774 .map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx,
5775 .init_firmware_loader = goya_init_firmware_loader,
5776 .init_cpu_scrambler_dram = goya_cpu_init_scrambler_dram,
5777 .state_dump_init = goya_state_dump_init,
5778 .get_sob_addr = &goya_get_sob_addr,
5779 .set_pci_memory_regions = goya_set_pci_memory_regions,
5780 .get_stream_master_qid_arr = goya_get_stream_master_qid_arr,
5784 * goya_set_asic_funcs - set Goya function pointers
5786 * @*hdev: pointer to hl_device structure
5789 void goya_set_asic_funcs(struct hl_device *hdev)
5791 hdev->asic_funcs = &goya_funcs;